1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 NXP
4 */
5
6#include <common.h>
7#include <env.h>
8#include <init.h>
9#include <malloc.h>
10#include <errno.h>
11#include <asm/global_data.h>
12#include <asm/io.h>
13#include <miiphy.h>
14#include <netdev.h>
15#include <asm/mach-imx/iomux-v3.h>
16#include <asm-generic/gpio.h>
17#include <fsl_esdhc_imx.h>
18#include <mmc.h>
19#include <asm/arch/imx8mq_pins.h>
20#include <asm/arch/sys_proto.h>
21#include <asm/mach-imx/gpio.h>
22#include <asm/mach-imx/mxc_i2c.h>
23#include <asm/arch/clock.h>
24#include <linux/delay.h>
25#include <spl.h>
26#include <power/pmic.h>
27
28DECLARE_GLOBAL_DATA_PTR;
29
30#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
31
32#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
33
34static iomux_v3_cfg_t const wdog_pads[] = {
35	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
36};
37
38static iomux_v3_cfg_t const uart_pads[] = {
39	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
40	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
41};
42
43int board_early_init_f(void)
44{
45	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
46
47	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
48	set_wdog_reset(wdog);
49
50	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
51
52	return 0;
53}
54
55int board_phys_sdram_size(phys_size_t *size)
56{
57	int ddr_size = readl(MCU_BOOTROM_BASE_ADDR);
58
59	if (ddr_size == 0x4) {
60		*size = 0x100000000;
61	} else if (ddr_size == 0x3) {
62		*size = 0xc0000000;
63	} else if (ddr_size == 0x2) {
64		*size = 0x80000000;
65	} else if (ddr_size == 0x1) {
66		*size = 0x40000000;
67	} else {
68		printf("Unknown DDR type!!!\n");
69		return -1;
70	}
71
72	return 0;
73}
74
75#ifdef CONFIG_FEC_MXC
76#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
77#define FEC_PWR_PAD IMX_GPIO_NR(1, 0)
78static iomux_v3_cfg_t const fec1_pads[] = {
79	/* Reset */
80	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
81	/* Power */
82	IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
83};
84
85static void setup_iomux_fec(void)
86{
87	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
88
89	gpio_request(IMX_GPIO_NR(1, 0), "fec1_pwr");
90	gpio_direction_output(IMX_GPIO_NR(1, 0), 1);
91	udelay(500);
92
93	gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
94	gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
95	udelay(500);
96	gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
97}
98
99static int setup_fec(void)
100{
101	struct iomuxc_gpr_base_regs *gpr =
102		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
103
104	setup_iomux_fec();
105
106	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
107	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
108	return set_clk_enet(ENET_125MHZ);
109}
110
111int board_phy_config(struct phy_device *phydev)
112{
113	/* enable rgmii rxc skew and phy mode select to RGMII copper */
114	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
115	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
116
117	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
118	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
119
120	if (phydev->drv->config)
121		phydev->drv->config(phydev);
122	return 0;
123}
124#endif
125
126int board_init(void)
127{
128#ifdef CONFIG_FEC_MXC
129	setup_fec();
130#endif
131
132	return 0;
133}
134
135int board_mmc_get_env_dev(int devno)
136{
137	return devno;
138}
139
140int board_late_init(void)
141{
142#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
143	env_set("board_rev", "iMX8MQ");
144#endif
145	return 0;
146}
147