1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2021 NXP 4 */ 5 6#include <common.h> 7#include <clock_legacy.h> 8#include <display_options.h> 9#include <dm.h> 10#include <init.h> 11#include <asm/global_data.h> 12#include <dm/platform_data/serial_pl01x.h> 13#include <i2c.h> 14#include <malloc.h> 15#include <errno.h> 16#include <event.h> 17#include <netdev.h> 18#include <fsl_ddr.h> 19#include <asm/io.h> 20#include <fdt_support.h> 21#include <linux/bitops.h> 22#include <linux/libfdt.h> 23#include <linux/delay.h> 24#include <fsl-mc/fsl_mc.h> 25#include <env_internal.h> 26#include <efi_loader.h> 27#include <asm/arch/mmu.h> 28#include <hwconfig.h> 29#include <asm/arch/clock.h> 30#include <asm/arch/config.h> 31#include <asm/arch/fsl_serdes.h> 32#include <asm/arch/soc.h> 33#include "../common/i2c_mux.h" 34 35#include "../common/qixis.h" 36#include "../common/vid.h" 37#include <fsl_immap.h> 38#include <asm/arch-fsl-layerscape/fsl_icid.h> 39#include "lx2160a.h" 40 41#ifdef CONFIG_EMC2305 42#include "../common/emc2305.h" 43#endif 44 45#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 46#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value) 47#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f) 48#define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value) 49#define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value) 50#define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value) 51#define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value) 52#define SDHC1_BASE_PMUX_DSPI 2 53#define SDHC2_BASE_PMUX_DSPI 2 54#define IIC5_PMUX_SPI3 3 55#endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */ 56 57DECLARE_GLOBAL_DATA_PTR; 58 59int board_early_init_f(void) 60{ 61#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_SPL_BUILD) 62 i2c_early_init_f(); 63#endif 64 65#ifdef CONFIG_EMC2305 66 select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305, 0); 67 emc2305_init(I2C_EMC2305_ADDR); 68 set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR); 69 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); 70#endif 71 72 fsl_lsch3_early_init_f(); 73 return 0; 74} 75 76#ifdef CONFIG_OF_BOARD_FIXUP 77int board_fix_fdt(void *fdt) 78{ 79 char *reg_names, *reg_name; 80 int names_len, old_name_len, new_name_len, remaining_names_len; 81 struct str_map { 82 char *old_str; 83 char *new_str; 84 } reg_names_map[] = { 85 { "ccsr", "dbi" }, 86 { "pf_ctrl", "ctrl" } 87 }; 88 int off = -1, i = 0; 89 90 if (IS_SVR_REV(get_svr(), 1, 0)) 91 return 0; 92 93 fdt_for_each_node_by_compatible(off, fdt, -1, "fsl,lx2160a-pcie") { 94 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie", 95 strlen("fsl,ls-pcie") + 1); 96 97 reg_names = (char *)fdt_getprop(fdt, off, "reg-names", 98 &names_len); 99 if (!reg_names) 100 continue; 101 102 reg_name = reg_names; 103 remaining_names_len = names_len - (reg_name - reg_names); 104 i = 0; 105 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) { 106 old_name_len = strlen(reg_names_map[i].old_str); 107 new_name_len = strlen(reg_names_map[i].new_str); 108 if (memcmp(reg_name, reg_names_map[i].old_str, 109 old_name_len) == 0) { 110 /* first only leave required bytes for new_str 111 * and copy rest of the string after it 112 */ 113 memcpy(reg_name + new_name_len, 114 reg_name + old_name_len, 115 remaining_names_len - old_name_len); 116 /* Now copy new_str */ 117 memcpy(reg_name, reg_names_map[i].new_str, 118 new_name_len); 119 names_len -= old_name_len; 120 names_len += new_name_len; 121 i++; 122 } 123 124 reg_name = memchr(reg_name, '\0', remaining_names_len); 125 if (!reg_name) 126 break; 127 128 reg_name += 1; 129 130 remaining_names_len = names_len - 131 (reg_name - reg_names); 132 } 133 134 fdt_setprop(fdt, off, "reg-names", reg_names, names_len); 135 } 136 137 /* Fixup u-boot's DTS in case this is a revC board and 138 * we're using DM_ETH. 139 */ 140 if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB) && IS_ENABLED(CONFIG_DM_ETH)) 141 fdt_fixup_board_phy_revc(fdt); 142 return 0; 143} 144#endif 145 146#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 147void esdhc_dspi_status_fixup(void *blob) 148{ 149 const char esdhc0_path[] = "/soc/esdhc@2140000"; 150 const char esdhc1_path[] = "/soc/esdhc@2150000"; 151 const char dspi0_path[] = "/soc/spi@2100000"; 152 const char dspi1_path[] = "/soc/spi@2110000"; 153 const char dspi2_path[] = "/soc/spi@2120000"; 154 155 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); 156 u32 sdhc1_base_pmux; 157 u32 sdhc2_base_pmux; 158 u32 iic5_pmux; 159 160 /* Check RCW field sdhc1_base_pmux to enable/disable 161 * esdhc0/dspi0 DT node 162 */ 163 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) 164 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK; 165 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT; 166 167 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) { 168 do_fixup_by_path(blob, dspi0_path, "status", "okay", 169 sizeof("okay"), 1); 170 do_fixup_by_path(blob, esdhc0_path, "status", "disabled", 171 sizeof("disabled"), 1); 172 } else { 173 do_fixup_by_path(blob, esdhc0_path, "status", "okay", 174 sizeof("okay"), 1); 175 do_fixup_by_path(blob, dspi0_path, "status", "disabled", 176 sizeof("disabled"), 1); 177 } 178 179 /* Check RCW field sdhc2_base_pmux to enable/disable 180 * esdhc1/dspi1 DT node 181 */ 182 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) 183 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK; 184 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT; 185 186 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) { 187 do_fixup_by_path(blob, dspi1_path, "status", "okay", 188 sizeof("okay"), 1); 189 do_fixup_by_path(blob, esdhc1_path, "status", "disabled", 190 sizeof("disabled"), 1); 191 } else { 192 do_fixup_by_path(blob, esdhc1_path, "status", "okay", 193 sizeof("okay"), 1); 194 do_fixup_by_path(blob, dspi1_path, "status", "disabled", 195 sizeof("disabled"), 1); 196 } 197 198 /* Check RCW field IIC5 to enable dspi2 DT node */ 199 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) 200 & FSL_CHASSIS3_IIC5_PMUX_MASK; 201 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; 202 203 if (iic5_pmux == IIC5_PMUX_SPI3) 204 do_fixup_by_path(blob, dspi2_path, "status", "okay", 205 sizeof("okay"), 1); 206 else 207 do_fixup_by_path(blob, dspi2_path, "status", "disabled", 208 sizeof("disabled"), 1); 209} 210#endif 211 212int esdhc_status_fixup(void *blob, const char *compat) 213{ 214#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 215 /* Enable esdhc and dspi DT nodes based on RCW fields */ 216 esdhc_dspi_status_fixup(blob); 217#else 218 /* Enable both esdhc DT nodes for LX2160ARDB */ 219 do_fixup_by_compat(blob, compat, "status", "okay", 220 sizeof("okay"), 1); 221#endif 222 return 0; 223} 224 225#if defined(CONFIG_VID) 226int i2c_multiplexer_select_vid_channel(u8 channel) 227{ 228 return select_i2c_ch_pca9547(channel, 0); 229} 230 231int init_func_vid(void) 232{ 233 int set_vid; 234 235 if (IS_SVR_REV(get_svr(), 1, 0)) 236 set_vid = adjust_vdd(800); 237 else 238 set_vid = adjust_vdd(0); 239 240 if (set_vid < 0) 241 printf("core voltage not adjusted\n"); 242 243 return 0; 244} 245#endif 246EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, init_func_vid); 247 248int checkboard(void) 249{ 250 enum boot_src src = get_boot_src(); 251 char buf[64]; 252 u8 sw; 253#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 254 int clock; 255 static const char *const freq[] = {"100", "125", "156.25", 256 "161.13", "322.26", "", "", "", 257 "", "", "", "", "", "", "", 258 "100 separate SSCG"}; 259#endif 260 261 cpu_name(buf); 262#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 263 printf("Board: %s-QDS, ", buf); 264#else 265 printf("Board: %s-RDB, ", buf); 266#endif 267 268 sw = QIXIS_READ(arch); 269 printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A'); 270 271 if (src == BOOT_SOURCE_SD_MMC) { 272 puts("SD\n"); 273 } else if (src == BOOT_SOURCE_SD_MMC2) { 274 puts("eMMC\n"); 275 } else { 276 sw = QIXIS_READ(brdcfg[0]); 277 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; 278 switch (sw) { 279 case 0: 280 case 4: 281 puts("FlexSPI DEV#0\n"); 282 break; 283 case 1: 284 puts("FlexSPI DEV#1\n"); 285 break; 286 case 2: 287 case 3: 288 puts("FlexSPI EMU\n"); 289 break; 290 default: 291 printf("invalid setting, xmap: %d\n", sw); 292 break; 293 } 294 } 295#if defined(CONFIG_TARGET_LX2160ARDB) 296 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); 297 298 puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); 299 puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); 300 puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); 301#else 302 printf("FPGA: v%d (%s), build %d", 303 (int)QIXIS_READ(scver), qixis_read_tag(buf), 304 (int)qixis_read_minor()); 305 /* the timestamp string contains "\n" at the end */ 306 printf(" on %s", qixis_read_time(buf)); 307 308 puts("SERDES1 Reference : "); 309 sw = QIXIS_READ(brdcfg[2]); 310 clock = sw >> 4; 311 printf("Clock1 = %sMHz ", freq[clock]); 312#if defined(CONFIG_TARGET_LX2160AQDS) 313 clock = sw & 0x0f; 314 printf("Clock2 = %sMHz", freq[clock]); 315#endif 316 sw = QIXIS_READ(brdcfg[3]); 317 puts("\nSERDES2 Reference : "); 318 clock = sw >> 4; 319 printf("Clock1 = %sMHz ", freq[clock]); 320 clock = sw & 0x0f; 321 printf("Clock2 = %sMHz\n", freq[clock]); 322#if defined(CONFIG_TARGET_LX2160AQDS) 323 sw = QIXIS_READ(brdcfg[12]); 324 puts("SERDES3 Reference : "); 325 clock = sw >> 4; 326 printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); 327#endif 328#endif 329 return 0; 330} 331 332#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 333static void esdhc_adapter_card_ident(void) 334{ 335 u8 card_id, val; 336 337 val = QIXIS_READ(sdhc1); 338 card_id = val & QIXIS_SDID_MASK; 339 340 switch (card_id) { 341 case QIXIS_ESDHC_ADAPTER_TYPE_SD: 342 /* Power cycle to card */ 343 val &= ~QIXIS_SDHC1_S1V3; 344 QIXIS_WRITE(sdhc1, val); 345 mdelay(1); 346 val |= QIXIS_SDHC1_S1V3; 347 QIXIS_WRITE(sdhc1, val); 348 /* Route to SDHC1_VS */ 349 val = QIXIS_READ(brdcfg[11]); 350 val |= QIXIS_SDHC1_VS; 351 QIXIS_WRITE(brdcfg[11], val); 352 break; 353 default: 354 break; 355 } 356} 357 358int config_board_mux(void) 359{ 360 u8 reg11, reg5, reg13; 361 struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); 362 u32 sdhc1_base_pmux; 363 u32 sdhc2_base_pmux; 364 u32 iic5_pmux; 365 366 /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}. 367 * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}. 368 * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}. 369 * Qixis and remote systems are isolated from the I2C1 bus. 370 * Processor connections are still available. 371 * SPI2 CS2_B controls EN25S64 SPI memory device. 372 * SPI3 CS2_B controls EN25S64 SPI memory device. 373 * EC2 connects to PHY #2 using RGMII protocol. 374 * CLK_OUT connects to FPGA for clock measurement. 375 */ 376 377 reg5 = QIXIS_READ(brdcfg[5]); 378 reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40); 379 QIXIS_WRITE(brdcfg[5], reg5); 380 381 /* Check RCW field sdhc1_base_pmux 382 * esdhc0 : sdhc1_base_pmux = 0 383 * dspi0 : sdhc1_base_pmux = 2 384 */ 385 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) 386 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK; 387 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT; 388 389 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) { 390 reg11 = QIXIS_READ(brdcfg[11]); 391 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40); 392 QIXIS_WRITE(brdcfg[11], reg11); 393 } else { 394 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot. 395 * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot. 396 * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot. 397 */ 398 reg11 = QIXIS_READ(brdcfg[11]); 399 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11); 400 QIXIS_WRITE(brdcfg[11], reg11); 401 } 402 403 /* Check RCW field sdhc2_base_pmux 404 * esdhc1 : sdhc2_base_pmux = 0 (default) 405 * dspi1 : sdhc2_base_pmux = 2 406 */ 407 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1]) 408 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK; 409 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT; 410 411 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) { 412 reg13 = QIXIS_READ(brdcfg[13]); 413 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01); 414 QIXIS_WRITE(brdcfg[13], reg13); 415 } else { 416 reg13 = QIXIS_READ(brdcfg[13]); 417 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00); 418 QIXIS_WRITE(brdcfg[13], reg13); 419 } 420 421 /* Check RCW field IIC5 to enable dspi2 DT nodei 422 * dspi2: IIC5 = 3 423 */ 424 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1]) 425 & FSL_CHASSIS3_IIC5_PMUX_MASK; 426 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT; 427 428 if (iic5_pmux == IIC5_PMUX_SPI3) { 429 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */ 430 reg11 = QIXIS_READ(brdcfg[11]); 431 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10); 432 QIXIS_WRITE(brdcfg[11], reg11); 433 434 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere. 435 * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }. 436 * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}. 437 */ 438 reg11 = QIXIS_READ(brdcfg[11]); 439 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01); 440 QIXIS_WRITE(brdcfg[11], reg11); 441 } else { 442 /* 443 * If {SDHC1_DAT4} has been configured to route to SDHC1_VS, 444 * do not change it. 445 * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot. 446 */ 447 reg11 = QIXIS_READ(brdcfg[11]); 448 if ((reg11 & 0x30) != 0x30) { 449 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00); 450 QIXIS_WRITE(brdcfg[11], reg11); 451 } 452 453 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot. 454 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot. 455 * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot. 456 */ 457 reg11 = QIXIS_READ(brdcfg[11]); 458 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00); 459 QIXIS_WRITE(brdcfg[11], reg11); 460 } 461 462 return 0; 463} 464 465int board_early_init_r(void) 466{ 467 esdhc_adapter_card_ident(); 468 return 0; 469} 470#elif defined(CONFIG_TARGET_LX2160ARDB) 471int config_board_mux(void) 472{ 473 u8 brdcfg; 474 475 brdcfg = QIXIS_READ(brdcfg[4]); 476 /* The BRDCFG4 register controls general board configuration. 477 *|-------------------------------------------| 478 *|Field | Function | 479 *|-------------------------------------------| 480 *|5 | CAN I/O Enable (net CFG_CAN_EN_B):| 481 *|CAN_EN | 0= CAN transceivers are disabled. | 482 *| | 1= CAN transceivers are enabled. | 483 *|-------------------------------------------| 484 */ 485 brdcfg |= BIT_MASK(5); 486 QIXIS_WRITE(brdcfg[4], brdcfg); 487 488 return 0; 489} 490#else 491int config_board_mux(void) 492{ 493 return 0; 494} 495#endif 496 497#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) 498u8 get_board_rev(void) 499{ 500 u8 board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A'; 501 502 return board_rev; 503} 504#endif 505 506unsigned long get_board_sys_clk(void) 507{ 508#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 509 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 510 511 switch (sysclk_conf & 0x03) { 512 case QIXIS_SYSCLK_100: 513 return 100000000; 514 case QIXIS_SYSCLK_125: 515 return 125000000; 516 case QIXIS_SYSCLK_133: 517 return 133333333; 518 } 519 return 100000000; 520#else 521 return 100000000; 522#endif 523} 524 525unsigned long get_board_ddr_clk(void) 526{ 527#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) 528 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 529 530 switch ((ddrclk_conf & 0x30) >> 4) { 531 case QIXIS_DDRCLK_100: 532 return 100000000; 533 case QIXIS_DDRCLK_125: 534 return 125000000; 535 case QIXIS_DDRCLK_133: 536 return 133333333; 537 } 538 return 100000000; 539#else 540 return 100000000; 541#endif 542} 543 544int board_init(void) 545{ 546#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) 547 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; 548#endif 549 550 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); 551 552#if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) 553 /* invert AQR107 IRQ pins polarity */ 554 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); 555#endif 556 557#if !defined(CONFIG_SYS_EARLY_PCI_INIT) 558 pci_init(); 559#endif 560 return 0; 561} 562 563void detail_board_ddr_info(void) 564{ 565 int i; 566 u64 ddr_size = 0; 567 568 puts("\nDDR "); 569 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) 570 ddr_size += gd->bd->bi_dram[i].size; 571 print_size(ddr_size, ""); 572 print_ddr_info(0); 573} 574 575#ifdef CONFIG_MISC_INIT_R 576int misc_init_r(void) 577{ 578 config_board_mux(); 579 580 return 0; 581} 582#endif 583 584#ifdef CONFIG_VID 585u16 soc_get_fuse_vid(int vid_index) 586{ 587 static const u16 vdd[32] = { 588 8250, 589 7875, 590 7750, 591 0, /* reserved */ 592 0, /* reserved */ 593 0, /* reserved */ 594 0, /* reserved */ 595 0, /* reserved */ 596 0, /* reserved */ 597 0, /* reserved */ 598 0, /* reserved */ 599 0, /* reserved */ 600 0, /* reserved */ 601 0, /* reserved */ 602 0, /* reserved */ 603 0, /* reserved */ 604 8000, 605 8125, 606 8250, 607 0, /* reserved */ 608 8500, 609 0, /* reserved */ 610 0, /* reserved */ 611 0, /* reserved */ 612 0, /* reserved */ 613 0, /* reserved */ 614 0, /* reserved */ 615 0, /* reserved */ 616 0, /* reserved */ 617 0, /* reserved */ 618 0, /* reserved */ 619 0, /* reserved */ 620 }; 621 622 return vdd[vid_index]; 623}; 624#endif 625 626#ifdef CONFIG_FSL_MC_ENET 627 628void fdt_fixup_board_enet(void *fdt) 629{ 630 int offset; 631 632 offset = fdt_path_offset(fdt, "/soc/fsl-mc"); 633 634 if (offset < 0) 635 offset = fdt_path_offset(fdt, "/fsl-mc"); 636 637 if (offset < 0) { 638 printf("%s: fsl-mc node not found in device tree (error %d)\n", 639 __func__, offset); 640 return; 641 } 642 643 if (get_mc_boot_status() == 0 && 644 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { 645 fdt_status_okay(fdt, offset); 646 if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB)) 647 fdt_fixup_board_phy_revc(fdt); 648 } else { 649 fdt_status_fail(fdt, offset); 650 } 651} 652 653void board_quiesce_devices(void) 654{ 655 fsl_mc_ldpaa_exit(gd->bd); 656} 657#endif 658 659#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) 660int fdt_fixup_add_thermal(void *blob, int mux_node, int channel, int reg) 661{ 662 int err; 663 int noff; 664 int offset; 665 char channel_node_name[50]; 666 char thermal_node_name[50]; 667 u32 phandle; 668 669 snprintf(channel_node_name, sizeof(channel_node_name), 670 "i2c@%x", channel); 671 debug("channel_node_name = %s\n", channel_node_name); 672 673 snprintf(thermal_node_name, sizeof(thermal_node_name), 674 "temperature-sensor@%x", reg); 675 debug("thermal_node_name = %s\n", thermal_node_name); 676 677 err = fdt_increase_size(blob, 200); 678 if (err) { 679 printf("fdt_increase_size: err=%s\n", fdt_strerror(err)); 680 return err; 681 } 682 683 noff = fdt_subnode_offset(blob, mux_node, (const char *) 684 channel_node_name); 685 if (noff < 0) { 686 /* channel node not found - create it */ 687 noff = fdt_add_subnode(blob, mux_node, channel_node_name); 688 if (noff < 0) { 689 printf("fdt_add_subnode: err=%s\n", fdt_strerror(err)); 690 return err; 691 } 692 fdt_setprop_u32 (blob, noff, "#address-cells", 1); 693 fdt_setprop_u32 (blob, noff, "#size-cells", 0); 694 fdt_setprop_u32 (blob, noff, "reg", channel); 695 } 696 697 /* Create thermal node*/ 698 offset = fdt_add_subnode(blob, noff, thermal_node_name); 699 fdt_setprop(blob, offset, "compatible", "nxp,sa56004", 700 strlen("nxp,sa56004") + 1); 701 fdt_setprop_u32 (blob, offset, "reg", reg); 702 703 /* fixup phandle*/ 704 noff = fdt_node_offset_by_compatible(blob, -1, "regulator-fixed"); 705 if (noff < 0) { 706 printf("%s : failed to get phandle\n", __func__); 707 return noff; 708 } 709 phandle = fdt_get_phandle(blob, noff); 710 fdt_setprop_u32 (blob, offset, "vcc-supply", phandle); 711 712 return 0; 713} 714 715void fdt_fixup_delete_thermal(void *blob, int mux_node, int channel, int reg) 716{ 717 int node; 718 int value; 719 int err; 720 int subnode; 721 722 fdt_for_each_subnode(subnode, blob, mux_node) { 723 value = fdtdec_get_uint(blob, subnode, "reg", -1); 724 if (value == channel) { 725 /* delete thermal node */ 726 fdt_for_each_subnode(node, blob, subnode) { 727 value = fdtdec_get_uint(blob, node, "reg", -1); 728 err = fdt_node_check_compatible(blob, node, 729 "nxp,sa56004"); 730 if (!err && value == reg) { 731 fdt_del_node(blob, node); 732 break; 733 } 734 } 735 } 736 } 737} 738 739void fdt_fixup_i2c_thermal_node(void *blob) 740{ 741 int i2coffset; 742 int mux_node; 743 int reg; 744 int err; 745 746 i2coffset = fdt_node_offset_by_compat_reg(blob, "fsl,vf610-i2c", 747 0x2000000); 748 if (i2coffset != -FDT_ERR_NOTFOUND) { 749 fdt_for_each_subnode(mux_node, blob, i2coffset) { 750 reg = fdtdec_get_uint(blob, mux_node, "reg", -1); 751 err = fdt_node_check_compatible(blob, mux_node, 752 "nxp,pca9547"); 753 if (!err && reg == 0x77) { 754 fdt_fixup_delete_thermal(blob, mux_node, 755 0x3, 0x4d); 756 err = fdt_fixup_add_thermal(blob, mux_node, 757 0x3, 0x48); 758 if (err) 759 printf("%s: Add thermal node failed\n", 760 __func__); 761 } 762 } 763 } else { 764 printf("%s: i2c node not found\n", __func__); 765 } 766} 767#endif 768 769#ifdef CONFIG_OF_BOARD_SETUP 770int ft_board_setup(void *blob, struct bd_info *bd) 771{ 772 int i; 773 u16 mc_memory_bank = 0; 774 775 u64 *base; 776 u64 *size; 777 u64 mc_memory_base = 0; 778 u64 mc_memory_size = 0; 779 u16 total_memory_banks; 780 int err; 781 782 err = fdt_increase_size(blob, 512); 783 if (err) { 784 printf("%s fdt_increase_size: err=%s\n", __func__, 785 fdt_strerror(err)); 786 return err; 787 } 788 789 ft_cpu_setup(blob, bd); 790 791 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); 792 793 if (mc_memory_base != 0) 794 mc_memory_bank++; 795 796 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank; 797 798 base = calloc(total_memory_banks, sizeof(u64)); 799 size = calloc(total_memory_banks, sizeof(u64)); 800 801 /* fixup DT for the three GPP DDR banks */ 802 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 803 base[i] = gd->bd->bi_dram[i].start; 804 size[i] = gd->bd->bi_dram[i].size; 805 } 806 807#ifdef CONFIG_RESV_RAM 808 /* reduce size if reserved memory is within this bank */ 809 if (gd->arch.resv_ram >= base[0] && 810 gd->arch.resv_ram < base[0] + size[0]) 811 size[0] = gd->arch.resv_ram - base[0]; 812 else if (gd->arch.resv_ram >= base[1] && 813 gd->arch.resv_ram < base[1] + size[1]) 814 size[1] = gd->arch.resv_ram - base[1]; 815 else if (gd->arch.resv_ram >= base[2] && 816 gd->arch.resv_ram < base[2] + size[2]) 817 size[2] = gd->arch.resv_ram - base[2]; 818#endif 819 820 if (mc_memory_base != 0) { 821 for (i = 0; i <= total_memory_banks; i++) { 822 if (base[i] == 0 && size[i] == 0) { 823 base[i] = mc_memory_base; 824 size[i] = mc_memory_size; 825 break; 826 } 827 } 828 } 829 830 fdt_fixup_memory_banks(blob, base, size, total_memory_banks); 831 832#ifdef CONFIG_USB_HOST 833 fsl_fdt_fixup_dr_usb(blob, bd); 834#endif 835 836#ifdef CONFIG_FSL_MC_ENET 837 fdt_fsl_mc_fixup_iommu_map_entry(blob); 838 fdt_fixup_board_enet(blob); 839 fdt_reserve_mc_mem(blob, 0x4000); 840#endif 841 fdt_fixup_icid(blob); 842 843#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) 844 if (get_board_rev() == 'C') 845 fdt_fixup_i2c_thermal_node(blob); 846#endif 847 848 return 0; 849} 850#endif 851 852void qixis_dump_switch(void) 853{ 854 int i, nr_of_cfgsw; 855 856 QIXIS_WRITE(cms[0], 0x00); 857 nr_of_cfgsw = QIXIS_READ(cms[1]); 858 859 puts("DIP switch settings dump:\n"); 860 for (i = 1; i <= nr_of_cfgsw; i++) { 861 QIXIS_WRITE(cms[0], i); 862 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); 863 } 864} 865