Searched refs:clk_set_rate (Results 1 - 25 of 96) sorted by relevance
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| /u-boot/arch/arm/mach-nexell/include/mach/ |
| H A D | clk.h | 20 int clk_set_rate(struct clk *clk, unsigned long rate);
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| /u-boot/arch/arm/include/asm/kona-common/ |
| H A D | clk.h | 22 int clk_set_rate(struct clk *clk, unsigned long rate);
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| /u-boot/drivers/clk/imx/ |
| H A D | clk-imxrt1020.c | 138 clk_set_rate(clk, 480000000UL);
144 clk_set_rate(clk, 297000000UL);
148 clk_set_rate(clk, 528000000UL);
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| H A D | clk-imxrt1050.c | 192 clk_set_rate(clk, 1056000000UL);
203 clk_set_rate(clk, 528000000UL);
211 clk_set_rate(clk, 480000000UL);
219 clk_set_rate(clk, 650000000UL);
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| H A D | clk-imxrt1170.c | 43 return clk_set_rate(c, rate);
200 clk_set_rate(clk, 132000000UL);
204 clk_set_rate(clk, 32000000UL);
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| H A D | clk-gate2.c | 82 return clk_set_rate(parent, rate);
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| /u-boot/drivers/clk/tegra/ |
| H A D | tegra186-clk.c | 42 req.clk_set_rate.rate = rate;
49 return resp.clk_set_rate.rate;
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| /u-boot/drivers/clk/at91/ |
| H A D | pmc.c | 150 ret = clk_set_rate(parent, setup[i].prate);
157 ret = clk_set_rate(c, setup[i].rate);
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| /u-boot/board/synopsys/hsdk/ |
| H A D | clk-lib.c | 44 ret = clk_set_rate(&clk, priv_rate);
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| /u-boot/drivers/serial/ |
| H A D | serial_s5p4418_pl011.c | 63 rate_act = clk_set_rate(nx_clk, plat->clock);
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| /u-boot/drivers/mmc/ |
| H A D | uniphier-sd.c | 64 ret = clk_set_rate(&priv->clk, ULONG_MAX);
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| H A D | npcm_sdhci.c | 34 ret = clk_set_rate(&clk, host->max_clk);
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| /u-boot/arch/arm/cpu/armv7/bcm235xx/ |
| H A D | clk-sdio.c | 59 ret = clk_set_rate(c, rate);
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| /u-boot/arch/arm/cpu/armv7/bcm281xx/ |
| H A D | clk-sdio.c | 59 ret = clk_set_rate(c, rate);
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| /u-boot/board/google/veyron/ |
| H A D | veyron.c | 51 ret = clk_set_rate(&clk, 1800000000);
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| /u-boot/drivers/net/ |
| H A D | gmac_rockchip.c | 100 ret = clk_set_rate(&clk_speed, 2500000);
106 ret = clk_set_rate(&clk_speed, 25000000);
200 ret = clk_set_rate(&clk_speed, 2500000);
206 ret = clk_set_rate(&clk_speed, 25000000);
591 rate = clk_set_rate(&clk, 125000000);
607 rate = clk_set_rate(&clk, 125000000);
621 rate = clk_set_rate(&clk, 50000000);
636 rate = clk_set_rate(&clk, 125000000);
651 rate = clk_set_rate(&clk, 125000000);
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| /u-boot/drivers/clk/ti/ |
| H A D | clk-k3.c | 175 clk_set_rate(clk, ti_clk_data->default_freq);
290 new_rate = clk_set_rate(clkp, rate / div);
333 clk_set_rate(clkp, pll_tgt);
335 return clk_set_rate(clk, rate / div) * div;
348 new_rate = clk_set_rate(clkp, (rate / div) + rem);
352 new_rate = clk_set_rate(clkp, rate / div);
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| /u-boot/arch/arm/mach-mediatek/mt8516/ |
| H A D | init.c | 64 ret = clk_set_rate(&clk, pll_rates[i]);
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| /u-boot/drivers/timer/ |
| H A D | npcm-timer.c | 79 ret = clk_set_rate(&clk, NPCM_TIMER_INPUT_RATE);
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| /u-boot/drivers/video/rockchip/ |
| H A D | rk3288_hdmi.c | 70 ret = clk_set_rate(&clk, 384000000);
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| /u-boot/test/dm/ |
| H A D | clk_ccf.c | 68 rate = clk_set_rate(clk, 60000000);
95 rate = clk_set_rate(clk, 80000000);
119 rate = clk_set_rate(clk, 60000000);
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| /u-boot/drivers/sound/ |
| H A D | rockchip_sound.c | 95 ret = clk_set_rate(&clk, 12288000);
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| /u-boot/arch/arm/mach-mediatek/mt7629/ |
| H A D | init.c | 52 ret = clk_set_rate(&clk, pll_rates[i]);
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| /u-boot/drivers/ram/starfive/ |
| H A D | starfive_ddr.c | 119 ret = clk_set_rate(&priv->clk, rate);
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| /u-boot/drivers/clk/ |
| H A D | clk.c | 99 return clk_set_rate(c, rate);
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Completed in 436 milliseconds
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