1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2018 Synopsys, Inc. All rights reserved. 4 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 5 */ 6 7#include <clk.h> 8#include <log.h> 9#include <malloc.h> 10#include <dm/device.h> 11#include <linux/printk.h> 12 13#include "clk-lib.h" 14 15#define HZ_IN_MHZ 1000000 16#define ceil(x, y) ({ ulong __x = (x), __y = (y); (__x + __y - 1) / __y; }) 17 18int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl) 19{ 20 int ret; 21 ulong mhz_rate, priv_rate; 22 struct clk clk; 23 24 /* Dummy fmeas device, just to be able to use standard clk_* api */ 25 struct udevice fmeas = { 26 .name = "clk-fmeas", 27 }; 28 dev_set_ofnode(&fmeas, ofnode_path("/clk-fmeas")); 29 30 ret = clk_get_by_name(&fmeas, name, &clk); 31 if (ret) { 32 pr_err("clock '%s' not found, err=%d\n", name, ret); 33 return ret; 34 } 35 36 if (ctl & CLK_ON) { 37 ret = clk_enable(&clk); 38 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) 39 return ret; 40 } 41 42 if ((ctl & CLK_SET) && rate) { 43 priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate; 44 ret = clk_set_rate(&clk, priv_rate); 45 if (ret) 46 return ret; 47 } 48 49 if (ctl & CLK_OFF) { 50 ret = clk_disable(&clk); 51 if (ret) { 52 pr_err("clock '%s' can't be disabled, err=%d\n", name, ret); 53 return ret; 54 } 55 } 56 57 priv_rate = clk_get_rate(&clk); 58 59 mhz_rate = ceil(priv_rate, HZ_IN_MHZ); 60 61 if (ctl & CLK_MHZ) 62 priv_rate = mhz_rate; 63 64 if ((ctl & CLK_GET) && rate) 65 *rate = priv_rate; 66 67 if ((ctl & CLK_PRINT) && (ctl & CLK_MHZ)) 68 printf("HSDK: clock '%s' rate %lu MHz\n", name, priv_rate); 69 else if (ctl & CLK_PRINT) 70 printf("HSDK: clock '%s' rate %lu Hz\n", name, priv_rate); 71 else 72 debug("HSDK: clock '%s' rate %lu MHz\n", name, mhz_rate); 73 74 return 0; 75} 76