1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright(C) 2020 4 * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> 5 */ 6 7#include <common.h> 8#include <clk.h> 9#include <clk-uclass.h> 10#include <dm.h> 11#include <asm/arch/clock.h> 12#include <asm/arch/imx-regs.h> 13#include <dt-bindings/clock/imxrt1020-clock.h> 14 15#include "clk.h" 16 17static struct clk_ops imxrt1020_clk_ops = { 18 .set_rate = ccf_clk_set_rate, 19 .get_rate = ccf_clk_get_rate, 20 .enable = ccf_clk_enable, 21 .disable = ccf_clk_disable, 22}; 23 24static const char * const pll2_bypass_sels[] = {"pll2_sys", "osc", }; 25static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "osc", }; 26 27static const char *const pre_periph_sels[] = { "pll2_sys", "pll2_pfd3_297m", "pll3_pfd3_454_74m", "arm_podf", }; 28static const char *const periph_sels[] = { "pre_periph_sel", "todo", }; 29static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; 30static const char *const lpuart_sels[] = { "pll3_80m", "osc", }; 31static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; 32static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", }; 33 34static int imxrt1020_clk_probe(struct udevice *dev) 35{ 36 void *base; 37 38 /* Anatop clocks */ 39 base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(), "fsl,imxrt-anatop")); 40 41 clk_dm(IMXRT1020_CLK_PLL2_SYS, 42 imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc", 43 base + 0x30, 0x1)); 44 clk_dm(IMXRT1020_CLK_PLL3_USB_OTG, 45 imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", 46 base + 0x10, 0x1)); 47 48 /* PLL bypass out */ 49 clk_dm(IMXRT1020_CLK_PLL2_BYPASS, 50 imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, 51 pll2_bypass_sels, 52 ARRAY_SIZE(pll2_bypass_sels), 53 CLK_SET_RATE_PARENT)); 54 clk_dm(IMXRT1020_CLK_PLL3_BYPASS, 55 imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, 56 pll3_bypass_sels, 57 ARRAY_SIZE(pll3_bypass_sels), 58 CLK_SET_RATE_PARENT)); 59 60 clk_dm(IMXRT1020_CLK_PLL3_80M, 61 imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6)); 62 63 clk_dm(IMXRT1020_CLK_PLL2_PFD0_352M, 64 imx_clk_pfd("pll2_pfd0_352m", "pll2_sys", base + 0x100, 0)); 65 clk_dm(IMXRT1020_CLK_PLL2_PFD1_594M, 66 imx_clk_pfd("pll2_pfd1_594m", "pll2_sys", base + 0x100, 1)); 67 clk_dm(IMXRT1020_CLK_PLL2_PFD2_396M, 68 imx_clk_pfd("pll2_pfd2_396m", "pll2_sys", base + 0x100, 2)); 69 clk_dm(IMXRT1020_CLK_PLL2_PFD3_297M, 70 imx_clk_pfd("pll2_pfd3_297m", "pll2_sys", base + 0x100, 3)); 71 clk_dm(IMXRT1020_CLK_PLL3_PFD1_664_62M, 72 imx_clk_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", base + 0xf0, 1)); 73 clk_dm(IMXRT1020_CLK_PLL3_PFD3_454_74M, 74 imx_clk_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", base + 0xf0, 3)); 75 76 /* CCM clocks */ 77 base = dev_read_addr_ptr(dev); 78 if (base == (void *)FDT_ADDR_T_NONE) 79 return -EINVAL; 80 81 clk_dm(IMXRT1020_CLK_PRE_PERIPH_SEL, 82 imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, 83 pre_periph_sels, ARRAY_SIZE(pre_periph_sels))); 84 clk_dm(IMXRT1020_CLK_PERIPH_SEL, 85 imx_clk_mux("periph_sel", base + 0x14, 25, 1, 86 periph_sels, ARRAY_SIZE(periph_sels))); 87 clk_dm(IMXRT1020_CLK_USDHC1_SEL, 88 imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, 89 usdhc_sels, ARRAY_SIZE(usdhc_sels))); 90 clk_dm(IMXRT1020_CLK_USDHC2_SEL, 91 imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, 92 usdhc_sels, ARRAY_SIZE(usdhc_sels))); 93 clk_dm(IMXRT1020_CLK_LPUART_SEL, 94 imx_clk_mux("lpuart_sel", base + 0x24, 6, 1, 95 lpuart_sels, ARRAY_SIZE(lpuart_sels))); 96 clk_dm(IMXRT1020_CLK_SEMC_ALT_SEL, 97 imx_clk_mux("semc_alt_sel", base + 0x14, 7, 1, 98 semc_alt_sels, ARRAY_SIZE(semc_alt_sels))); 99 clk_dm(IMXRT1020_CLK_SEMC_SEL, 100 imx_clk_mux("semc_sel", base + 0x14, 6, 1, 101 semc_sels, ARRAY_SIZE(semc_sels))); 102 103 clk_dm(IMXRT1020_CLK_AHB_PODF, 104 imx_clk_divider("ahb_podf", "periph_sel", 105 base + 0x14, 10, 3)); 106 clk_dm(IMXRT1020_CLK_USDHC1_PODF, 107 imx_clk_divider("usdhc1_podf", "usdhc1_sel", 108 base + 0x24, 11, 3)); 109 clk_dm(IMXRT1020_CLK_USDHC2_PODF, 110 imx_clk_divider("usdhc2_podf", "usdhc2_sel", 111 base + 0x24, 16, 3)); 112 clk_dm(IMXRT1020_CLK_LPUART_PODF, 113 imx_clk_divider("lpuart_podf", "lpuart_sel", 114 base + 0x24, 0, 6)); 115 clk_dm(IMXRT1020_CLK_SEMC_PODF, 116 imx_clk_divider("semc_podf", "semc_sel", 117 base + 0x14, 16, 3)); 118 119 clk_dm(IMXRT1020_CLK_USDHC1, 120 imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2)); 121 clk_dm(IMXRT1020_CLK_USDHC2, 122 imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4)); 123 clk_dm(IMXRT1020_CLK_LPUART1, 124 imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24)); 125 clk_dm(IMXRT1020_CLK_SEMC, 126 imx_clk_gate2("semc", "semc_podf", base + 0x74, 4)); 127 128#ifdef CONFIG_SPL_BUILD 129 struct clk *clk, *clk1; 130 131 clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1); 132 clk_get_by_id(IMXRT1020_CLK_SEMC_ALT_SEL, &clk); 133 clk_set_parent(clk1, clk); 134 135 /* Configure PLL3_USB_OTG to 480MHz */ 136 clk_get_by_id(IMXRT1020_CLK_PLL3_USB_OTG, &clk); 137 clk_enable(clk); 138 clk_set_rate(clk, 480000000UL); 139 140 clk_get_by_id(IMXRT1020_CLK_PLL3_BYPASS, &clk1); 141 clk_set_parent(clk1, clk); 142 143 clk_get_by_id(IMXRT1020_CLK_PLL2_PFD3_297M, &clk); 144 clk_set_rate(clk, 297000000UL); 145 146 clk_get_by_id(IMXRT1020_CLK_PLL2_SYS, &clk); 147 clk_enable(clk); 148 clk_set_rate(clk, 528000000UL); 149 150 clk_get_by_id(IMXRT1020_CLK_PLL2_BYPASS, &clk1); 151 clk_set_parent(clk1, clk); 152 153#endif 154 155 return 0; 156} 157 158static const struct udevice_id imxrt1020_clk_ids[] = { 159 { .compatible = "fsl,imxrt1020-ccm" }, 160 { }, 161}; 162 163U_BOOT_DRIVER(imxrt1020_clk) = { 164 .name = "clk_imxrt1020", 165 .id = UCLASS_CLK, 166 .of_match = imxrt1020_clk_ids, 167 .ops = &imxrt1020_clk_ops, 168 .probe = imxrt1020_clk_probe, 169 .flags = DM_FLAG_PRE_RELOC, 170}; 171