/u-boot/board/sunxi/ |
H A D | gmac.c | 9 struct sunxi_ccm_reg *const ccm = local 14 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | 16 setbits_le32(&ccm->gmac_clk_cfg, 19 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
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/u-boot/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 21 struct sunxi_ccm_reg * const ccm = local 26 writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg); 27 writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg); 28 while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {} 31 writel(0x0, &ccm->cci400_cfg); 33 writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg); 37 clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK, 39 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); 40 while (!(readl(&ccm 52 struct sunxi_ccm_reg *const ccm = local 74 struct sunxi_ccm_reg * const ccm = local 108 struct sunxi_ccm_reg * const ccm = local 124 struct sunxi_ccm_reg *const ccm = local [all...] |
H A D | clock_sun9i.c | 22 struct sunxi_ccm_reg * const ccm = local 27 clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, 32 &ccm->pll2_c1_cfg); 37 clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK, 43 struct sunxi_ccm_reg * const ccm = local 47 &ccm->pll4_periph0_cfg); 54 struct sunxi_ccm_reg * const ccm = local 57 if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN) 61 &ccm->pll12_periph1_cfg); 68 struct sunxi_ccm_reg * const ccm local 115 struct sunxi_ccm_reg *const ccm = local 130 struct sunxi_ccm_reg * const ccm = local 157 struct sunxi_ccm_reg * const ccm = local 172 struct sunxi_ccm_reg *const ccm = local 198 struct sunxi_ccm_reg *const ccm = local [all...] |
H A D | clock_sun4i.c | 19 struct sunxi_ccm_reg * const ccm = local 27 &ccm->cpu_ahb_apb0_cfg); 29 writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); 35 &ccm->cpu_ahb_apb0_cfg); 38 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); 40 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); 42 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); 43 setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT); 49 struct sunxi_ccm_reg *const ccm = local 56 &ccm 65 struct sunxi_ccm_reg *const ccm = local 120 struct sunxi_ccm_reg * const ccm = local 183 struct sunxi_ccm_reg * const ccm = local 198 struct sunxi_ccm_reg *const ccm = local 207 struct sunxi_ccm_reg *const ccm = local 218 struct sunxi_ccm_reg *const ccm = local [all...] |
H A D | clock_sun6i.c | 22 struct sunxi_ccm_reg * const ccm = local 41 writel(GENMASK(12, 0), &ccm->pll_lock_ctrl); 46 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); 47 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) 50 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); 53 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); 55 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); 59 setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT); 60 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA); 61 setbits_le32(&ccm 69 struct sunxi_ccm_reg * const ccm = local 88 struct sunxi_ccm_reg *const ccm = local 128 struct sunxi_ccm_reg * const ccm = local 177 struct sunxi_ccm_reg * const ccm = local 199 struct sunxi_ccm_reg * const ccm = local 214 struct sunxi_ccm_reg * const ccm = local 246 struct sunxi_ccm_reg * const ccm = local 287 struct sunxi_ccm_reg * const ccm = local 311 struct sunxi_ccm_reg * const ccm = local 328 struct sunxi_ccm_reg *const ccm = local 340 struct sunxi_ccm_reg *const ccm = local 353 struct sunxi_ccm_reg *const ccm = local [all...] |
H A D | clock_sun50i_h6.c | 9 struct sunxi_ccm_reg *const ccm = local 35 writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg); 36 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK)) 39 clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK | CCM_CPU_AXI_AXI_MASK, 42 writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg); 44 writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg); 46 writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg); 52 writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg); 57 struct sunxi_ccm_reg *const ccm = local 64 &ccm 77 struct sunxi_ccm_reg * const ccm = local 109 struct sunxi_ccm_reg *const ccm = local 139 struct sunxi_ccm_reg *const ccm = local [all...] |
H A D | clock.c | 39 struct sunxi_ccm_reg *const ccm = local 54 setbits_le32(&ccm->apb2_gate, 56 setbits_le32(&ccm->apb2_reset_cfg, 59 clrbits_le32(&ccm->apb2_reset_cfg, 61 clrbits_le32(&ccm->apb2_gate,
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/u-boot/arch/m68k/cpu/mcf523x/ |
H A D | cpu.c | 25 ccm_t *ccm = (ccm_t *) MMAP_CCM; local 27 out_8(&ccm->rcr, CCM_RCR_SOFTRST); 35 ccm_t *ccm = (ccm_t *) MMAP_CCM; local 41 msk = (in_be16(&ccm->cir) >> 6); 42 ver = (in_be16(&ccm->cir) & 0x003f);
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/u-boot/board/tbs/tbs2910/ |
H A D | tbs2910.c | 76 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local 84 reg = readl(&ccm->analog_pll_video); 86 writel(reg, &ccm->analog_pll_video); 92 writel(reg, &ccm->analog_pll_video); 94 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); 95 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); 98 writel(reg, &ccm->analog_pll_video); 101 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) 106 reg = readl(&ccm->analog_pll_video); 109 writel(reg, &ccm [all...] |
/u-boot/board/toradex/colibri_vf/ |
H A D | colibri_vf.c | 220 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; local 224 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, 227 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK); 229 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, 231 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, 235 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, 237 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, 240 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, 242 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, 244 clrsetbits_le32(&ccm [all...] |
/u-boot/arch/m68k/cpu/mcf5445x/ |
H A D | speed.c | 32 ccm_t *ccm = (ccm_t *)MMAP_CCM; local 45 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); 54 ccm_t *ccm = (ccm_t *)MMAP_CCM; local 58 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); 68 ccm_t *ccm = (ccm_t *)MMAP_CCM; local 72 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14; 100 setbits_be16(&ccm->misccr2, 0x02); 113 if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */
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/u-boot/board/phytec/pcm052/ |
H A D | pcm052.c | 219 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; local 222 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, 224 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, 226 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, 231 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, 233 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, 236 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, 238 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, 240 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, 242 clrsetbits_le32(&ccm [all...] |
/u-boot/arch/arm/cpu/armv7/vf610/ |
H A D | generic.c | 34 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; local 37 reg = readl(&ccm->ccgr6); 42 writel(reg, &ccm->ccgr6); 48 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; local 53 ccm_ccsr = readl(&ccm->ccsr); 57 ccm_cacrr = readl(&ccm->cacrr); 112 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; local 115 ccm_cacrr = readl(&ccm->cacrr); 126 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; local 129 ccm_cacrr = readl(&ccm 145 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; local 178 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; local 391 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; local [all...] |
/u-boot/board/bsh/imx6ulz_smm_m2/ |
H A D | spl.c | 101 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local 103 writel(0xFFFFFFFF, &ccm->CCGR0); 104 writel(0xFFFFFFFF, &ccm->CCGR1); 105 writel(0xFFFFFFFF, &ccm->CCGR2); 106 writel(0xFFFFFFFF, &ccm->CCGR3); 107 writel(0xFFFFFFFF, &ccm->CCGR4); 108 writel(0xFFFFFFFF, &ccm->CCGR5); 109 writel(0xFFFFFFFF, &ccm->CCGR6);
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/u-boot/arch/m68k/cpu/mcf532x/ |
H A D | speed.c | 53 ccm_t *ccm = (ccm_t *)(MMAP_CCM); local 58 if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) { 59 divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF); 91 ccm_t *ccm = (ccm_t *)(MMAP_CCM); local 101 temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF)); 104 out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp)); 106 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); 114 ccm_t *ccm = (ccm_t *)(MMAP_CCM); local 118 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP); 121 while (!(in_be16(&ccm [all...] |
H A D | cpu.c | 38 ccm_t *ccm = (ccm_t *) MMAP_CCM; local 44 msk = (in_be16(&ccm->cir) >> 6); 45 ver = (in_be16(&ccm->cir) & 0x003f);
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/u-boot/arch/arm/mach-imx/mx6/ |
H A D | litesom.c | 152 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local 154 writel(0xFFFFFFFF, &ccm->CCGR0); 155 writel(0xFFFFFFFF, &ccm->CCGR1); 156 writel(0xFFFFFFFF, &ccm->CCGR2); 157 writel(0xFFFFFFFF, &ccm->CCGR3); 158 writel(0xFFFFFFFF, &ccm->CCGR4); 159 writel(0xFFFFFFFF, &ccm->CCGR5); 160 writel(0xFFFFFFFF, &ccm->CCGR6); 161 writel(0xFFFFFFFF, &ccm->CCGR7);
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H A D | opos6ul.c | 162 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local 164 writel(0xFFFFFFFF, &ccm->CCGR0); 165 writel(0xFFFFFFFF, &ccm->CCGR1); 166 writel(0xFFFFFFFF, &ccm->CCGR2); 167 writel(0xFFFFFFFF, &ccm->CCGR3); 168 writel(0xFFFFFFFF, &ccm->CCGR4); 169 writel(0xFFFFFFFF, &ccm->CCGR5); 170 writel(0xFFFFFFFF, &ccm->CCGR6); 171 writel(0xFFFFFFFF, &ccm->CCGR7);
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/u-boot/board/variscite/dart_6ul/ |
H A D | spl.c | 94 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local 96 writel(0xFFFFFFFF, &ccm->CCGR0); 97 writel(0xFFFFFFFF, &ccm->CCGR1); 98 writel(0xFFFFFFFF, &ccm->CCGR2); 99 writel(0xFFFFFFFF, &ccm->CCGR3); 100 writel(0xFFFFFFFF, &ccm->CCGR4); 101 writel(0xFFFFFFFF, &ccm->CCGR5); 102 writel(0xFFFFFFFF, &ccm->CCGR6); 103 writel(0xFFFFFFFF, &ccm->CCGR7);
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/u-boot/board/freescale/vf610twr/ |
H A D | vf610twr.c | 272 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; local 275 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, 277 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, 279 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, 284 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, 286 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, 289 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, 291 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, 293 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, 295 clrsetbits_le32(&ccm [all...] |
/u-boot/board/seeed/npi_imx6ull/ |
H A D | spl.c | 86 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local 88 writel(0xFFFFFFFF, &ccm->CCGR0); 89 writel(0xFFFFFFFF, &ccm->CCGR1); 90 writel(0xFFFFFFFF, &ccm->CCGR2); 91 writel(0xFFFFFFFF, &ccm->CCGR3); 92 writel(0xFFFFFFFF, &ccm->CCGR4); 93 writel(0xFFFFFFFF, &ccm->CCGR5); 94 writel(0xFFFFFFFF, &ccm->CCGR6);
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/u-boot/board/phytec/pcl063/ |
H A D | spl.c | 88 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local 90 writel(0xFFFFFFFF, &ccm->CCGR0); 91 writel(0xFFFFFFFF, &ccm->CCGR1); 92 writel(0xFFFFFFFF, &ccm->CCGR2); 93 writel(0xFFFFFFFF, &ccm->CCGR3); 94 writel(0xFFFFFFFF, &ccm->CCGR4); 95 writel(0xFFFFFFFF, &ccm->CCGR5); 96 writel(0xFFFFFFFF, &ccm->CCGR6);
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/u-boot/board/technexion/pico-imx6ul/ |
H A D | spl.c | 100 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local 102 writel(0xFFFFFFFF, &ccm->CCGR0); 103 writel(0xFFFFFFFF, &ccm->CCGR1); 104 writel(0xFFFFFFFF, &ccm->CCGR2); 105 writel(0xFFFFFFFF, &ccm->CCGR3); 106 writel(0xFFFFFFFF, &ccm->CCGR4); 107 writel(0xFFFFFFFF, &ccm->CCGR5); 108 writel(0xFFFFFFFF, &ccm->CCGR6);
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/u-boot/board/myir/mys_6ulx/ |
H A D | spl.c | 87 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local 89 writel(0xFFFFFFFF, &ccm->CCGR0); 90 writel(0xFFFFFFFF, &ccm->CCGR1); 91 writel(0xFFFFFFFF, &ccm->CCGR2); 92 writel(0xFFFFFFFF, &ccm->CCGR3); 93 writel(0xFFFFFFFF, &ccm->CCGR4); 94 writel(0xFFFFFFFF, &ccm->CCGR5); 95 writel(0xFFFFFFFF, &ccm->CCGR6);
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/u-boot/board/bticino/mamoj/ |
H A D | spl.c | 144 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; local 146 writel(0x00003f3f, &ccm->CCGR0); 147 writel(0x0030fc00, &ccm->CCGR1); 148 writel(0x000fc000, &ccm->CCGR2); 149 writel(0x3f300000, &ccm->CCGR3); 150 writel(0xff00f300, &ccm->CCGR4); 151 writel(0x0f0000c3, &ccm->CCGR5); 152 writel(0x000003cc, &ccm->CCGR6);
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