1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * sun6i specific clock code 4 * 5 * (C) Copyright 2007-2012 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 10 */ 11 12#include <asm/io.h> 13#include <asm/arch/clock.h> 14#include <asm/arch/prcm.h> 15#include <asm/arch/sys_proto.h> 16#include <linux/bitops.h> 17#include <linux/delay.h> 18 19#ifdef CONFIG_SPL_BUILD 20void clock_init_safe(void) 21{ 22 struct sunxi_ccm_reg * const ccm = 23 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 24 25#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) && \ 26 !defined(CONFIG_MACH_SUNIV) 27 struct sunxi_prcm_reg * const prcm = 28 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; 29 30 /* Set PLL ldo voltage without this PLL6 does not work properly */ 31 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, 32 PRCM_PLL_CTRL_LDO_KEY); 33 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, 34 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN | 35 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140)); 36 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); 37#endif 38 39#if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I) 40 /* Set PLL lock enable bits and switch to old lock mode */ 41 writel(GENMASK(12, 0), &ccm->pll_lock_ctrl); 42#endif 43 44 clock_set_pll1(408000000); 45 46 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); 47 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK)) 48 ; 49 50 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); 51 52 if (!IS_ENABLED(CONFIG_MACH_SUNIV)) { 53 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg); 54 if (IS_ENABLED(CONFIG_MACH_SUN6I)) 55 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg); 56 } 57 58#if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI) 59 setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT); 60 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA); 61 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA); 62 setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE); 63#endif 64} 65 66void clock_init_sec(void) 67{ 68#ifdef CONFIG_MACH_SUNXI_H3_H5 69 struct sunxi_ccm_reg * const ccm = 70 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 71 struct sunxi_prcm_reg * const prcm = 72 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; 73 74 setbits_le32(&ccm->ccu_sec_switch, 75 CCM_SEC_SWITCH_MBUS_NONSEC | 76 CCM_SEC_SWITCH_BUS_NONSEC | 77 CCM_SEC_SWITCH_PLL_NONSEC); 78 setbits_le32(&prcm->prcm_sec_switch, 79 PRCM_SEC_SWITCH_APB0_CLK_NONSEC | 80 PRCM_SEC_SWITCH_PLL_CFG_NONSEC | 81 PRCM_SEC_SWITCH_PWR_GATE_NONSEC); 82#endif 83} 84 85void clock_init_uart(void) 86{ 87#if CONFIG_CONS_INDEX < 5 88 struct sunxi_ccm_reg *const ccm = 89 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 90 91#ifdef CONFIG_MACH_SUNIV 92 /* suniv doesn't have apb2, UART clock source is always apb1 */ 93 94 /* open the clock for uart */ 95 setbits_le32(&ccm->apb1_gate, 96 CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT + 97 CONFIG_CONS_INDEX - 1)); 98 99 /* deassert uart reset */ 100 setbits_le32(&ccm->apb1_reset_cfg, 101 1 << (APB1_RESET_UART_SHIFT + 102 CONFIG_CONS_INDEX - 1)); 103#else 104 /* uart clock source is apb2 */ 105 writel(APB2_CLK_SRC_OSC24M| 106 APB2_CLK_RATE_N_1| 107 APB2_CLK_RATE_M(1), 108 &ccm->apb2_div); 109 110 /* open the clock for uart */ 111 setbits_le32(&ccm->apb2_gate, 112 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + 113 CONFIG_CONS_INDEX - 1)); 114 115 /* deassert uart reset */ 116 setbits_le32(&ccm->apb2_reset_cfg, 117 1 << (APB2_RESET_UART_SHIFT + 118 CONFIG_CONS_INDEX - 1)); 119#endif /* !CONFIG_MACH_SUNIV */ 120#else /* CONFIG_CONS_INDEX >= 5 */ 121 /* enable R_PIO and R_UART clocks, and de-assert resets */ 122 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); 123#endif 124} 125 126void clock_set_pll1(unsigned int clk) 127{ 128 struct sunxi_ccm_reg * const ccm = 129 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 130 const int p = 0; 131 int k = 1; 132 int m = 1; 133 134 if (clk > 1152000000) { 135 k = 2; 136 } else if (clk > 768000000) { 137 k = 4; 138 m = 2; 139 } 140 141 /* Switch to 24MHz clock while changing PLL1 */ 142 if (IS_ENABLED(CONFIG_MACH_SUNIV)) { 143 writel(CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, 144 &ccm->cpu_axi_cfg); 145 } else { 146 writel(AXI_DIV_3 << AXI_DIV_SHIFT | 147 ATB_DIV_2 << ATB_DIV_SHIFT | 148 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, 149 &ccm->cpu_axi_cfg); 150 } 151 152 /* 153 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored) 154 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m 155 */ 156 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | 157 CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) | 158 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg); 159 sdelay(200); 160 161 /* Switch CPU to PLL1 */ 162 if (IS_ENABLED(CONFIG_MACH_SUNIV)) { 163 writel(CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, 164 &ccm->cpu_axi_cfg); 165 } else { 166 writel(AXI_DIV_3 << AXI_DIV_SHIFT | 167 ATB_DIV_2 << ATB_DIV_SHIFT | 168 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, 169 &ccm->cpu_axi_cfg); 170 } 171} 172#endif /* CONFIG_SPL_BUILD */ 173 174/* video, DRAM, PLL_PERIPH clocks */ 175void clock_set_pll3(unsigned int clk) 176{ 177 struct sunxi_ccm_reg * const ccm = 178 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 179#ifdef CONFIG_SUNXI_DE2 180 const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */ 181#else 182 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */ 183#endif 184 185 if (clk == 0) { 186 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN); 187 return; 188 } 189 190 /* PLL3 rate = 24000000 * n / m */ 191 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | 192 CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m), 193 &ccm->pll3_cfg); 194} 195 196#ifdef CONFIG_SUNXI_DE2 197void clock_set_pll3_factors(int m, int n) 198{ 199 struct sunxi_ccm_reg * const ccm = 200 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 201 202 /* PLL3 rate = 24000000 * n / m */ 203 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE | 204 CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m), 205 &ccm->pll3_cfg); 206 207 while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK)) 208 ; 209} 210#endif 211 212void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) 213{ 214 struct sunxi_ccm_reg * const ccm = 215 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 216 const int max_n = 32; 217 int k = 1, m = 2; 218 219#ifdef CONFIG_MACH_SUNXI_H3_H5 220 clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK | 221 CCM_PLL5_TUN_INIT_FREQ_MASK, 222 CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16)); 223#endif 224 225 if (sigma_delta_enable) 226 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg); 227 228 /* PLL5 rate = 24000000 * n * k / m */ 229 if (clk > 24000000 * k * max_n / m) { 230 m = 1; 231 if (clk > 24000000 * k * max_n / m) 232 k = 2; 233 } 234 writel(CCM_PLL5_CTRL_EN | 235 (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) | 236 CCM_PLL5_CTRL_UPD | 237 CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) | 238 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); 239 240 udelay(5500); 241} 242 243#ifdef CONFIG_MACH_SUN6I 244void clock_set_mipi_pll(unsigned int clk) 245{ 246 struct sunxi_ccm_reg * const ccm = 247 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 248 unsigned int k, m, n, value, diff; 249 unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff; 250 unsigned int src = clock_get_pll3(); 251 252 /* All calculations are in KHz to avoid overflows */ 253 clk /= 1000; 254 src /= 1000; 255 256 /* Pick the closest lower clock */ 257 for (k = 1; k <= 4; k++) { 258 for (m = 1; m <= 16; m++) { 259 for (n = 1; n <= 16; n++) { 260 value = src * n * k / m; 261 if (value > clk) 262 continue; 263 264 diff = clk - value; 265 if (diff < best_diff) { 266 best_diff = diff; 267 best_k = k; 268 best_m = m; 269 best_n = n; 270 } 271 if (diff == 0) 272 goto done; 273 } 274 } 275 } 276 277done: 278 writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN | 279 CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) | 280 CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg); 281} 282#endif 283 284#ifdef CONFIG_SUNXI_DE2 285void clock_set_pll10(unsigned int clk) 286{ 287 struct sunxi_ccm_reg * const ccm = 288 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 289 const int m = 2; /* 12 MHz steps */ 290 291 if (clk == 0) { 292 clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN); 293 return; 294 } 295 296 /* PLL10 rate = 24000000 * n / m */ 297 writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE | 298 CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m), 299 &ccm->pll10_cfg); 300 301 while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK)) 302 ; 303} 304#endif 305 306#if defined(CONFIG_MACH_SUN8I_A33) || \ 307 defined(CONFIG_MACH_SUN8I_R40) || \ 308 defined(CONFIG_MACH_SUN50I) 309void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) 310{ 311 struct sunxi_ccm_reg * const ccm = 312 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 313 314 if (sigma_delta_enable) 315 writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0); 316 317 writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD | 318 (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) | 319 CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg); 320 321 while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD) 322 ; 323} 324#endif 325 326unsigned int clock_get_pll3(void) 327{ 328 struct sunxi_ccm_reg *const ccm = 329 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 330 uint32_t rval = readl(&ccm->pll3_cfg); 331 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1; 332 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1; 333 334 /* Multiply by 1000 after dividing by m to avoid integer overflows */ 335 return (24000 * n / m) * 1000; 336} 337 338unsigned int clock_get_pll6(void) 339{ 340 struct sunxi_ccm_reg *const ccm = 341 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 342 uint32_t rval = readl(&ccm->pll6_cfg); 343 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1; 344 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1; 345 if (IS_ENABLED(CONFIG_MACH_SUNIV)) 346 return 24000000 * n * k; 347 else 348 return 24000000 * n * k / 2; 349} 350 351unsigned int clock_get_mipi_pll(void) 352{ 353 struct sunxi_ccm_reg *const ccm = 354 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 355 uint32_t rval = readl(&ccm->mipi_pll_cfg); 356 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1; 357 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1; 358 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1; 359 unsigned int src = clock_get_pll3(); 360 361 /* Multiply by 1000 after dividing by m to avoid integer overflows */ 362 return ((src / 1000) * n * k / m) * 1000; 363} 364 365void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz) 366{ 367 int pll = clock_get_pll6() * 2; 368 int div = 1; 369 370 while ((pll / div) > hz) 371 div++; 372 373 writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div), 374 clk_cfg); 375} 376