1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * A83 specific clock code 4 * 5 * (C) Copyright 2007-2012 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> 10 */ 11 12#include <asm/io.h> 13#include <asm/arch/clock.h> 14#include <asm/arch/prcm.h> 15#include <asm/arch/sys_proto.h> 16#include <linux/delay.h> 17 18#ifdef CONFIG_SPL_BUILD 19void clock_init_safe(void) 20{ 21 struct sunxi_ccm_reg * const ccm = 22 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 23 24 clock_set_pll1(408000000); 25 /* enable pll_hsic, default is 480M */ 26 writel(PLL8_CFG_DEFAULT, &ccm->pll8_cfg); 27 writel(readl(&ccm->pll8_cfg) | (0x1 << 31), &ccm->pll8_cfg); 28 while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {} 29 30 /* switch to default 24MHz before changing to hsic */ 31 writel(0x0, &ccm->cci400_cfg); 32 sdelay(50); 33 writel(CCM_CCI400_CLK_SEL_HSIC, &ccm->cci400_cfg); 34 sdelay(100); 35 36 /* switch before changing pll6 */ 37 clrsetbits_le32(&ccm->ahb1_apb1_div, AHB1_CLK_SRC_MASK, 38 AHB1_CLK_SRC_OSC24M); 39 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); 40 while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {} 41 42 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div); 43 writel(CCM_MBUS_RESET_RESET, &ccm->mbus_reset); 44 writel(MBUS_CLK_DEFAULT, &ccm->mbus_clk_cfg); 45 46 /* timestamp */ 47 writel(1, 0x01720000); 48} 49 50void clock_init_uart(void) 51{ 52 struct sunxi_ccm_reg *const ccm = 53 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 54 55 /* uart clock source is apb2 */ 56 writel(APB2_CLK_SRC_OSC24M| 57 APB2_CLK_RATE_N_1| 58 APB2_CLK_RATE_M(1), 59 &ccm->apb2_div); 60 61 /* open the clock for uart */ 62 setbits_le32(&ccm->apb2_gate, 63 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT + 64 CONFIG_CONS_INDEX - 1)); 65 66 /* deassert uart reset */ 67 setbits_le32(&ccm->apb2_reset_cfg, 68 1 << (APB2_RESET_UART_SHIFT + 69 CONFIG_CONS_INDEX - 1)); 70} 71 72void clock_set_pll1(unsigned int clk) 73{ 74 struct sunxi_ccm_reg * const ccm = 75 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 76 const int p = 0; 77 78 /* Switch to 24MHz clock while changing PLL1 */ 79 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | 80 AXI_DIV_2 << AXI1_DIV_SHIFT | 81 CPU_CLK_SRC_OSC24M << C0_CPUX_CLK_SRC_SHIFT | 82 CPU_CLK_SRC_OSC24M << C1_CPUX_CLK_SRC_SHIFT, 83 &ccm->cpu_axi_cfg); 84 85 /* clk = 24*n/p, p is ignored if clock is >288MHz */ 86 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 | 87 CCM_PLL1_CTRL_N(clk / 24000000), 88 &ccm->pll1_c0_cfg); 89 while (!(readl(&ccm->pll_stable_status) & 0x01)) {} 90 91 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) | CMM_PLL1_CLOCK_TIME_2 | 92 CCM_PLL1_CTRL_N(clk / (24000000)), 93 &ccm->pll1_c1_cfg); 94 while (!(readl(&ccm->pll_stable_status) & 0x02)) {} 95 96 /* Switch CPU to PLL1 */ 97 writel(AXI_DIV_2 << AXI0_DIV_SHIFT | 98 AXI_DIV_2 << AXI1_DIV_SHIFT | 99 CPU_CLK_SRC_PLL1 << C0_CPUX_CLK_SRC_SHIFT | 100 CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT, 101 &ccm->cpu_axi_cfg); 102} 103#endif /* CONFIG_SPL_BUILD */ 104 105/* DRAM and PLL_PERIPH0 clock (used by the MMC driver) */ 106void clock_set_pll5(unsigned int clk) 107{ 108 struct sunxi_ccm_reg * const ccm = 109 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 110 unsigned int div1 = 0, div2 = 0; 111 112 /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */ 113 writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD | 114 CCM_PLL5_CTRL_N(clk / (24000000)) | 115 div2 << CCM_PLL5_DIV2_SHIFT | 116 div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg); 117 118 udelay(5500); 119} 120 121 122unsigned int clock_get_pll6(void) 123{ 124 struct sunxi_ccm_reg *const ccm = 125 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 126 127 uint32_t rval = readl(&ccm->pll6_cfg); 128 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT); 129 int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> 130 CCM_PLL6_CTRL_DIV1_SHIFT) + 1; 131 int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> 132 CCM_PLL6_CTRL_DIV2_SHIFT) + 1; 133 return 24000000 * n / div1 / div2; 134} 135