1// SPDX-License-Identifier: GPL-2.0+
2
3/*
4 * sun9i specific clock code
5 *
6 * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
7 *
8 * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
9 *                    Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
10 */
11
12#include <asm/io.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/prcm.h>
15#include <asm/arch/sys_proto.h>
16
17
18#ifdef CONFIG_SPL_BUILD
19
20static void clock_set_pll2(unsigned int clk)
21{
22	struct sunxi_ccm_reg * const ccm =
23		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
24	const int p = 0;
25
26	/* Switch cluster 1 to 24MHz clock while changing PLL2 */
27	clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,
28			C1_CPUX_CLK_SRC_OSC24M);
29
30	writel(CCM_PLL2_CTRL_EN | CCM_PLL2_CTRL_P(p) |
31	       CCM_PLL2_CLOCK_TIME_2 | CCM_PLL2_CTRL_N(clk / 24000000),
32	       &ccm->pll2_c1_cfg);
33
34	sdelay(2000);
35
36	/* Switch cluster 1 back to PLL2 */
37	clrsetbits_le32(&ccm->cpu_clk_source, C1_CPUX_CLK_SRC_MASK,
38			C1_CPUX_CLK_SRC_PLL2);
39}
40
41static void clock_set_pll4(unsigned int clk)
42{
43	struct sunxi_ccm_reg * const ccm =
44		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
45
46	writel(CCM_PLL4_CTRL_EN | CCM_PLL4_CTRL_N(clk / 24000000),
47	       &ccm->pll4_periph0_cfg);
48
49	sdelay(2000);
50}
51
52static void clock_set_pll12(unsigned int clk)
53{
54	struct sunxi_ccm_reg * const ccm =
55		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
56
57	if (readl(&ccm->pll12_periph1_cfg) & CCM_PLL12_CTRL_EN)
58		return;
59
60	writel(CCM_PLL12_CTRL_EN | CCM_PLL12_CTRL_N(clk / 24000000),
61	       &ccm->pll12_periph1_cfg);
62
63	sdelay(2000);
64}
65
66void clock_init_safe(void)
67{
68	struct sunxi_ccm_reg * const ccm =
69		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
70
71	/* Set up PLL12 (peripheral 1) */
72	clock_set_pll12(1200000000);
73
74	/* Set up PLL1 (cluster 0) and PLL2 (cluster 1) */
75	clock_set_pll1(408000000);
76	clock_set_pll2(408000000);
77
78	/* Set up PLL4 (peripheral 0) */
79	clock_set_pll4(960000000);
80
81	/* Set up dividers for AXI0 and APB0 on cluster 0: PLL1 / 2 = 204MHz */
82	writel(C0_CFG_AXI0_CLK_DIV_RATIO(2) |
83	       C0_CFG_APB0_CLK_DIV_RATIO(2), &ccm->c0_cfg);
84
85	/* AHB0: 120 MHz (PLL_PERIPH0 / 8) */
86	writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(8),
87	       &ccm->ahb0_cfg);
88	/* AHB1: 240 MHz (PLL_PERIPH0 / 4) */
89	writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(4),
90	       &ccm->ahb1_cfg);
91	/* AHB2: 120 MHz (PLL_PERIPH0 / 8) */
92	writel(AHBx_SRC_PLL_PERIPH0 | AHBx_CLK_DIV_RATIO(8),
93	       &ccm->ahb2_cfg);
94	/* APB0: 120 MHz (PLL_PERIPH0 / 8) */
95	writel(APB0_SRC_PLL_PERIPH0 | APB0_CLK_DIV_RATIO(8),
96	       &ccm->apb0_cfg);
97
98	/* GTBUS: 400MHz (PERIPH0 div 3) */
99	writel(GTBUS_SRC_PLL_PERIPH1 | GTBUS_CLK_DIV_RATIO(3),
100	       &ccm->gtbus_cfg);
101	/* CCI400: 480MHz (PERIPH1 div 2) */
102	writel(CCI400_SRC_PLL_PERIPH0 | CCI400_CLK_DIV_RATIO(2),
103	       &ccm->cci400_cfg);
104
105	/* Deassert DMA reset and open clock gating for DMA */
106	setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24));
107	setbits_le32(&ccm->apb1_gate, (1 << 24));
108
109	/* set enable-bit in TSTAMP_CTRL_REG */
110	writel(1, 0x01720000);
111}
112
113void clock_init_uart(void)
114{
115	struct sunxi_ccm_reg *const ccm =
116		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
117
118	/* open the clock for uart */
119	setbits_le32(&ccm->apb1_gate,
120		     CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
121				       CONFIG_CONS_INDEX - 1));
122	/* deassert uart reset */
123	setbits_le32(&ccm->apb1_reset_cfg,
124		     1 << (APB1_RESET_UART_SHIFT +
125			   CONFIG_CONS_INDEX - 1));
126}
127
128void clock_set_pll1(unsigned int clk)
129{
130	struct sunxi_ccm_reg * const ccm =
131		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
132	const int p = 0;
133
134	/* Switch cluster 0 to 24MHz clock while changing PLL1 */
135	clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK,
136			C0_CPUX_CLK_SRC_OSC24M);
137
138	writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
139	       CCM_PLL1_CLOCK_TIME_2 |
140	       CCM_PLL1_CTRL_N(clk / 24000000),
141	       &ccm->pll1_c0_cfg);
142	/*
143	 * Don't bother with the stable-time registers, as it doesn't
144	 * wait until the PLL is stable.  Note, that even Allwinner
145	 * just uses a delay loop (or rather the AVS timer) for this
146	 * instead of the PLL_STABLE_STATUS register.
147	 */
148	sdelay(2000);
149
150	/* Switch cluster 0 back to PLL1 */
151	clrsetbits_le32(&ccm->cpu_clk_source, C0_CPUX_CLK_SRC_MASK,
152			C0_CPUX_CLK_SRC_PLL1);
153}
154
155void clock_set_pll6(unsigned int clk)
156{
157	struct sunxi_ccm_reg * const ccm =
158		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
159	const int p = 0;
160
161	writel(CCM_PLL6_CTRL_EN | CCM_PLL6_CFG_UPDATE | CCM_PLL6_CTRL_P(p)
162	       | CCM_PLL6_CTRL_N(clk / 24000000),
163	       &ccm->pll6_ddr_cfg);
164	do { } while (!(readl(&ccm->pll_stable_status) & PLL_DDR_STATUS));
165
166	sdelay(2000);
167}
168
169
170int clock_twi_onoff(int port, int state)
171{
172	struct sunxi_ccm_reg *const ccm =
173		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
174
175	if (port > 4)
176		return -1;
177
178	/* set the apb reset and clock gate for twi */
179	if (state) {
180		setbits_le32(&ccm->apb1_gate,
181			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
182		setbits_le32(&ccm->apb1_reset_cfg,
183			     1 << (APB1_RESET_TWI_SHIFT + port));
184	} else {
185		clrbits_le32(&ccm->apb1_reset_cfg,
186			     1 << (APB1_RESET_TWI_SHIFT + port));
187		clrbits_le32(&ccm->apb1_gate,
188			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
189	}
190
191	return 0;
192}
193#endif /* CONFIG_SPL_BUILD */
194
195/* PLL_PERIPH0 clock (used by the MMC driver) */
196unsigned int clock_get_pll4_periph0(void)
197{
198	struct sunxi_ccm_reg *const ccm =
199		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
200	uint32_t rval = readl(&ccm->pll4_periph0_cfg);
201	int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT);
202	int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT);
203	int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1;
204	const int k = 1;
205
206	return ((24000000 * n * k) >> p) / m;
207}
208