Searched refs:DCRN_MAL_BASE (Results 1 - 17 of 17) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-ppc/
H A Dibm403.h343 #ifdef DCRN_MAL_BASE
344 #define DCRN_MALCR (DCRN_MAL_BASE + 0x0) /* MAL Configuration */
345 #define DCRN_MALDBR (DCRN_MAL_BASE + 0x3) /* Debug Register */
346 #define DCRN_MALESR (DCRN_MAL_BASE + 0x1) /* Error Status */
347 #define DCRN_MALIER (DCRN_MAL_BASE + 0x2) /* Interrupt Enable */
348 #define DCRN_MALTXCARR (DCRN_MAL_BASE + 0x5) /* TX Channed Active Reset Register */
349 #define DCRN_MALTXCASR (DCRN_MAL_BASE + 0x4) /* TX Channel Active Set Register */
350 #define DCRN_MALTXDEIR (DCRN_MAL_BASE + 0x7) /* Tx Descriptor Error Interrupt */
351 #define DCRN_MALTXEOBISR (DCRN_MAL_BASE + 0x6) /* Tx End of Buffer Interrupt Status */
352 #define DCRN_MALRXCARR (DCRN_MAL_BASE
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H A Dibm44x.h198 #define DCRN_MAL_BASE 0x180 macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/ppc/boot/simple/
H A Dmisc.c108 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR);
110 while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {};
H A Dembed_config.c785 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); /* 1st reset MAL */
786 while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for the reset */
853 mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); /* 1st reset MAL */
854 while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for the reset */
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/ppc/platforms/4xx/
H A Dibm405gp.c48 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
H A Dibm405gpr.c42 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
H A Dibm440sp.c43 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
H A Dibm405ep.c33 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
H A Dibm405ep.h133 #define DCRN_MAL_BASE 0x180 macro
H A Dibm405gp.h136 #define DCRN_MAL_BASE 0x180 macro
H A Dibm405gpr.h136 #define DCRN_MAL_BASE 0x180 macro
H A Dibm440gp.c57 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
H A Dibmnp405h.c73 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
H A Dppc440spe.c47 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
H A Dibm440ep.c55 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
H A Dibm440gx.c83 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
H A Dibmnp405h.h122 #define DCRN_MAL_BASE 0x180 macro

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