1/* 2 * Authors: Armin Kuster <akuster@mvista.com> and Tom Rini <trini@mvista.com> 3 * 4 * 2001 (c) MontaVista, Software, Inc. This file is licensed under 5 * the terms of the GNU General Public License version 2. This program 6 * is licensed "as is" without any warranty of any kind, whether express 7 * or implied. 8 */ 9 10 11#ifdef __KERNEL__ 12#ifndef __ASM_IBM403_H__ 13#define __ASM_IBM403_H__ 14 15 16#if defined(CONFIG_403GCX) 17 18#define DCRN_BE_BASE 0x090 19#define DCRN_DMA0_BASE 0x0C0 20#define DCRN_DMA1_BASE 0x0C8 21#define DCRN_DMA2_BASE 0x0D0 22#define DCRN_DMA3_BASE 0x0D8 23#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */ 24#define DCRN_DMASR_BASE 0x0E0 25 26#define DCRN_EXIER_BASE 0x042 27#define DCRN_EXISR_BASE 0x040 28#define DCRN_IOCR_BASE 0x0A0 29 30 31/* ------------------------------------------------------------------------- */ 32#endif 33 34 35 36#ifdef DCRN_BE_BASE 37#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ 38#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register*/ 39#endif 40/* DCRN_BESR */ 41#define BESR_DSES 0x80000000 /* Data-Side Error Status */ 42#define BESR_DMES 0x40000000 /* DMA Error Status */ 43#define BESR_RWS 0x20000000 /* Read/Write Status */ 44#define BESR_ETMASK 0x1C000000 /* Error Type */ 45#define ET_PROT 0 46#define ET_PARITY 1 47#define ET_NCFG 2 48#define ET_BUSERR 4 49#define ET_BUSTO 6 50 51#ifdef DCRN_CHCR_BASE 52#define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */ 53#define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */ 54#endif 55#define CHR1_CETE 0x00800000 /* CPU external timer enable */ 56#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ 57 58#ifdef DCRN_CHPSR_BASE 59#define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */ 60#endif 61 62#ifdef DCRN_CIC_BASE 63#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */ 64#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */ 65#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */ 66#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */ 67#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */ 68#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */ 69#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */ 70#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */ 71#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */ 72#endif 73 74#ifdef DCRN_CPMFR_BASE 75#define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */ 76#endif 77 78#ifndef CPM_AUD 79#define CPM_AUD 0x00000000 80#endif 81#ifndef CPM_BRG 82#define CPM_BRG 0x00000000 83#endif 84#ifndef CPM_CBS 85#define CPM_CBS 0x00000000 86#endif 87#ifndef CPM_CPU 88#define CPM_CPU 0x00000000 89#endif 90#ifndef CPM_DCP 91#define CPM_DCP 0x00000000 92#endif 93#ifndef CPM_DCRX 94#define CPM_DCRX 0x00000000 95#endif 96#ifndef CPM_DENC 97#define CPM_DENC 0x00000000 98#endif 99#ifndef CPM_DMA 100#define CPM_DMA 0x00000000 101#endif 102#ifndef CPM_DSCR 103#define CPM_DSCR 0x00000000 104#endif 105#ifndef CPM_EBC 106#define CPM_EBC 0x00000000 107#endif 108#ifndef CPM_EBIU 109#define CPM_EBIU 0x00000000 110#endif 111#ifndef CPM_EMAC_MM 112#define CPM_EMAC_MM 0x00000000 113#endif 114#ifndef CPM_EMAC_RM 115#define CPM_EMAC_RM 0x00000000 116#endif 117#ifndef CPM_EMAC_TM 118#define CPM_EMAC_TM 0x00000000 119#endif 120#ifndef CPM_GPIO0 121#define CPM_GPIO0 0x00000000 122#endif 123#ifndef CPM_GPT 124#define CPM_GPT 0x00000000 125#endif 126#ifndef CPM_I1284 127#define CPM_I1284 0x00000000 128#endif 129#ifndef CPM_IIC0 130#define CPM_IIC0 0x00000000 131#endif 132#ifndef CPM_IIC1 133#define CPM_IIC1 0x00000000 134#endif 135#ifndef CPM_MSI 136#define CPM_MSI 0x00000000 137#endif 138#ifndef CPM_PCI 139#define CPM_PCI 0x00000000 140#endif 141#ifndef CPM_PLB 142#define CPM_PLB 0x00000000 143#endif 144#ifndef CPM_SC0 145#define CPM_SC0 0x00000000 146#endif 147#ifndef CPM_SC1 148#define CPM_SC1 0x00000000 149#endif 150#ifndef CPM_SDRAM0 151#define CPM_SDRAM0 0x00000000 152#endif 153#ifndef CPM_SDRAM1 154#define CPM_SDRAM1 0x00000000 155#endif 156#ifndef CPM_TMRCLK 157#define CPM_TMRCLK 0x00000000 158#endif 159#ifndef CPM_UART0 160#define CPM_UART0 0x00000000 161#endif 162#ifndef CPM_UART1 163#define CPM_UART1 0x00000000 164#endif 165#ifndef CPM_UART2 166#define CPM_UART2 0x00000000 167#endif 168#ifndef CPM_UIC 169#define CPM_UIC 0x00000000 170#endif 171#ifndef CPM_VID2 172#define CPM_VID2 0x00000000 173#endif 174#ifndef CPM_XPT27 175#define CPM_XPT27 0x00000000 176#endif 177#ifndef CPM_XPT54 178#define CPM_XPT54 0x00000000 179#endif 180 181#ifdef DCRN_CPMSR_BASE 182#define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */ 183#define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */ 184#endif 185 186#ifdef DCRN_DCP0_BASE 187#define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) /* Decompression Controller Address */ 188#define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) /* Decompression Controller Data */ 189#endif 190 191#ifdef DCRN_DCRX_BASE 192#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */ 193#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */ 194#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */ 195#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */ 196#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */ 197#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */ 198#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */ 199#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */ 200#endif 201 202#ifdef DCRN_DMA0_BASE 203#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control Register 0 */ 204#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */ 205#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) /* DMA Destination Address Register 0 */ 206#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Source Address Register 0 */ 207#ifdef DCRNCAP_DMA_CC 208#define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) /* DMA Chained Count Register 0 */ 209#endif 210 211#ifdef DCRNCAP_DMA_SG 212#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 0 */ 213#endif 214#endif 215 216#ifdef DCRN_DMA1_BASE 217#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control Register 1 */ 218#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */ 219#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) /* DMA Destination Address Register 1 */ 220#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */ 221 222#ifdef DCRNCAP_DMA_CC 223#define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) /* DMA Chained Count Register 1 */ 224#endif 225#ifdef DCRNCAP_DMA_SG 226#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 1 */ 227#endif 228#endif 229 230#ifdef DCRN_DMA2_BASE 231#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */ 232#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */ 233#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */ 234#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */ 235#ifdef DCRNCAP_DMA_CC 236#define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */ 237#endif 238#ifdef DCRNCAP_DMA_SG 239#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */ 240#endif 241#endif 242 243#ifdef DCRN_DMA3_BASE 244#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */ 245#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */ 246#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */ 247#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */ 248#ifdef DCRNCAP_DMA_CC 249#define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */ 250#endif 251#ifdef DCRNCAP_DMA_SG 252#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */ 253#endif 254#endif 255 256#ifdef DCRN_DMASR_BASE 257#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ 258#ifdef DCRNCAP_DMA_SG 259#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ 260/* don't know if these two registers always exist if scatter/gather exists */ 261#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ 262#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ 263#endif 264#endif 265 266#ifdef DCRN_EBC_BASE 267#define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */ 268#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */ 269#endif 270 271#ifdef DCRN_EXIER_BASE 272#define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */ 273#endif 274 275#ifdef DCRN_EBIMC_BASE 276#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */ 277#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */ 278#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */ 279#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */ 280#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */ 281#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */ 282#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */ 283#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */ 284#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10)/* BRC 0 */ 285#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11)/* BRC 1 */ 286#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12)/* BRC 2 */ 287#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13)/* BRC 3 */ 288#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14)/* BRC 4 */ 289#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15)/* BRC 5 */ 290#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16)/* BRC 6 */ 291#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17)/* BRC 7 */ 292#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20)/* Bus Error Address Register */ 293#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21)/* Bus Error Status Register */ 294#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A)/* Bus Interfac Unit Ctrl Reg */ 295#endif 296 297#ifdef DCRN_EXISR_BASE 298#define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */ 299#endif 300#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ 301#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ 302#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ 303#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ 304#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ 305#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ 306#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ 307#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ 308#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ 309#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ 310#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ 311#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ 312#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ 313#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ 314 315#ifdef DCRN_IOCR_BASE 316#define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */ 317#endif 318#define IOCR_E0TE 0x80000000 319#define IOCR_E0LP 0x40000000 320#define IOCR_E1TE 0x20000000 321#define IOCR_E1LP 0x10000000 322#define IOCR_E2TE 0x08000000 323#define IOCR_E2LP 0x04000000 324#define IOCR_E3TE 0x02000000 325#define IOCR_E3LP 0x01000000 326#define IOCR_E4TE 0x00800000 327#define IOCR_E4LP 0x00400000 328#define IOCR_EDT 0x00080000 329#define IOCR_SOR 0x00040000 330#define IOCR_EDO 0x00008000 331#define IOCR_2XC 0x00004000 332#define IOCR_ATC 0x00002000 333#define IOCR_SPD 0x00001000 334#define IOCR_BEM 0x00000800 335#define IOCR_PTD 0x00000400 336#define IOCR_ARE 0x00000080 337#define IOCR_DRC 0x00000020 338#define IOCR_RDM(x) (((x) & 0x3) << 3) 339#define IOCR_TCS 0x00000004 340#define IOCR_SCS 0x00000002 341#define IOCR_SPC 0x00000001 342 343#ifdef DCRN_MAL_BASE 344#define DCRN_MALCR (DCRN_MAL_BASE + 0x0) /* MAL Configuration */ 345#define DCRN_MALDBR (DCRN_MAL_BASE + 0x3) /* Debug Register */ 346#define DCRN_MALESR (DCRN_MAL_BASE + 0x1) /* Error Status */ 347#define DCRN_MALIER (DCRN_MAL_BASE + 0x2) /* Interrupt Enable */ 348#define DCRN_MALTXCARR (DCRN_MAL_BASE + 0x5) /* TX Channed Active Reset Register */ 349#define DCRN_MALTXCASR (DCRN_MAL_BASE + 0x4) /* TX Channel Active Set Register */ 350#define DCRN_MALTXDEIR (DCRN_MAL_BASE + 0x7) /* Tx Descriptor Error Interrupt */ 351#define DCRN_MALTXEOBISR (DCRN_MAL_BASE + 0x6) /* Tx End of Buffer Interrupt Status */ 352#define DCRN_MALRXCARR (DCRN_MAL_BASE + 0x11) /* RX Channed Active Reset Register */ 353#define DCRN_MALRXCASR (DCRN_MAL_BASE + 0x10) /* RX Channel Active Set Register */ 354#define DCRN_MALRXDEIR (DCRN_MAL_BASE + 0x13) /* Rx Descriptor Error Interrupt */ 355#define DCRN_MALRXEOBISR (DCRN_MAL_BASE + 0x12) /* Rx End of Buffer Interrupt Status */ 356#define DCRN_MALRXCTP0R (DCRN_MAL_BASE + 0x40) /* Channel Rx 0 Channel Table Pointer */ 357#define DCRN_MALTXCTP0R (DCRN_MAL_BASE + 0x20) /* Channel Tx 0 Channel Table Pointer */ 358#define DCRN_MALTXCTP1R (DCRN_MAL_BASE + 0x21) /* Channel Tx 1 Channel Table Pointer */ 359#define DCRN_MALRCBS0 (DCRN_MAL_BASE + 0x60) /* Channel Rx 0 Channel Buffer Size */ 360#endif 361/* DCRN_MALCR */ 362#define MALCR_MMSR 0x80000000/* MAL Software reset */ 363#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ 364#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ 365#define MALCR_PLBP_3 0x00C00000 /* highest */ 366#define MALCR_GA 0x00200000 /* Guarded Active Bit */ 367#define MALCR_OA 0x00100000 /* Ordered Active Bit */ 368#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ 369#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ 370#define MALCR_PLBLT_2 0x00020000 371#define MALCR_PLBLT_3 0x00010000 372#define MALCR_PLBLT_4 0x00008000 373#define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ 374#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ 375#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ 376#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ 377#define MALCR_LEA 0x00000002 /* Locked Error Active */ 378#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ 379/* DCRN_MALESR */ 380#define MALESR_EVB 0x80000000 /* Error Valid Bit */ 381#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ 382#define MALESR_DE 0x00100000 /* Descriptor Error */ 383#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ 384#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ 385#define MALESR_OSE 0x00020000 /* OPB Slave Error */ 386#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ 387#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ 388#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ 389#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ 390#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ 391#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ 392/* DCRN_MALIER */ 393#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ 394#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ 395#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ 396#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ 397#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ 398/* DCRN_MALTXEOBISR */ 399#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ 400#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ 401 402#ifdef DCRN_OCM0_BASE 403#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ 404#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ 405#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ 406#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ 407#endif 408 409#ifdef DCRN_PLB0_BASE 410#define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0) 411#define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2) 412/* doesn't exist on stb03xxx? */ 413#define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3) 414#endif 415 416#ifdef DCRN_PLB1_BASE 417#define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0) 418#define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1) 419/* doesn't exist on stb03xxx? */ 420#define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2) 421#endif 422 423#ifdef DCRN_PLLMR_BASE 424#define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */ 425#endif 426 427#ifdef DCRN_POB0_BASE 428#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0) 429#define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2) 430#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4) 431#endif 432 433#ifdef DCRN_SCCR_BASE 434#define DCRN_SCCR (DCRN_SCCR_BASE + 0x0) 435#endif 436 437#ifdef DCRN_SDRAM0_BASE 438#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Mem Ctrlr Address */ 439#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Mem Ctrlr Data */ 440#endif 441 442#ifdef DCRN_UIC0_BASE 443#define DCRN_UIC0_SR (DCRN_UIC0_BASE + 0x0) 444#define DCRN_UIC0_ER (DCRN_UIC0_BASE + 0x2) 445#define DCRN_UIC0_CR (DCRN_UIC0_BASE + 0x3) 446#define DCRN_UIC0_PR (DCRN_UIC0_BASE + 0x4) 447#define DCRN_UIC0_TR (DCRN_UIC0_BASE + 0x5) 448#define DCRN_UIC0_MSR (DCRN_UIC0_BASE + 0x6) 449#define DCRN_UIC0_VR (DCRN_UIC0_BASE + 0x7) 450#define DCRN_UIC0_VCR (DCRN_UIC0_BASE + 0x8) 451#endif 452 453#ifdef DCRN_UIC1_BASE 454#define DCRN_UIC1_SR (DCRN_UIC1_BASE + 0x0) 455#define DCRN_UIC1_SRS (DCRN_UIC1_BASE + 0x1) 456#define DCRN_UIC1_ER (DCRN_UIC1_BASE + 0x2) 457#define DCRN_UIC1_CR (DCRN_UIC1_BASE + 0x3) 458#define DCRN_UIC1_PR (DCRN_UIC1_BASE + 0x4) 459#define DCRN_UIC1_TR (DCRN_UIC1_BASE + 0x5) 460#define DCRN_UIC1_MSR (DCRN_UIC1_BASE + 0x6) 461#define DCRN_UIC1_VR (DCRN_UIC1_BASE + 0x7) 462#define DCRN_UIC1_VCR (DCRN_UIC1_BASE + 0x8) 463#endif 464 465#ifdef DCRN_SDRAM0_BASE 466#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */ 467#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */ 468#endif 469 470#ifdef DCRN_OCM0_BASE 471#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ 472#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ 473#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ 474#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ 475#endif 476 477#endif /* __ASM_IBM403_H__ */ 478#endif /* __KERNEL__ */ 479