1/* 2 * PPC440GP I/O descriptions 3 * 4 * Matt Porter <mporter@mvista.com> 5 * Copyright 2002-2004 MontaVista Software Inc. 6 * 7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 8 * Copyright (c) 2003, 2004 Zultys Technologies 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16#include <linux/init.h> 17#include <linux/module.h> 18#include <platforms/4xx/ibm440gp.h> 19#include <asm/ocp.h> 20#include <asm/ppc4xx_pic.h> 21 22static struct ocp_func_emac_data ibm440gp_emac0_def = { 23 .rgmii_idx = -1, /* No RGMII */ 24 .rgmii_mux = -1, /* No RGMII */ 25 .zmii_idx = 0, /* ZMII device index */ 26 .zmii_mux = 0, /* ZMII input of this EMAC */ 27 .mal_idx = 0, /* MAL device index */ 28 .mal_rx_chan = 0, /* MAL rx channel number */ 29 .mal_tx_chan = 0, /* MAL tx channel number */ 30 .wol_irq = 61, /* WOL interrupt number */ 31 .mdio_idx = -1, /* No shared MDIO */ 32 .tah_idx = -1, /* No TAH */ 33}; 34 35static struct ocp_func_emac_data ibm440gp_emac1_def = { 36 .rgmii_idx = -1, /* No RGMII */ 37 .rgmii_mux = -1, /* No RGMII */ 38 .zmii_idx = 0, /* ZMII device index */ 39 .zmii_mux = 1, /* ZMII input of this EMAC */ 40 .mal_idx = 0, /* MAL device index */ 41 .mal_rx_chan = 1, /* MAL rx channel number */ 42 .mal_tx_chan = 2, /* MAL tx channel number */ 43 .wol_irq = 63, /* WOL interrupt number */ 44 .mdio_idx = -1, /* No shared MDIO */ 45 .tah_idx = -1, /* No TAH */ 46}; 47OCP_SYSFS_EMAC_DATA() 48 49static struct ocp_func_mal_data ibm440gp_mal0_def = { 50 .num_tx_chans = 4, /* Number of TX channels */ 51 .num_rx_chans = 2, /* Number of RX channels */ 52 .txeob_irq = 10, /* TX End Of Buffer IRQ */ 53 .rxeob_irq = 11, /* RX End Of Buffer IRQ */ 54 .txde_irq = 33, /* TX Descriptor Error IRQ */ 55 .rxde_irq = 34, /* RX Descriptor Error IRQ */ 56 .serr_irq = 32, /* MAL System Error IRQ */ 57 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ 58}; 59OCP_SYSFS_MAL_DATA() 60 61static struct ocp_func_iic_data ibm440gp_iic0_def = { 62 .fast_mode = 0, /* Use standad mode (100Khz) */ 63}; 64 65static struct ocp_func_iic_data ibm440gp_iic1_def = { 66 .fast_mode = 0, /* Use standad mode (100Khz) */ 67}; 68OCP_SYSFS_IIC_DATA() 69 70struct ocp_def core_ocp[] = { 71 { .vendor = OCP_VENDOR_IBM, 72 .function = OCP_FUNC_OPB, 73 .index = 0, 74 .paddr = 0x0000000140000000ULL, 75 .irq = OCP_IRQ_NA, 76 .pm = OCP_CPM_NA, 77 }, 78 { .vendor = OCP_VENDOR_IBM, 79 .function = OCP_FUNC_16550, 80 .index = 0, 81 .paddr = PPC440GP_UART0_ADDR, 82 .irq = UART0_INT, 83 .pm = IBM_CPM_UART0, 84 }, 85 { .vendor = OCP_VENDOR_IBM, 86 .function = OCP_FUNC_16550, 87 .index = 1, 88 .paddr = PPC440GP_UART1_ADDR, 89 .irq = UART1_INT, 90 .pm = IBM_CPM_UART1, 91 }, 92 { .vendor = OCP_VENDOR_IBM, 93 .function = OCP_FUNC_IIC, 94 .index = 0, 95 .paddr = 0x0000000140000400ULL, 96 .irq = 2, 97 .pm = IBM_CPM_IIC0, 98 .additions = &ibm440gp_iic0_def, 99 .show = &ocp_show_iic_data 100 }, 101 { .vendor = OCP_VENDOR_IBM, 102 .function = OCP_FUNC_IIC, 103 .index = 1, 104 .paddr = 0x0000000140000500ULL, 105 .irq = 3, 106 .pm = IBM_CPM_IIC1, 107 .additions = &ibm440gp_iic1_def, 108 .show = &ocp_show_iic_data 109 }, 110 { .vendor = OCP_VENDOR_IBM, 111 .function = OCP_FUNC_GPIO, 112 .index = 0, 113 .paddr = 0x0000000140000700ULL, 114 .irq = OCP_IRQ_NA, 115 .pm = IBM_CPM_GPIO0, 116 }, 117 { .vendor = OCP_VENDOR_IBM, 118 .function = OCP_FUNC_MAL, 119 .paddr = OCP_PADDR_NA, 120 .irq = OCP_IRQ_NA, 121 .pm = OCP_CPM_NA, 122 .additions = &ibm440gp_mal0_def, 123 .show = &ocp_show_mal_data, 124 }, 125 { .vendor = OCP_VENDOR_IBM, 126 .function = OCP_FUNC_EMAC, 127 .index = 0, 128 .paddr = 0x0000000140000800ULL, 129 .irq = 60, 130 .pm = OCP_CPM_NA, 131 .additions = &ibm440gp_emac0_def, 132 .show = &ocp_show_emac_data, 133 }, 134 { .vendor = OCP_VENDOR_IBM, 135 .function = OCP_FUNC_EMAC, 136 .index = 1, 137 .paddr = 0x0000000140000900ULL, 138 .irq = 62, 139 .pm = OCP_CPM_NA, 140 .additions = &ibm440gp_emac1_def, 141 .show = &ocp_show_emac_data, 142 }, 143 { .vendor = OCP_VENDOR_IBM, 144 .function = OCP_FUNC_ZMII, 145 .paddr = 0x0000000140000780ULL, 146 .irq = OCP_IRQ_NA, 147 .pm = OCP_CPM_NA, 148 }, 149 { .vendor = OCP_VENDOR_INVALID 150 } 151}; 152 153/* Polarity and triggering settings for internal interrupt sources */ 154struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { 155 { .polarity = 0xfffffe03, 156 .triggering = 0x01c00000, 157 .ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */ 158 }, 159 { .polarity = 0xffffc0ff, 160 .triggering = 0x00ff8000, 161 .ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */ 162 }, 163}; 164