1/* 2 * PPC440SPe I/O descriptions 3 * 4 * Roland Dreier <rolandd@cisco.com> 5 * Copyright (c) 2005 Cisco Systems. All rights reserved. 6 * 7 * Matt Porter <mporter@kernel.crashing.org> 8 * Copyright 2002-2005 MontaVista Software Inc. 9 * 10 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 11 * Copyright (c) 2003, 2004 Zultys Technologies 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 */ 19#include <linux/init.h> 20#include <linux/module.h> 21#include <platforms/4xx/ppc440spe.h> 22#include <asm/ocp.h> 23#include <asm/ppc4xx_pic.h> 24 25static struct ocp_func_emac_data ppc440spe_emac0_def = { 26 .rgmii_idx = -1, /* No RGMII */ 27 .rgmii_mux = -1, /* No RGMII */ 28 .zmii_idx = -1, /* No ZMII */ 29 .zmii_mux = -1, /* No ZMII */ 30 .mal_idx = 0, /* MAL device index */ 31 .mal_rx_chan = 0, /* MAL rx channel number */ 32 .mal_tx_chan = 0, /* MAL tx channel number */ 33 .wol_irq = 61, /* WOL interrupt number */ 34 .mdio_idx = -1, /* No shared MDIO */ 35 .tah_idx = -1, /* No TAH */ 36}; 37OCP_SYSFS_EMAC_DATA() 38 39static struct ocp_func_mal_data ppc440spe_mal0_def = { 40 .num_tx_chans = 1, /* Number of TX channels */ 41 .num_rx_chans = 1, /* Number of RX channels */ 42 .txeob_irq = 38, /* TX End Of Buffer IRQ */ 43 .rxeob_irq = 39, /* RX End Of Buffer IRQ */ 44 .txde_irq = 34, /* TX Descriptor Error IRQ */ 45 .rxde_irq = 35, /* RX Descriptor Error IRQ */ 46 .serr_irq = 33, /* MAL System Error IRQ */ 47 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ 48}; 49OCP_SYSFS_MAL_DATA() 50 51static struct ocp_func_iic_data ppc440spe_iic0_def = { 52 .fast_mode = 0, /* Use standad mode (100Khz) */ 53}; 54 55static struct ocp_func_iic_data ppc440spe_iic1_def = { 56 .fast_mode = 0, /* Use standad mode (100Khz) */ 57}; 58OCP_SYSFS_IIC_DATA() 59 60struct ocp_def core_ocp[] = { 61 { .vendor = OCP_VENDOR_IBM, 62 .function = OCP_FUNC_16550, 63 .index = 0, 64 .paddr = PPC440SPE_UART0_ADDR, 65 .irq = UART0_INT, 66 .pm = IBM_CPM_UART0, 67 }, 68 { .vendor = OCP_VENDOR_IBM, 69 .function = OCP_FUNC_16550, 70 .index = 1, 71 .paddr = PPC440SPE_UART1_ADDR, 72 .irq = UART1_INT, 73 .pm = IBM_CPM_UART1, 74 }, 75 { .vendor = OCP_VENDOR_IBM, 76 .function = OCP_FUNC_16550, 77 .index = 2, 78 .paddr = PPC440SPE_UART2_ADDR, 79 .irq = UART2_INT, 80 .pm = IBM_CPM_UART2, 81 }, 82 { .vendor = OCP_VENDOR_IBM, 83 .function = OCP_FUNC_IIC, 84 .index = 0, 85 .paddr = 0x00000004f0000400ULL, 86 .irq = 2, 87 .pm = IBM_CPM_IIC0, 88 .additions = &ppc440spe_iic0_def, 89 .show = &ocp_show_iic_data 90 }, 91 { .vendor = OCP_VENDOR_IBM, 92 .function = OCP_FUNC_IIC, 93 .index = 1, 94 .paddr = 0x00000004f0000500ULL, 95 .irq = 3, 96 .pm = IBM_CPM_IIC1, 97 .additions = &ppc440spe_iic1_def, 98 .show = &ocp_show_iic_data 99 }, 100 { .vendor = OCP_VENDOR_IBM, 101 .function = OCP_FUNC_GPIO, 102 .index = 0, 103 .paddr = 0x00000004f0000700ULL, 104 .irq = OCP_IRQ_NA, 105 .pm = IBM_CPM_GPIO0, 106 }, 107 { .vendor = OCP_VENDOR_IBM, 108 .function = OCP_FUNC_MAL, 109 .paddr = OCP_PADDR_NA, 110 .irq = OCP_IRQ_NA, 111 .pm = OCP_CPM_NA, 112 .additions = &ppc440spe_mal0_def, 113 .show = &ocp_show_mal_data, 114 }, 115 { .vendor = OCP_VENDOR_IBM, 116 .function = OCP_FUNC_EMAC, 117 .index = 0, 118 .paddr = 0x00000004f0000800ULL, 119 .irq = 60, 120 .pm = OCP_CPM_NA, 121 .additions = &ppc440spe_emac0_def, 122 .show = &ocp_show_emac_data, 123 }, 124 { .vendor = OCP_VENDOR_INVALID 125 } 126}; 127 128/* Polarity and triggering settings for internal interrupt sources */ 129struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { 130 { .polarity = 0xffffffff, 131 .triggering = 0x010f0004, 132 .ext_irq_mask = 0x00000000, 133 }, 134 { .polarity = 0xffffffff, 135 .triggering = 0x001f8040, 136 .ext_irq_mask = 0x00007c30, /* IRQ6 - IRQ7, IRQ8 - IRQ12 */ 137 }, 138 { .polarity = 0xffffffff, 139 .triggering = 0x00000000, 140 .ext_irq_mask = 0x000000fc, /* IRQ0 - IRQ5 */ 141 }, 142 { .polarity = 0xffffffff, 143 .triggering = 0x00000000, 144 .ext_irq_mask = 0x00000000, 145 }, 146}; 147