1/* 2 * 3 * Copyright 2000-2001 MontaVista Software Inc. 4 * Original author: Armin Kuster akuster@mvista.com 5 * 6 * Module name: ibm405gp.c 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 */ 15 16#include <linux/init.h> 17#include <linux/smp.h> 18#include <linux/threads.h> 19#include <linux/param.h> 20#include <linux/string.h> 21#include <platforms/4xx/ibm405gp.h> 22#include <asm/ibm4xx.h> 23#include <asm/ocp.h> 24#include <asm/ppc4xx_pic.h> 25 26static struct ocp_func_emac_data ibm405gp_emac0_def = { 27 .rgmii_idx = -1, /* No RGMII */ 28 .rgmii_mux = -1, /* No RGMII */ 29 .zmii_idx = -1, /* ZMII device index */ 30 .zmii_mux = 0, /* ZMII input of this EMAC */ 31 .mal_idx = 0, /* MAL device index */ 32 .mal_rx_chan = 0, /* MAL rx channel number */ 33 .mal_tx_chan = 0, /* MAL tx channel number */ 34 .wol_irq = 9, /* WOL interrupt number */ 35 .mdio_idx = -1, /* No shared MDIO */ 36 .tah_idx = -1, /* No TAH */ 37}; 38OCP_SYSFS_EMAC_DATA() 39 40static struct ocp_func_mal_data ibm405gp_mal0_def = { 41 .num_tx_chans = 1, /* Number of TX channels */ 42 .num_rx_chans = 1, /* Number of RX channels */ 43 .txeob_irq = 11, /* TX End Of Buffer IRQ */ 44 .rxeob_irq = 12, /* RX End Of Buffer IRQ */ 45 .txde_irq = 13, /* TX Descriptor Error IRQ */ 46 .rxde_irq = 14, /* RX Descriptor Error IRQ */ 47 .serr_irq = 10, /* MAL System Error IRQ */ 48 .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ 49}; 50OCP_SYSFS_MAL_DATA() 51 52static struct ocp_func_iic_data ibm405gp_iic0_def = { 53 .fast_mode = 0, /* Use standad mode (100Khz) */ 54}; 55OCP_SYSFS_IIC_DATA() 56 57struct ocp_def core_ocp[] = { 58 { .vendor = OCP_VENDOR_IBM, 59 .function = OCP_FUNC_OPB, 60 .index = 0, 61 .paddr = 0xEF600000, 62 .irq = OCP_IRQ_NA, 63 .pm = OCP_CPM_NA, 64 }, 65 { .vendor = OCP_VENDOR_IBM, 66 .function = OCP_FUNC_16550, 67 .index = 0, 68 .paddr = UART0_IO_BASE, 69 .irq = UART0_INT, 70 .pm = IBM_CPM_UART0 71 }, 72 { .vendor = OCP_VENDOR_IBM, 73 .function = OCP_FUNC_16550, 74 .index = 1, 75 .paddr = UART1_IO_BASE, 76 .irq = UART1_INT, 77 .pm = IBM_CPM_UART1 78 }, 79 { .vendor = OCP_VENDOR_IBM, 80 .function = OCP_FUNC_IIC, 81 .paddr = 0xEF600500, 82 .irq = 2, 83 .pm = IBM_CPM_IIC0, 84 .additions = &ibm405gp_iic0_def, 85 .show = &ocp_show_iic_data, 86 }, 87 { .vendor = OCP_VENDOR_IBM, 88 .function = OCP_FUNC_GPIO, 89 .paddr = 0xEF600700, 90 .irq = OCP_IRQ_NA, 91 .pm = IBM_CPM_GPIO0 92 }, 93 { .vendor = OCP_VENDOR_IBM, 94 .function = OCP_FUNC_MAL, 95 .paddr = OCP_PADDR_NA, 96 .irq = OCP_IRQ_NA, 97 .pm = OCP_CPM_NA, 98 .additions = &ibm405gp_mal0_def, 99 .show = &ocp_show_mal_data, 100 }, 101 { .vendor = OCP_VENDOR_IBM, 102 .function = OCP_FUNC_EMAC, 103 .index = 0, 104 .paddr = EMAC0_BASE, 105 .irq = 15, 106 .pm = IBM_CPM_EMAC0, 107 .additions = &ibm405gp_emac0_def, 108 .show = &ocp_show_emac_data, 109 }, 110 { .vendor = OCP_VENDOR_INVALID 111 } 112}; 113 114/* Polarity and triggering settings for internal interrupt sources */ 115struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { 116 { .polarity = 0xffffff80, 117 .triggering = 0x10000000, 118 .ext_irq_mask = 0x0000007f, /* IRQ0 - IRQ6 */ 119 } 120}; 121