1/*
2 * Author: Armin Kuster <akuster@mvista.com>
3 *
4 * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
5 * the terms of the GNU General Public License version 2.  This program
6 * is licensed "as is" without any warranty of any kind, whether express
7 * or implied.
8 */
9
10#include <linux/init.h>
11#include <asm/ocp.h>
12#include <platforms/4xx/ibmnp405h.h>
13
14static struct ocp_func_emac_data ibmnp405h_emac0_def = {
15	.rgmii_idx	= -1,		/* No RGMII */
16	.rgmii_mux	= -1,		/* No RGMII */
17	.zmii_idx	= 0,		/* ZMII device index */
18	.zmii_mux	= 0,		/* ZMII input of this EMAC */
19	.mal_idx	= 0,		/* MAL device index */
20	.mal_rx_chan	= 0,		/* MAL rx channel number */
21	.mal_tx_chan	= 0,		/* MAL tx channel number */
22	.wol_irq	= 41,		/* WOL interrupt number */
23	.mdio_idx	= -1,		/* No shared MDIO */
24	.tah_idx	= -1,		/* No TAH */
25};
26
27static struct ocp_func_emac_data ibmnp405h_emac1_def = {
28	.rgmii_idx	= -1,		/* No RGMII */
29	.rgmii_mux	= -1,		/* No RGMII */
30	.zmii_idx	= 0,		/* ZMII device index */
31	.zmii_mux	= 1,		/* ZMII input of this EMAC */
32	.mal_idx	= 0,		/* MAL device index */
33	.mal_rx_chan	= 1,		/* MAL rx channel number */
34	.mal_tx_chan	= 2,		/* MAL tx channel number */
35	.wol_irq	= 41,		/* WOL interrupt number */
36	.mdio_idx	= -1,		/* No shared MDIO */
37	.tah_idx	= -1,		/* No TAH */
38};
39static struct ocp_func_emac_data ibmnp405h_emac2_def = {
40	.rgmii_idx	= -1,		/* No RGMII */
41	.rgmii_mux	= -1,		/* No RGMII */
42	.zmii_idx	= 0,		/* ZMII device index */
43	.zmii_mux	= 2,		/* ZMII input of this EMAC */
44	.mal_idx	= 0,		/* MAL device index */
45	.mal_rx_chan	= 2,		/* MAL rx channel number */
46	.mal_tx_chan	= 4,		/* MAL tx channel number */
47	.wol_irq	= 41,		/* WOL interrupt number */
48	.mdio_idx	= -1,		/* No shared MDIO */
49	.tah_idx	= -1,		/* No TAH */
50};
51static struct ocp_func_emac_data ibmnp405h_emac3_def = {
52	.rgmii_idx	= -1,		/* No RGMII */
53	.rgmii_mux	= -1,		/* No RGMII */
54	.zmii_idx	= 0,		/* ZMII device index */
55	.zmii_mux	= 3,		/* ZMII input of this EMAC */
56	.mal_idx	= 0,		/* MAL device index */
57	.mal_rx_chan	= 3,		/* MAL rx channel number */
58	.mal_tx_chan	= 6,		/* MAL tx channel number */
59	.wol_irq	= 41,		/* WOL interrupt number */
60	.mdio_idx	= -1,		/* No shared MDIO */
61	.tah_idx	= -1,		/* No TAH */
62};
63OCP_SYSFS_EMAC_DATA()
64
65static struct ocp_func_mal_data ibmnp405h_mal0_def = {
66	.num_tx_chans	= 8,		/* Number of TX channels */
67	.num_rx_chans	= 4,		/* Number of RX channels */
68	.txeob_irq	= 17,		/* TX End Of Buffer IRQ  */
69	.rxeob_irq	= 18,		/* RX End Of Buffer IRQ  */
70	.txde_irq	= 46,		/* TX Descriptor Error IRQ */
71	.rxde_irq	= 47,		/* RX Descriptor Error IRQ */
72	.serr_irq	= 45,		/* MAL System Error IRQ    */
73	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
74};
75OCP_SYSFS_MAL_DATA()
76
77static struct ocp_func_iic_data ibmnp405h_iic0_def = {
78	.fast_mode	= 0,		/* Use standad mode (100Khz) */
79};
80OCP_SYSFS_IIC_DATA()
81
82struct ocp_def core_ocp[] = {
83	{ .vendor	= OCP_VENDOR_IBM,
84	  .function	= OCP_FUNC_OPB,
85	  .index	= 0,
86	  .paddr	= 0xEF600000,
87	  .irq		= OCP_IRQ_NA,
88	  .pm		= OCP_CPM_NA,
89	},
90	{ .vendor	= OCP_VENDOR_IBM,
91	  .function	= OCP_FUNC_16550,
92	  .index	= 0,
93	  .paddr	= UART0_IO_BASE,
94	  .irq		= UART0_INT,
95	  .pm		= IBM_CPM_UART0
96	},
97	{ .vendor	= OCP_VENDOR_IBM,
98	  .function	= OCP_FUNC_16550,
99	  .index	= 1,
100	  .paddr	= UART1_IO_BASE,
101	  .irq		= UART1_INT,
102	  .pm		= IBM_CPM_UART1
103	},
104	{ .vendor	= OCP_VENDOR_IBM,
105	  .function	= OCP_FUNC_IIC,
106	  .paddr	= 0xEF600500,
107	  .irq		= 2,
108	  .pm		= IBM_CPM_IIC0,
109	  .additions	= &ibmnp405h_iic0_def,
110	  .show		= &ocp_show_iic_data
111	},
112	{ .vendor	= OCP_VENDOR_IBM,
113	  .function	= OCP_FUNC_GPIO,
114	  .paddr	= 0xEF600700,
115	  .irq		= OCP_IRQ_NA,
116	  .pm		= IBM_CPM_GPIO0
117	},
118	{ .vendor	= OCP_VENDOR_IBM,
119	  .function	= OCP_FUNC_MAL,
120	  .paddr	= OCP_PADDR_NA,
121	  .irq		= OCP_IRQ_NA,
122	  .pm		= OCP_CPM_NA,
123	  .additions	= &ibmnp405h_mal0_def,
124	  .show		= &ocp_show_mal_data,
125	},
126	{ .vendor	= OCP_VENDOR_IBM,
127	  .function	= OCP_FUNC_EMAC,
128	  .index	= 0,
129	  .paddr	= EMAC0_BASE,
130	  .irq		= 37,
131	  .pm		= IBM_CPM_EMAC0,
132	  .additions	= &ibmnp405h_emac0_def,
133	  .show		= &ocp_show_emac_data,
134	},
135	{ .vendor	= OCP_VENDOR_IBM,
136	  .function	= OCP_FUNC_EMAC,
137	  .index	= 1,
138	  .paddr	= 0xEF600900,
139	  .irq		= 38,
140	  .pm		= IBM_CPM_EMAC1,
141	  .additions	= &ibmnp405h_emac1_def,
142	  .show		= &ocp_show_emac_data,
143	},
144	{ .vendor	= OCP_VENDOR_IBM,
145	  .function	= OCP_FUNC_EMAC,
146	  .index	= 2,
147	  .paddr	= 0xEF600a00,
148	  .irq		= 39,
149	  .pm		= IBM_CPM_EMAC2,
150	  .additions	= &ibmnp405h_emac2_def,
151	  .show		= &ocp_show_emac_data,
152	},
153	{ .vendor	= OCP_VENDOR_IBM,
154	  .function	= OCP_FUNC_EMAC,
155	  .index	= 3,
156	  .paddr	= 0xEF600b00,
157	  .irq		= 40,
158	  .pm		= IBM_CPM_EMAC3,
159	  .additions	= &ibmnp405h_emac3_def,
160	  .show		= &ocp_show_emac_data,
161	},
162	{ .vendor	= OCP_VENDOR_IBM,
163	  .function	= OCP_FUNC_ZMII,
164	  .paddr	= 0xEF600C10,
165	  .irq		= OCP_IRQ_NA,
166	  .pm		= OCP_CPM_NA,
167	},
168	{ .vendor	= OCP_VENDOR_INVALID
169	}
170};
171