/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
H A D | amdgpu_vega12_hwmgr.c | 524 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) 534 dpm_table->count = num_of_levels; 541 dpm_table->dpm_levels[i].value = clk; 542 dpm_table->dpm_levels[i].enabled = true; 561 struct vega12_single_dpm_table *dpm_table; local 564 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); 567 dpm_table = &(data->dpm_table.soc_table); 569 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCL 523 vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) argument 1721 struct vega12_single_dpm_table *dpm_table; local 1754 struct vega12_single_dpm_table *dpm_table; local 1781 struct vega12_single_dpm_table *dpm_table; local 1809 struct vega12_single_dpm_table *dpm_table; local 2179 struct vega12_single_dpm_table *dpm_table; local 2336 vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, struct vega12_single_dpm_table *dpm_table) argument [all...] |
H A D | amdgpu_vega20_hwmgr.c | 570 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) 580 dpm_table->count = num_of_levels; 587 dpm_table->dpm_levels[i].value = clk; 588 dpm_table->dpm_levels[i].enabled = true; 598 struct vega20_single_dpm_table *dpm_table; local 601 dpm_table = &(data->dpm_table.gfx_table); 603 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); 608 dpm_table->count = 1; 609 dpm_table 569 vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) argument 619 struct vega20_single_dpm_table *dpm_table; local 648 struct vega20_single_dpm_table *dpm_table; local 2304 struct vega20_single_dpm_table *dpm_table = local 2768 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); local 2796 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table); local 2821 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table); local 2843 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table); local 3487 vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, struct vega20_single_dpm_table *dpm_table) argument 3515 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table); local 3642 struct vega20_single_dpm_table *dpm_table; local [all...] |
H A D | amdgpu_vega10_hwmgr.c | 1235 struct vega10_single_dpm_table *dpm_table, 1240 dpm_table->count = 0; 1243 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= 1245 dpm_table->dpm_levels[dpm_table->count].value = 1247 dpm_table->dpm_levels[dpm_table->count].enabled = true; 1248 dpm_table->count++; 1255 struct vega10_pcie_table *pcie_table = &(data->dpm_table 1234 vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *dpm_table, struct phm_ppt_v1_clock_voltage_dependency_table *dep_table) argument 1306 struct vega10_single_dpm_table *dpm_table; local 1677 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); local 1825 struct vega10_single_dpm_table *dpm_table = local 1963 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table); local 3372 struct vega10_dpm_table *dpm_table = &data->dpm_table; local 3412 vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit) argument 3428 vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr, struct vega10_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit, uint32_t disable_dpm_mask) argument 3826 struct vega10_dpm_table *dpm_table = &data->dpm_table; local 3968 struct vega10_single_dpm_table *dpm_table = local 5164 struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table; local 5235 struct vega10_single_dpm_table *dpm_table; local [all...] |
H A D | amdgpu_smu7_hwmgr.c | 563 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, 574 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, 580 data->dpm_table.pcie_speed_table.count = max_entry - 1; 584 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, 589 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, 594 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, 599 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, 604 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, 609 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, 615 data->dpm_table 3659 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 3766 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 3809 smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr, struct smu7_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit) argument [all...] |
H A D | amdgpu_smu_helper.c | 355 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; local 357 dpm_table->count = count > max ? max : count; 359 for (i = 0; i < dpm_table->count; i++) 360 dpm_table->dpm_level[i].enabled = false; 370 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; local 371 dpm_table->dpm_level[index].value = pcie_gen; 372 dpm_table->dpm_level[index].param1 = pcie_lanes; 373 dpm_table->dpm_level[index].enabled = 1; 380 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; local 382 for (i = dpm_table 452 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; local [all...] |
H A D | smu7_hwmgr.h | 206 struct smu7_dpm_table dpm_table; member in struct:smu7_hwmgr
|
H A D | vega10_hwmgr.h | 313 struct vega10_dpm_table dpm_table; member in struct:vega10_hwmgr
|
H A D | vega12_hwmgr.h | 316 struct vega12_dpm_table dpm_table; member in struct:vega12_hwmgr
|
H A D | vega20_hwmgr.h | 439 struct vega20_dpm_table dpm_table; member in struct:vega20_hwmgr
|
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
H A D | amdgpu_vega20_ppt.c | 726 struct vega20_dpm_table *dpm_table = NULL; local 729 dpm_table = smu_dpm->dpm_context; 732 single_dpm_table = &(dpm_table->soc_table); 748 single_dpm_table = &(dpm_table->gfx_table); 764 single_dpm_table = &(dpm_table->mem_table); 780 single_dpm_table = &(dpm_table->eclk_table); 795 single_dpm_table = &(dpm_table->vclk_table); 810 single_dpm_table = &(dpm_table->dclk_table); 825 single_dpm_table = &(dpm_table->dcef_table); 841 single_dpm_table = &(dpm_table 909 struct vega20_dpm_table *dpm_table = NULL; local 932 vega20_get_clk_table(struct smu_context *smu, struct pp_clock_levels_with_latency *clocks, struct vega20_single_dpm_table *dpm_table) argument 961 struct vega20_dpm_table *dpm_table = NULL; local 1196 struct vega20_dpm_table *dpm_table; local 1284 struct vega20_dpm_table *dpm_table; local 1451 struct vega20_dpm_table *dpm_table = NULL; local 1740 struct vega20_dpm_table *dpm_table = NULL; local 1979 struct vega20_dpm_table *dpm_table = (struct vega20_dpm_table *)smu->smu_dpm.dpm_context; local 2017 vega20_set_uclk_to_highest_dpm_level(struct smu_context *smu, struct vega20_single_dpm_table *dpm_table) argument 2052 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context; local 2094 struct vega20_single_dpm_table *dpm_table; local 2240 struct vega20_dpm_table *dpm_table = smu->smu_dpm.dpm_context; local 2331 struct vega20_dpm_table *dpm_table = local 2382 struct vega20_dpm_table *dpm_table = local 2531 struct vega20_dpm_table *dpm_table = NULL; local 2604 struct vega20_dpm_table *dpm_table = NULL; local [all...] |
H A D | amdgpu_arcturus_ppt.c | 426 struct arcturus_dpm_table *dpm_table = NULL; local 429 dpm_table = smu_dpm->dpm_context; 432 single_dpm_table = &(dpm_table->soc_table); 447 single_dpm_table = &(dpm_table->gfx_table); 462 single_dpm_table = &(dpm_table->mem_table); 477 single_dpm_table = &(dpm_table->fclk_table); 491 memcpy(smu_dpm->golden_dpm_context, dpm_table, 572 struct arcturus_dpm_table *dpm_table = NULL; local 576 dpm_table = smu_dpm->dpm_context; 577 gfx_table = &(dpm_table 596 arcturus_get_clk_table(struct smu_context *smu, struct pp_clock_levels_with_latency *clocks, struct arcturus_single_dpm_table *dpm_table) argument 745 struct arcturus_dpm_table *dpm_table = local 801 struct arcturus_dpm_table *dpm_table; local 1163 struct arcturus_dpm_table *dpm_table = local 1205 struct arcturus_dpm_table *dpm_table = local 1248 struct arcturus_dpm_table *dpm_table = local [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
H A D | amdgpu_fiji_smumgr.c | 497 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); local 509 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( 511 dpm_table->TargetTdp = PP_HOST_TO_SMC_US( 518 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); 519 dpm_table->GpuTjHyst = 8; 521 dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase; 524 dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( 526 dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( 528 dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US( 530 dpm_table 837 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 1011 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 1230 struct smu7_dpm_table *dpm_table = &data->dpm_table; local [all...] |
H A D | amdgpu_iceland_smumgr.c | 772 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 776 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ 777 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { 779 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 781 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 793 (uint8_t)dpm_table->pcie_speed_table.count; 795 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 968 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 1355 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 1859 SMU71_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); local [all...] |
H A D | amdgpu_vegam_smumgr.c | 578 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 581 /* Index (dpm_table->pcie_speed_table.count) 583 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { 585 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 587 dpm_table->pcie_speed_table.dpm_levels[i].param1); 595 (uint8_t)dpm_table->pcie_speed_table.count; 599 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 870 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; local 1040 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; local [all...] |
H A D | amdgpu_ci_smumgr.c | 479 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 489 for (i = 0; i < dpm_table->sclk_table.count; i++) { 491 dpm_table->sclk_table.dpm_levels[i].value, 497 if (i == (dpm_table->sclk_table.count - 1)) 504 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; 506 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); 723 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); local 729 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256)); 730 dpm_table 1003 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 1307 struct smu7_dpm_table *dpm_table = &data->dpm_table; local [all...] |
H A D | amdgpu_tonga_smumgr.c | 515 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 519 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ 520 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { 522 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 524 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 536 (uint8_t)dpm_table->pcie_speed_table.count; 538 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 696 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 1096 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 1836 SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); local [all...] |
H A D | amdgpu_polaris10_smumgr.c | 776 struct smu7_dpm_table *dpm_table = &data->dpm_table; local 779 /* Index (dpm_table->pcie_speed_table.count) 781 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { 783 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 785 dpm_table->pcie_speed_table.dpm_levels[i].param1); 793 (uint8_t)dpm_table->pcie_speed_table.count; 797 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 986 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; local 1133 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; local [all...] |
/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_ci_dpm.c | 439 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; local 447 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; 448 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; 450 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; 451 dpm_table->GpuTjMax = 453 dpm_table->GpuTjHyst = 8; 455 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; 458 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); 459 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); 461 dpm_table 2616 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table) argument 2636 struct ci_dpm_table *dpm_table = &pi->dpm_table; local 3285 struct ci_dpm_table *dpm_table = &pi->dpm_table; local 3332 struct ci_dpm_table *dpm_table = &pi->dpm_table; local 3380 ci_reset_single_dpm_table(struct radeon_device *rdev, struct ci_single_dpm_table* dpm_table, u32 count) argument 3391 ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table, u32 index, u32 pcie_gen, u32 pcie_lanes) argument 3709 ci_trim_single_dpm_states(struct radeon_device *rdev, struct ci_single_dpm_table *dpm_table, u32 low_limit, u32 high_limit) argument 3910 struct ci_dpm_table *dpm_table = &pi->dpm_table; local 5684 SMU7_Discrete_DpmTable *dpm_table; local [all...] |
H A D | ci_dpm.h | 197 struct ci_dpm_table dpm_table; member in struct:ci_power_info
|