Lines Matching refs:dpm_table

578 	struct smu7_dpm_table *dpm_table = &data->dpm_table;
581 /* Index (dpm_table->pcie_speed_table.count)
583 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
585 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
587 dpm_table->pcie_speed_table.dpm_levels[i].param1);
595 (uint8_t)dpm_table->pcie_speed_table.count;
599 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
870 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
874 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
890 for (i = 0; i < dpm_table->sclk_table.count; i++) {
893 dpm_table->sclk_table.dpm_levels[i].value,
911 (uint8_t)dpm_table->sclk_table.count;
913 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
915 for (i = 0; i < dpm_table->sclk_table.count; i++)
924 for (i = 0; i < dpm_table->sclk_table.count; i++)
949 for (i = 2; i < dpm_table->sclk_table.count; i++)
1040 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1051 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1052 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1056 dpm_table->mclk_table.dpm_levels[i].value,
1069 (uint8_t)dpm_table->mclk_table.count;
1071 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1073 for (i = 0; i < dpm_table->mclk_table.count; i++)
1077 levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
1289 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1290 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1292 hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1293 hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1376 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1382 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
2036 PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,
2040 hw_data->dpm_table.pcie_speed_table.count;
2105 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {