1/* $NetBSD: vega20_hwmgr.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3/* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26#ifndef _VEGA20_HWMGR_H_ 27#define _VEGA20_HWMGR_H_ 28 29#include "hwmgr.h" 30#include "smu11_driver_if.h" 31#include "ppatomfwctrl.h" 32 33#define VEGA20_MAX_HARDWARE_POWERLEVELS 2 34 35#define WaterMarksExist 1 36#define WaterMarksLoaded 2 37 38#define VG20_PSUEDO_NUM_GFXCLK_DPM_LEVELS 8 39#define VG20_PSUEDO_NUM_SOCCLK_DPM_LEVELS 8 40#define VG20_PSUEDO_NUM_DCEFCLK_DPM_LEVELS 8 41#define VG20_PSUEDO_NUM_UCLK_DPM_LEVELS 4 42 43//OverDriver8 macro defs 44#define AVFS_CURVE 0 45#define OD8_HOTCURVE_TEMPERATURE 85 46 47#define VG20_CLOCK_MAX_DEFAULT 0xFFFF 48 49typedef uint32_t PP_Clock; 50 51enum { 52 GNLD_DPM_PREFETCHER = 0, 53 GNLD_DPM_GFXCLK, 54 GNLD_DPM_UCLK, 55 GNLD_DPM_SOCCLK, 56 GNLD_DPM_UVD, 57 GNLD_DPM_VCE, 58 GNLD_ULV, 59 GNLD_DPM_MP0CLK, 60 GNLD_DPM_LINK, 61 GNLD_DPM_DCEFCLK, 62 GNLD_DS_GFXCLK, 63 GNLD_DS_SOCCLK, 64 GNLD_DS_LCLK, 65 GNLD_PPT, 66 GNLD_TDC, 67 GNLD_THERMAL, 68 GNLD_GFX_PER_CU_CG, 69 GNLD_RM, 70 GNLD_DS_DCEFCLK, 71 GNLD_ACDC, 72 GNLD_VR0HOT, 73 GNLD_VR1HOT, 74 GNLD_FW_CTF, 75 GNLD_LED_DISPLAY, 76 GNLD_FAN_CONTROL, 77 GNLD_DIDT, 78 GNLD_GFXOFF, 79 GNLD_CG, 80 GNLD_DPM_FCLK, 81 GNLD_DS_FCLK, 82 GNLD_DS_MP1CLK, 83 GNLD_DS_MP0CLK, 84 GNLD_XGMI, 85 GNLD_ECC, 86 87 GNLD_FEATURES_MAX 88}; 89 90 91#define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1) 92 93#define SMC_DPM_FEATURES 0x30F 94 95struct smu_features { 96 bool supported; 97 bool enabled; 98 bool allowed; 99 uint32_t smu_feature_id; 100 uint64_t smu_feature_bitmap; 101}; 102 103struct vega20_performance_level { 104 uint32_t soc_clock; 105 uint32_t gfx_clock; 106 uint32_t mem_clock; 107}; 108 109struct vega20_bacos { 110 uint32_t baco_flags; 111 /* struct vega20_performance_level performance_level; */ 112}; 113 114struct vega20_uvd_clocks { 115 uint32_t vclk; 116 uint32_t dclk; 117}; 118 119struct vega20_vce_clocks { 120 uint32_t evclk; 121 uint32_t ecclk; 122}; 123 124struct vega20_power_state { 125 uint32_t magic; 126 struct vega20_uvd_clocks uvd_clks; 127 struct vega20_vce_clocks vce_clks; 128 uint16_t performance_level_count; 129 bool dc_compatible; 130 uint32_t sclk_threshold; 131 struct vega20_performance_level performance_levels[VEGA20_MAX_HARDWARE_POWERLEVELS]; 132}; 133 134struct vega20_dpm_level { 135 bool enabled; 136 uint32_t value; 137 uint32_t param1; 138}; 139 140#define VEGA20_MAX_DEEPSLEEP_DIVIDER_ID 5 141#define MAX_REGULAR_DPM_NUMBER 16 142#define MAX_PCIE_CONF 2 143#define VEGA20_MINIMUM_ENGINE_CLOCK 2500 144 145struct vega20_max_sustainable_clocks { 146 PP_Clock display_clock; 147 PP_Clock phy_clock; 148 PP_Clock pixel_clock; 149 PP_Clock uclock; 150 PP_Clock dcef_clock; 151 PP_Clock soc_clock; 152}; 153 154struct vega20_dpm_state { 155 uint32_t soft_min_level; 156 uint32_t soft_max_level; 157 uint32_t hard_min_level; 158 uint32_t hard_max_level; 159}; 160 161struct vega20_single_dpm_table { 162 uint32_t count; 163 struct vega20_dpm_state dpm_state; 164 struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 165}; 166 167struct vega20_odn_dpm_control { 168 uint32_t count; 169 uint32_t entries[MAX_REGULAR_DPM_NUMBER]; 170}; 171 172struct vega20_pcie_table { 173 uint16_t count; 174 uint8_t pcie_gen[MAX_PCIE_CONF]; 175 uint8_t pcie_lane[MAX_PCIE_CONF]; 176 uint32_t lclk[MAX_PCIE_CONF]; 177}; 178 179struct vega20_dpm_table { 180 struct vega20_single_dpm_table soc_table; 181 struct vega20_single_dpm_table gfx_table; 182 struct vega20_single_dpm_table mem_table; 183 struct vega20_single_dpm_table eclk_table; 184 struct vega20_single_dpm_table vclk_table; 185 struct vega20_single_dpm_table dclk_table; 186 struct vega20_single_dpm_table dcef_table; 187 struct vega20_single_dpm_table pixel_table; 188 struct vega20_single_dpm_table display_table; 189 struct vega20_single_dpm_table phy_table; 190 struct vega20_single_dpm_table fclk_table; 191 struct vega20_pcie_table pcie_table; 192}; 193 194#define VEGA20_MAX_LEAKAGE_COUNT 8 195struct vega20_leakage_voltage { 196 uint16_t count; 197 uint16_t leakage_id[VEGA20_MAX_LEAKAGE_COUNT]; 198 uint16_t actual_voltage[VEGA20_MAX_LEAKAGE_COUNT]; 199}; 200 201struct vega20_display_timing { 202 uint32_t min_clock_in_sr; 203 uint32_t num_existing_displays; 204}; 205 206struct vega20_dpmlevel_enable_mask { 207 uint32_t uvd_dpm_enable_mask; 208 uint32_t vce_dpm_enable_mask; 209 uint32_t samu_dpm_enable_mask; 210 uint32_t sclk_dpm_enable_mask; 211 uint32_t mclk_dpm_enable_mask; 212}; 213 214struct vega20_vbios_boot_state { 215 uint8_t uc_cooling_id; 216 uint16_t vddc; 217 uint16_t vddci; 218 uint16_t mvddc; 219 uint16_t vdd_gfx; 220 uint32_t gfx_clock; 221 uint32_t mem_clock; 222 uint32_t soc_clock; 223 uint32_t dcef_clock; 224 uint32_t eclock; 225 uint32_t dclock; 226 uint32_t vclock; 227 uint32_t fclock; 228}; 229 230#define DPMTABLE_OD_UPDATE_SCLK 0x00000001 231#define DPMTABLE_OD_UPDATE_MCLK 0x00000002 232#define DPMTABLE_UPDATE_SCLK 0x00000004 233#define DPMTABLE_UPDATE_MCLK 0x00000008 234#define DPMTABLE_OD_UPDATE_VDDC 0x00000010 235#define DPMTABLE_OD_UPDATE_SCLK_MASK 0x00000020 236#define DPMTABLE_OD_UPDATE_MCLK_MASK 0x00000040 237 238// To determine if sclk and mclk are in overdrive state 239#define SCLK_MASK_OVERDRIVE_ENABLED 0x00000008 240#define MCLK_MASK_OVERDRIVE_ENABLED 0x00000010 241#define SOCCLK_OVERDRIVE_ENABLED 0x00000020 242 243struct vega20_smc_state_table { 244 uint32_t soc_boot_level; 245 uint32_t gfx_boot_level; 246 uint32_t dcef_boot_level; 247 uint32_t mem_boot_level; 248 uint32_t uvd_boot_level; 249 uint32_t vce_boot_level; 250 uint32_t gfx_max_level; 251 uint32_t mem_max_level; 252 uint8_t vr_hot_gpio; 253 uint8_t ac_dc_gpio; 254 uint8_t therm_out_gpio; 255 uint8_t therm_out_polarity; 256 uint8_t therm_out_mode; 257 PPTable_t pp_table; 258 Watermarks_t water_marks_table; 259 AvfsDebugTable_t avfs_debug_table; 260 AvfsFuseOverride_t avfs_fuse_override_table; 261 SmuMetrics_t smu_metrics; 262 DriverSmuConfig_t driver_smu_config; 263 DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint; 264 OverDriveTable_t overdrive_table; 265}; 266 267struct vega20_mclk_latency_entries { 268 uint32_t frequency; 269 uint32_t latency; 270}; 271 272struct vega20_mclk_latency_table { 273 uint32_t count; 274 struct vega20_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 275}; 276 277struct vega20_registry_data { 278 uint64_t disallowed_features; 279 uint8_t ac_dc_switch_gpio_support; 280 uint8_t acg_loop_support; 281 uint8_t clock_stretcher_support; 282 uint8_t db_ramping_support; 283 uint8_t didt_mode; 284 uint8_t didt_support; 285 uint8_t edc_didt_support; 286 uint8_t force_dpm_high; 287 uint8_t fuzzy_fan_control_support; 288 uint8_t mclk_dpm_key_disabled; 289 uint8_t od_state_in_dc_support; 290 uint8_t pcie_lane_override; 291 uint8_t pcie_speed_override; 292 uint32_t pcie_clock_override; 293 uint8_t pcie_dpm_key_disabled; 294 uint8_t dcefclk_dpm_key_disabled; 295 uint8_t prefetcher_dpm_key_disabled; 296 uint8_t quick_transition_support; 297 uint8_t regulator_hot_gpio_support; 298 uint8_t master_deep_sleep_support; 299 uint8_t gfx_clk_deep_sleep_support; 300 uint8_t sclk_deep_sleep_support; 301 uint8_t lclk_deep_sleep_support; 302 uint8_t dce_fclk_deep_sleep_support; 303 uint8_t sclk_dpm_key_disabled; 304 uint8_t sclk_throttle_low_notification; 305 uint8_t skip_baco_hardware; 306 uint8_t socclk_dpm_key_disabled; 307 uint8_t sq_ramping_support; 308 uint8_t tcp_ramping_support; 309 uint8_t td_ramping_support; 310 uint8_t dbr_ramping_support; 311 uint8_t gc_didt_support; 312 uint8_t psm_didt_support; 313 uint8_t thermal_support; 314 uint8_t fw_ctf_enabled; 315 uint8_t led_dpm_enabled; 316 uint8_t fan_control_support; 317 uint8_t ulv_support; 318 uint8_t od8_feature_enable; 319 uint8_t disable_water_mark; 320 uint8_t disable_workload_policy; 321 uint32_t force_workload_policy_mask; 322 uint8_t disable_3d_fs_detection; 323 uint8_t disable_pp_tuning; 324 uint8_t disable_xlpp_tuning; 325 uint32_t perf_ui_tuning_profile_turbo; 326 uint32_t perf_ui_tuning_profile_powerSave; 327 uint32_t perf_ui_tuning_profile_xl; 328 uint16_t zrpm_stop_temp; 329 uint16_t zrpm_start_temp; 330 uint32_t stable_pstate_sclk_dpm_percentage; 331 uint8_t fps_support; 332 uint8_t vr0hot; 333 uint8_t vr1hot; 334 uint8_t disable_auto_wattman; 335 uint32_t auto_wattman_debug; 336 uint32_t auto_wattman_sample_period; 337 uint32_t fclk_gfxclk_ratio; 338 uint8_t auto_wattman_threshold; 339 uint8_t log_avfs_param; 340 uint8_t enable_enginess; 341 uint8_t custom_fan_support; 342 uint8_t disable_pcc_limit_control; 343 uint8_t gfxoff_controlled_by_driver; 344}; 345 346struct vega20_odn_clock_voltage_dependency_table { 347 uint32_t count; 348 struct phm_ppt_v1_clock_voltage_dependency_record 349 entries[MAX_REGULAR_DPM_NUMBER]; 350}; 351 352struct vega20_odn_dpm_table { 353 struct vega20_odn_dpm_control control_gfxclk_state; 354 struct vega20_odn_dpm_control control_memclk_state; 355 struct phm_odn_clock_levels odn_core_clock_dpm_levels; 356 struct phm_odn_clock_levels odn_memory_clock_dpm_levels; 357 struct vega20_odn_clock_voltage_dependency_table vdd_dependency_on_sclk; 358 struct vega20_odn_clock_voltage_dependency_table vdd_dependency_on_mclk; 359 struct vega20_odn_clock_voltage_dependency_table vdd_dependency_on_socclk; 360 uint32_t odn_mclk_min_limit; 361}; 362 363struct vega20_odn_fan_table { 364 uint32_t target_fan_speed; 365 uint32_t target_temperature; 366 uint32_t min_performance_clock; 367 uint32_t min_fan_limit; 368 bool force_fan_pwm; 369}; 370 371struct vega20_odn_temp_table { 372 uint16_t target_operating_temp; 373 uint16_t default_target_operating_temp; 374 uint16_t operating_temp_min_limit; 375 uint16_t operating_temp_max_limit; 376 uint16_t operating_temp_step; 377}; 378 379struct vega20_odn_data { 380 uint32_t apply_overdrive_next_settings_mask; 381 uint32_t overdrive_next_state; 382 uint32_t overdrive_next_capabilities; 383 uint32_t odn_sclk_dpm_enable_mask; 384 uint32_t odn_mclk_dpm_enable_mask; 385 struct vega20_odn_dpm_table odn_dpm_table; 386 struct vega20_odn_fan_table odn_fan_table; 387 struct vega20_odn_temp_table odn_temp_table; 388}; 389 390enum OD8_FEATURE_ID 391{ 392 OD8_GFXCLK_LIMITS = 1 << 0, 393 OD8_GFXCLK_CURVE = 1 << 1, 394 OD8_UCLK_MAX = 1 << 2, 395 OD8_POWER_LIMIT = 1 << 3, 396 OD8_ACOUSTIC_LIMIT_SCLK = 1 << 4, //FanMaximumRpm 397 OD8_FAN_SPEED_MIN = 1 << 5, //FanMinimumPwm 398 OD8_TEMPERATURE_FAN = 1 << 6, //FanTargetTemperature 399 OD8_TEMPERATURE_SYSTEM = 1 << 7, //MaxOpTemp 400 OD8_MEMORY_TIMING_TUNE = 1 << 8, 401 OD8_FAN_ZERO_RPM_CONTROL = 1 << 9 402}; 403 404enum OD8_SETTING_ID 405{ 406 OD8_SETTING_GFXCLK_FMIN = 0, 407 OD8_SETTING_GFXCLK_FMAX, 408 OD8_SETTING_GFXCLK_FREQ1, 409 OD8_SETTING_GFXCLK_VOLTAGE1, 410 OD8_SETTING_GFXCLK_FREQ2, 411 OD8_SETTING_GFXCLK_VOLTAGE2, 412 OD8_SETTING_GFXCLK_FREQ3, 413 OD8_SETTING_GFXCLK_VOLTAGE3, 414 OD8_SETTING_UCLK_FMAX, 415 OD8_SETTING_POWER_PERCENTAGE, 416 OD8_SETTING_FAN_ACOUSTIC_LIMIT, 417 OD8_SETTING_FAN_MIN_SPEED, 418 OD8_SETTING_FAN_TARGET_TEMP, 419 OD8_SETTING_OPERATING_TEMP_MAX, 420 OD8_SETTING_AC_TIMING, 421 OD8_SETTING_FAN_ZERO_RPM_CONTROL, 422 OD8_SETTING_COUNT 423}; 424 425struct vega20_od8_single_setting { 426 uint32_t feature_id; 427 int32_t min_value; 428 int32_t max_value; 429 int32_t current_value; 430 int32_t default_value; 431}; 432 433struct vega20_od8_settings { 434 uint32_t overdrive8_capabilities; 435 struct vega20_od8_single_setting od8_settings_array[OD8_SETTING_COUNT]; 436}; 437 438struct vega20_hwmgr { 439 struct vega20_dpm_table dpm_table; 440 struct vega20_dpm_table golden_dpm_table; 441 struct vega20_registry_data registry_data; 442 struct vega20_vbios_boot_state vbios_boot_state; 443 struct vega20_mclk_latency_table mclk_latency_table; 444 445 struct vega20_max_sustainable_clocks max_sustainable_clocks; 446 447 struct vega20_leakage_voltage vddc_leakage; 448 449 uint32_t vddc_control; 450 struct pp_atomfwctrl_voltage_table vddc_voltage_table; 451 uint32_t mvdd_control; 452 struct pp_atomfwctrl_voltage_table mvdd_voltage_table; 453 uint32_t vddci_control; 454 struct pp_atomfwctrl_voltage_table vddci_voltage_table; 455 456 uint32_t active_auto_throttle_sources; 457 struct vega20_bacos bacos; 458 459 /* ---- General data ---- */ 460 uint8_t need_update_dpm_table; 461 462 bool cac_enabled; 463 bool battery_state; 464 bool is_tlu_enabled; 465 bool avfs_exist; 466 467 uint32_t low_sclk_interrupt_threshold; 468 469 uint32_t total_active_cus; 470 471 uint32_t water_marks_bitmap; 472 473 struct vega20_display_timing display_timing; 474 475 /* ---- Vega20 Dyn Register Settings ---- */ 476 477 uint32_t debug_settings; 478 uint32_t lowest_uclk_reserved_for_ulv; 479 uint32_t gfxclk_average_alpha; 480 uint32_t socclk_average_alpha; 481 uint32_t uclk_average_alpha; 482 uint32_t gfx_activity_average_alpha; 483 uint32_t display_voltage_mode; 484 uint32_t dcef_clk_quad_eqn_a; 485 uint32_t dcef_clk_quad_eqn_b; 486 uint32_t dcef_clk_quad_eqn_c; 487 uint32_t disp_clk_quad_eqn_a; 488 uint32_t disp_clk_quad_eqn_b; 489 uint32_t disp_clk_quad_eqn_c; 490 uint32_t pixel_clk_quad_eqn_a; 491 uint32_t pixel_clk_quad_eqn_b; 492 uint32_t pixel_clk_quad_eqn_c; 493 uint32_t phy_clk_quad_eqn_a; 494 uint32_t phy_clk_quad_eqn_b; 495 uint32_t phy_clk_quad_eqn_c; 496 497 /* ---- Thermal Temperature Setting ---- */ 498 struct vega20_dpmlevel_enable_mask dpm_level_enable_mask; 499 500 /* ---- Power Gating States ---- */ 501 bool uvd_power_gated; 502 bool vce_power_gated; 503 bool samu_power_gated; 504 bool need_long_memory_training; 505 506 /* Internal settings to apply the application power optimization parameters */ 507 bool apply_optimized_settings; 508 uint32_t disable_dpm_mask; 509 510 /* ---- Overdrive next setting ---- */ 511 struct vega20_odn_data odn_data; 512 bool gfxclk_overdrive; 513 bool memclk_overdrive; 514 515 /* ---- Overdrive8 Setting ---- */ 516 struct vega20_od8_settings od8_settings; 517 518 /* ---- Workload Mask ---- */ 519 uint32_t workload_mask; 520 521 /* ---- SMU9 ---- */ 522 uint32_t smu_version; 523 struct smu_features smu_features[GNLD_FEATURES_MAX]; 524 struct vega20_smc_state_table smc_state_table; 525 526 /* ---- Gfxoff ---- */ 527 bool gfxoff_allowed; 528 uint32_t counter_gfxoff; 529 530 unsigned long metrics_time; 531 SmuMetrics_t metrics_table; 532 533 bool pcie_parameters_override; 534 uint32_t pcie_gen_level1; 535 uint32_t pcie_width_level1; 536 537 bool is_custom_profile_set; 538}; 539 540#define VEGA20_DPM2_NEAR_TDP_DEC 10 541#define VEGA20_DPM2_ABOVE_SAFE_INC 5 542#define VEGA20_DPM2_BELOW_SAFE_INC 20 543 544#define VEGA20_DPM2_LTA_WINDOW_SIZE 7 545 546#define VEGA20_DPM2_LTS_TRUNCATE 0 547 548#define VEGA20_DPM2_TDP_SAFE_LIMIT_PERCENT 80 549 550#define VEGA20_DPM2_MAXPS_PERCENT_M 90 551#define VEGA20_DPM2_MAXPS_PERCENT_H 90 552 553#define VEGA20_DPM2_PWREFFICIENCYRATIO_MARGIN 50 554 555#define VEGA20_DPM2_SQ_RAMP_MAX_POWER 0x3FFF 556#define VEGA20_DPM2_SQ_RAMP_MIN_POWER 0x12 557#define VEGA20_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 558#define VEGA20_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E 559#define VEGA20_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF 560 561#define VEGA20_VOLTAGE_CONTROL_NONE 0x0 562#define VEGA20_VOLTAGE_CONTROL_BY_GPIO 0x1 563#define VEGA20_VOLTAGE_CONTROL_BY_SVID2 0x2 564#define VEGA20_VOLTAGE_CONTROL_MERGED 0x3 565/* To convert to Q8.8 format for firmware */ 566#define VEGA20_Q88_FORMAT_CONVERSION_UNIT 256 567 568#define VEGA20_UNUSED_GPIO_PIN 0x7F 569 570#define VEGA20_THERM_OUT_MODE_DISABLE 0x0 571#define VEGA20_THERM_OUT_MODE_THERM_ONLY 0x1 572#define VEGA20_THERM_OUT_MODE_THERM_VRHOT 0x2 573 574#define PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT 0xffffffff 575#define PPREGKEY_VEGA20QUADRATICEQUATION_DFLT 0xffffffff 576 577#define PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 578#define PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 579#define PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 580#define PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 581#define PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT 0xffffffff 582#define PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT 0xffffffff 583#define PPREGKEY_VEGA20QUADRATICEQUATION_DFLT 0xffffffff 584 585#define VEGA20_UMD_PSTATE_GFXCLK_LEVEL 0x3 586#define VEGA20_UMD_PSTATE_SOCCLK_LEVEL 0x3 587#define VEGA20_UMD_PSTATE_MCLK_LEVEL 0x2 588#define VEGA20_UMD_PSTATE_UVDCLK_LEVEL 0x3 589#define VEGA20_UMD_PSTATE_VCEMCLK_LEVEL 0x3 590 591#endif /* _VEGA20_HWMGR_H_ */ 592