powerplay/smumgr/amdgpu_ci_smumgr.c

479 	struct smu7_dpm_table *dpm_table = &data->dpm_table;
489 	for (i = 0; i < dpm_table->sclk_table.count; i++) {
491 				dpm_table->sclk_table.dpm_levels[i].value,
497 		if (i == (dpm_table->sclk_table.count - 1))
504 	smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
506 		phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
723 	SMU7_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
729 	dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256));
730 	dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
732 	dpm_table->DTETjOffset = 0;
733 	dpm_table->GpuTjMax = (uint8_t)(data->thermal_temp_setting.temperature_high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES);
734 	dpm_table->GpuTjHyst = 8;
736 	dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
739 		dpm_table->PPM_PkgPwrLimit = (uint16_t)ppm->dgpu_tdp * 256 / 1000;
740 		dpm_table->PPM_TemperatureLimit = (uint16_t)ppm->tj_max * 256;
742 		dpm_table->PPM_PkgPwrLimit = 0;
743 		dpm_table->PPM_TemperatureLimit = 0;
746 	CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
747 	CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);
749 	dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
756 				dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*def1);
757 				dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*def2);
1003 	struct smu7_dpm_table *dpm_table = &data->dpm_table;
1007 /* Index dpm_table->pcie_speed_table.count is reserved for PCIE boot level.*/
1008 	for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1010 			(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1012 			(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
1019 		(uint8_t)dpm_table->pcie_speed_table.count;
1021 		phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1307 	struct smu7_dpm_table *dpm_table = &data->dpm_table;
1319 	for (i = 0; i < dpm_table->mclk_table.count; i++) {
1320 		PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1322 		result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
1332 	if ((dpm_table->mclk_table.count >= 2)
1342 	smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count;
1343 	data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1344 	smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1663 	for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1664 		for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1666 				(hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
1667 				 data->dpm_table.mclk_table.dpm_levels[j].value,
1699 	result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1709 	result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1799 	for (i = 0; i < data->dpm_table.mclk_table.count; i++) {
1802 				data->dpm_table.mclk_table.dpm_levels[i].value,
1835 				sizeof(SMU7_Discrete_MCRegisterSet) * data->dpm_table.mclk_table.count,
2057 	PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count),
2061 	table->PCIeBootLinkLevel = (uint8_t)data->dpm_table.pcie_speed_table.count;