| /netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | rv740d.h | 68 #define MCLK_PWRMGT_CNTL 0x648 macro
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| H A D | rv6xxd.h | 49 #define MCLK_PWRMGT_CNTL 0x624 macro
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| H A D | radeon_rv740_dpm.c | 313 RREG32(MCLK_PWRMGT_CNTL);
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| H A D | radeon_rv770_dpm.c | 188 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
206 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
1544 RREG32(MCLK_PWRMGT_CNTL);
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| H A D | radeon_r600_dpm.c | 319 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
321 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
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| H A D | rv770d.h | 173 #define MCLK_PWRMGT_CNTL 0x648 macro
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| H A D | radeon_rv6xx_dpm.c | 996 WREG32_P(MCLK_PWRMGT_CNTL, USE_DISPLAY_GAP, ~USE_DISPLAY_GAP);
998 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~USE_DISPLAY_GAP);
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| H A D | radeon_cypress_dpm.c | 263 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
265 WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
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| H A D | nid.h | 615 #define MCLK_PWRMGT_CNTL 0x648 macro
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| H A D | cikd.h | 723 #define MCLK_PWRMGT_CNTL 0x2ba0 macro
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| H A D | sid.h | 598 #define MCLK_PWRMGT_CNTL 0x2ba0 macro
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| H A D | evergreend.h | 153 #define MCLK_PWRMGT_CNTL 0x648 macro
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| H A D | r600d.h | 1327 #define MCLK_PWRMGT_CNTL 0x624 macro
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| H A D | radeon_ni_dpm.c | 1199 ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
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| H A D | radeon_ci_dpm.c | 1893 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
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| H A D | radeon_si_dpm.c | 3583 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| H A D | amdgpu_iceland_smumgr.c | 1150 /* MCLK_PWRMGT_CNTL setup */
1152 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1154 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1156 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1517 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
1519 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
1523 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
1525 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
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| H A D | amdgpu_ci_smumgr.c | 1101 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
1103 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
1105 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1469 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
1471 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
1475 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
1477 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
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| H A D | amdgpu_tonga_smumgr.c | 902 /* MCLK_PWRMGT_CNTL setup */
904 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
906 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
908 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
1259 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
1261 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
1265 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
1267 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | sid.h | 600 #define MCLK_PWRMGT_CNTL 0xAE8 macro
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| H A D | amdgpu_si_dpm.c | 4044 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
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