1/* $NetBSD: evergreend.h,v 1.5 2021/12/18 23:45:42 riastradh Exp $ */ 2 3/* 4 * Copyright 2010 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26#ifndef EVERGREEND_H 27#define EVERGREEND_H 28 29#define EVERGREEN_MAX_SH_GPRS 256 30#define EVERGREEN_MAX_TEMP_GPRS 16 31#define EVERGREEN_MAX_SH_THREADS 256 32#define EVERGREEN_MAX_SH_STACK_ENTRIES 4096 33#define EVERGREEN_MAX_FRC_EOV_CNT 16384 34#define EVERGREEN_MAX_BACKENDS 8 35#define EVERGREEN_MAX_BACKENDS_MASK 0xFF 36#define EVERGREEN_MAX_SIMDS 16 37#define EVERGREEN_MAX_SIMDS_MASK 0xFFFF 38#define EVERGREEN_MAX_PIPES 8 39#define EVERGREEN_MAX_PIPES_MASK 0xFF 40#define EVERGREEN_MAX_LDS_NUM 0xFFFF 41 42#define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003 43#define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003 44#define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 45#define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002 46#define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002 47#define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 48#define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 49#define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 50#define SUMO_GB_ADDR_CONFIG_GOLDEN 0x02010002 51#define SUMO2_GB_ADDR_CONFIG_GOLDEN 0x02010002 52 53/* pm registers */ 54#define SMC_MSG 0x20c 55#define HOST_SMC_MSG(x) ((x) << 0) 56#define HOST_SMC_MSG_MASK (0xff << 0) 57#define HOST_SMC_MSG_SHIFT 0 58#define HOST_SMC_RESP(x) ((x) << 8) 59#define HOST_SMC_RESP_MASK (0xff << 8) 60#define HOST_SMC_RESP_SHIFT 8 61#define SMC_HOST_MSG(x) ((x) << 16) 62#define SMC_HOST_MSG_MASK (0xff << 16) 63#define SMC_HOST_MSG_SHIFT 16 64#define SMC_HOST_RESP(x) ((x) << 24) 65#define SMC_HOST_RESP_MASK (0xff << 24) 66#define SMC_HOST_RESP_SHIFT 24 67 68#define DCCG_DISP_SLOW_SELECT_REG 0x4fc 69#define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) 70#define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) 71#define DCCG_DISP1_SLOW_SELECT_SHIFT 0 72#define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) 73#define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) 74#define DCCG_DISP2_SLOW_SELECT_SHIFT 4 75 76#define CG_SPLL_FUNC_CNTL 0x600 77#define SPLL_RESET (1 << 0) 78#define SPLL_SLEEP (1 << 1) 79#define SPLL_BYPASS_EN (1 << 3) 80#define SPLL_REF_DIV(x) ((x) << 4) 81#define SPLL_REF_DIV_MASK (0x3f << 4) 82#define SPLL_PDIV_A(x) ((x) << 20) 83#define SPLL_PDIV_A_MASK (0x7f << 20) 84#define CG_SPLL_FUNC_CNTL_2 0x604 85#define SCLK_MUX_SEL(x) ((x) << 0) 86#define SCLK_MUX_SEL_MASK (0x1ff << 0) 87#define SCLK_MUX_UPDATE (1 << 26) 88#define CG_SPLL_FUNC_CNTL_3 0x608 89#define SPLL_FB_DIV(x) ((x) << 0) 90#define SPLL_FB_DIV_MASK (0x3ffffff << 0) 91#define SPLL_DITHEN (1 << 28) 92#define CG_SPLL_STATUS 0x60c 93#define SPLL_CHG_STATUS (1 << 1) 94 95#define MPLL_CNTL_MODE 0x61c 96# define MPLL_MCLK_SEL (1 << 11) 97# define SS_SSEN (1 << 24) 98# define SS_DSMODE_EN (1 << 25) 99 100#define MPLL_AD_FUNC_CNTL 0x624 101#define CLKF(x) ((x) << 0) 102#define CLKF_MASK (0x7f << 0) 103#define CLKR(x) ((x) << 7) 104#define CLKR_MASK (0x1f << 7) 105#define CLKFRAC(x) ((x) << 12) 106#define CLKFRAC_MASK (0x1f << 12) 107#define YCLK_POST_DIV(x) ((x) << 17) 108#define YCLK_POST_DIV_MASK (3 << 17) 109#define IBIAS(x) ((x) << 20) 110#define IBIAS_MASK (0x3ff << 20) 111#define RESET (1 << 30) 112#define PDNB (1U << 31) 113#define MPLL_AD_FUNC_CNTL_2 0x628 114#define BYPASS (1 << 19) 115#define BIAS_GEN_PDNB (1 << 24) 116#define RESET_EN (1 << 25) 117#define VCO_MODE (1 << 29) 118#define MPLL_DQ_FUNC_CNTL 0x62c 119#define MPLL_DQ_FUNC_CNTL_2 0x630 120 121#define GENERAL_PWRMGT 0x63c 122# define GLOBAL_PWRMGT_EN (1 << 0) 123# define STATIC_PM_EN (1 << 1) 124# define THERMAL_PROTECTION_DIS (1 << 2) 125# define THERMAL_PROTECTION_TYPE (1 << 3) 126# define ENABLE_GEN2PCIE (1 << 4) 127# define ENABLE_GEN2XSP (1 << 5) 128# define SW_SMIO_INDEX(x) ((x) << 6) 129# define SW_SMIO_INDEX_MASK (3 << 6) 130# define SW_SMIO_INDEX_SHIFT 6 131# define LOW_VOLT_D2_ACPI (1 << 8) 132# define LOW_VOLT_D3_ACPI (1 << 9) 133# define VOLT_PWRMGT_EN (1 << 10) 134# define BACKBIAS_PAD_EN (1 << 18) 135# define BACKBIAS_VALUE (1 << 19) 136# define DYN_SPREAD_SPECTRUM_EN (1 << 23) 137# define AC_DC_SW (1 << 24) 138 139#define SCLK_PWRMGT_CNTL 0x644 140# define SCLK_PWRMGT_OFF (1 << 0) 141# define SCLK_LOW_D1 (1 << 1) 142# define FIR_RESET (1 << 4) 143# define FIR_FORCE_TREND_SEL (1 << 5) 144# define FIR_TREND_MODE (1 << 6) 145# define DYN_GFX_CLK_OFF_EN (1 << 7) 146# define GFX_CLK_FORCE_ON (1 << 8) 147# define GFX_CLK_REQUEST_OFF (1 << 9) 148# define GFX_CLK_FORCE_OFF (1 << 10) 149# define GFX_CLK_OFF_ACPI_D1 (1 << 11) 150# define GFX_CLK_OFF_ACPI_D2 (1 << 12) 151# define GFX_CLK_OFF_ACPI_D3 (1 << 13) 152# define DYN_LIGHT_SLEEP_EN (1 << 14) 153#define MCLK_PWRMGT_CNTL 0x648 154# define DLL_SPEED(x) ((x) << 0) 155# define DLL_SPEED_MASK (0x1f << 0) 156# define MPLL_PWRMGT_OFF (1 << 5) 157# define DLL_READY (1 << 6) 158# define MC_INT_CNTL (1 << 7) 159# define MRDCKA0_PDNB (1 << 8) 160# define MRDCKA1_PDNB (1 << 9) 161# define MRDCKB0_PDNB (1 << 10) 162# define MRDCKB1_PDNB (1 << 11) 163# define MRDCKC0_PDNB (1 << 12) 164# define MRDCKC1_PDNB (1 << 13) 165# define MRDCKD0_PDNB (1 << 14) 166# define MRDCKD1_PDNB (1 << 15) 167# define MRDCKA0_RESET (1 << 16) 168# define MRDCKA1_RESET (1 << 17) 169# define MRDCKB0_RESET (1 << 18) 170# define MRDCKB1_RESET (1 << 19) 171# define MRDCKC0_RESET (1 << 20) 172# define MRDCKC1_RESET (1 << 21) 173# define MRDCKD0_RESET (1 << 22) 174# define MRDCKD1_RESET (1 << 23) 175# define DLL_READY_READ (1 << 24) 176# define USE_DISPLAY_GAP (1 << 25) 177# define USE_DISPLAY_URGENT_NORMAL (1 << 26) 178# define MPLL_TURNOFF_D2 (1 << 28) 179#define DLL_CNTL 0x64c 180# define MRDCKA0_BYPASS (1 << 24) 181# define MRDCKA1_BYPASS (1 << 25) 182# define MRDCKB0_BYPASS (1 << 26) 183# define MRDCKB1_BYPASS (1 << 27) 184# define MRDCKC0_BYPASS (1 << 28) 185# define MRDCKC1_BYPASS (1 << 29) 186# define MRDCKD0_BYPASS (1 << 30) 187# define MRDCKD1_BYPASS (1U << 31) 188 189#define CG_AT 0x6d4 190# define CG_R(x) ((x) << 0) 191# define CG_R_MASK (0xffff << 0) 192# define CG_L(x) ((x) << 16) 193# define CG_L_MASK (0xffff << 16) 194 195#define CG_DISPLAY_GAP_CNTL 0x714 196# define DISP1_GAP(x) ((x) << 0) 197# define DISP1_GAP_MASK (3 << 0) 198# define DISP2_GAP(x) ((x) << 2) 199# define DISP2_GAP_MASK (3 << 2) 200# define VBI_TIMER_COUNT(x) ((x) << 4) 201# define VBI_TIMER_COUNT_MASK (0x3fff << 4) 202# define VBI_TIMER_UNIT(x) ((x) << 20) 203# define VBI_TIMER_UNIT_MASK (7 << 20) 204# define DISP1_GAP_MCHG(x) ((x) << 24) 205# define DISP1_GAP_MCHG_MASK (3 << 24) 206# define DISP2_GAP_MCHG(x) ((x) << 26) 207# define DISP2_GAP_MCHG_MASK (3 << 26) 208 209#define CG_BIF_REQ_AND_RSP 0x7f4 210#define CG_CLIENT_REQ(x) ((x) << 0) 211#define CG_CLIENT_REQ_MASK (0xff << 0) 212#define CG_CLIENT_REQ_SHIFT 0 213#define CG_CLIENT_RESP(x) ((x) << 8) 214#define CG_CLIENT_RESP_MASK (0xff << 8) 215#define CG_CLIENT_RESP_SHIFT 8 216#define CLIENT_CG_REQ(x) ((x) << 16) 217#define CLIENT_CG_REQ_MASK (0xff << 16) 218#define CLIENT_CG_REQ_SHIFT 16 219#define CLIENT_CG_RESP(x) ((x) << 24) 220#define CLIENT_CG_RESP_MASK (0xff << 24) 221#define CLIENT_CG_RESP_SHIFT 24 222 223#define CG_SPLL_SPREAD_SPECTRUM 0x790 224#define SSEN (1 << 0) 225#define CG_SPLL_SPREAD_SPECTRUM_2 0x794 226 227#define MPLL_SS1 0x85c 228#define CLKV(x) ((x) << 0) 229#define CLKV_MASK (0x3ffffff << 0) 230#define MPLL_SS2 0x860 231#define CLKS(x) ((x) << 0) 232#define CLKS_MASK (0xfff << 0) 233 234#define CG_IND_ADDR 0x8f8 235#define CG_IND_DATA 0x8fc 236/* CGIND regs */ 237#define CG_CGTT_LOCAL_0 0x00 238#define CG_CGTT_LOCAL_1 0x01 239#define CG_CGTT_LOCAL_2 0x02 240#define CG_CGTT_LOCAL_3 0x03 241#define CG_CGLS_TILE_0 0x20 242#define CG_CGLS_TILE_1 0x21 243#define CG_CGLS_TILE_2 0x22 244#define CG_CGLS_TILE_3 0x23 245#define CG_CGLS_TILE_4 0x24 246#define CG_CGLS_TILE_5 0x25 247#define CG_CGLS_TILE_6 0x26 248#define CG_CGLS_TILE_7 0x27 249#define CG_CGLS_TILE_8 0x28 250#define CG_CGLS_TILE_9 0x29 251#define CG_CGLS_TILE_10 0x2a 252#define CG_CGLS_TILE_11 0x2b 253 254#define VM_L2_CG 0x15c0 255 256#define MC_CONFIG 0x2000 257 258#define MC_CONFIG_MCD 0x20a0 259#define MC_CG_CONFIG_MCD 0x20a4 260#define MC_RD_ENABLE_MCD(x) ((x) << 8) 261#define MC_RD_ENABLE_MCD_MASK (7 << 8) 262 263#define MC_HUB_MISC_HUB_CG 0x20b8 264#define MC_HUB_MISC_VM_CG 0x20bc 265#define MC_HUB_MISC_SIP_CG 0x20c0 266 267#define MC_XPB_CLK_GAT 0x2478 268 269#define MC_CG_CONFIG 0x25bc 270#define MC_RD_ENABLE(x) ((x) << 4) 271#define MC_RD_ENABLE_MASK (3 << 4) 272 273#define MC_CITF_MISC_RD_CG 0x2648 274#define MC_CITF_MISC_WR_CG 0x264c 275#define MC_CITF_MISC_VM_CG 0x2650 276# define MEM_LS_ENABLE (1 << 19) 277 278#define MC_ARB_BURST_TIME 0x2808 279#define STATE0(x) ((x) << 0) 280#define STATE0_MASK (0x1f << 0) 281#define STATE1(x) ((x) << 5) 282#define STATE1_MASK (0x1f << 5) 283#define STATE2(x) ((x) << 10) 284#define STATE2_MASK (0x1f << 10) 285#define STATE3(x) ((x) << 15) 286#define STATE3_MASK (0x1f << 15) 287 288#define MC_SEQ_RAS_TIMING 0x28a0 289#define MC_SEQ_CAS_TIMING 0x28a4 290#define MC_SEQ_MISC_TIMING 0x28a8 291#define MC_SEQ_MISC_TIMING2 0x28ac 292 293#define MC_SEQ_RD_CTL_D0 0x28b4 294#define MC_SEQ_RD_CTL_D1 0x28b8 295#define MC_SEQ_WR_CTL_D0 0x28bc 296#define MC_SEQ_WR_CTL_D1 0x28c0 297 298#define MC_SEQ_STATUS_M 0x29f4 299# define PMG_PWRSTATE (1 << 16) 300 301#define MC_SEQ_MISC1 0x2a04 302#define MC_SEQ_RESERVE_M 0x2a08 303#define MC_PMG_CMD_EMRS 0x2a0c 304 305#define MC_SEQ_MISC3 0x2a2c 306 307#define MC_SEQ_MISC5 0x2a54 308#define MC_SEQ_MISC6 0x2a58 309 310#define MC_SEQ_MISC7 0x2a64 311 312#define MC_SEQ_CG 0x2a68 313#define CG_SEQ_REQ(x) ((x) << 0) 314#define CG_SEQ_REQ_MASK (0xff << 0) 315#define CG_SEQ_REQ_SHIFT 0 316#define CG_SEQ_RESP(x) ((x) << 8) 317#define CG_SEQ_RESP_MASK (0xff << 8) 318#define CG_SEQ_RESP_SHIFT 8 319#define SEQ_CG_REQ(x) ((x) << 16) 320#define SEQ_CG_REQ_MASK (0xff << 16) 321#define SEQ_CG_REQ_SHIFT 16 322#define SEQ_CG_RESP(x) ((x) << 24) 323#define SEQ_CG_RESP_MASK (0xff << 24) 324#define SEQ_CG_RESP_SHIFT 24 325#define MC_SEQ_RAS_TIMING_LP 0x2a6c 326#define MC_SEQ_CAS_TIMING_LP 0x2a70 327#define MC_SEQ_MISC_TIMING_LP 0x2a74 328#define MC_SEQ_MISC_TIMING2_LP 0x2a78 329#define MC_SEQ_WR_CTL_D0_LP 0x2a7c 330#define MC_SEQ_WR_CTL_D1_LP 0x2a80 331#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 332#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 333 334#define MC_PMG_CMD_MRS 0x2aac 335 336#define MC_SEQ_RD_CTL_D0_LP 0x2b1c 337#define MC_SEQ_RD_CTL_D1_LP 0x2b20 338 339#define MC_PMG_CMD_MRS1 0x2b44 340#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 341 342#define CGTS_SM_CTRL_REG 0x9150 343 344/* Registers */ 345 346#define RCU_IND_INDEX 0x100 347#define RCU_IND_DATA 0x104 348 349/* discrete uvd clocks */ 350#define CG_UPLL_FUNC_CNTL 0x718 351# define UPLL_RESET_MASK 0x00000001 352# define UPLL_SLEEP_MASK 0x00000002 353# define UPLL_BYPASS_EN_MASK 0x00000004 354# define UPLL_CTLREQ_MASK 0x00000008 355# define UPLL_REF_DIV_MASK 0x003F0000 356# define UPLL_VCO_MODE_MASK 0x00000200 357# define UPLL_CTLACK_MASK 0x40000000 358# define UPLL_CTLACK2_MASK 0x80000000 359#define CG_UPLL_FUNC_CNTL_2 0x71c 360# define UPLL_PDIV_A(x) ((x) << 0) 361# define UPLL_PDIV_A_MASK 0x0000007F 362# define UPLL_PDIV_B(x) ((x) << 8) 363# define UPLL_PDIV_B_MASK 0x00007F00 364# define VCLK_SRC_SEL(x) ((x) << 20) 365# define VCLK_SRC_SEL_MASK 0x01F00000 366# define DCLK_SRC_SEL(x) ((x) << 25) 367# define DCLK_SRC_SEL_MASK 0x3E000000 368#define CG_UPLL_FUNC_CNTL_3 0x720 369# define UPLL_FB_DIV(x) ((x) << 0) 370# define UPLL_FB_DIV_MASK 0x01FFFFFF 371#define CG_UPLL_FUNC_CNTL_4 0x854 372# define UPLL_SPARE_ISPARE9 0x00020000 373#define CG_UPLL_SPREAD_SPECTRUM 0x79c 374# define SSEN_MASK 0x00000001 375 376/* fusion uvd clocks */ 377#define CG_DCLK_CNTL 0x610 378# define DCLK_DIVIDER_MASK 0x7f 379# define DCLK_DIR_CNTL_EN (1 << 8) 380#define CG_DCLK_STATUS 0x614 381# define DCLK_STATUS (1 << 0) 382#define CG_VCLK_CNTL 0x618 383#define CG_VCLK_STATUS 0x61c 384#define CG_SCRATCH1 0x820 385 386#define RLC_CNTL 0x3f00 387# define RLC_ENABLE (1 << 0) 388# define GFX_POWER_GATING_ENABLE (1 << 7) 389# define GFX_POWER_GATING_SRC (1 << 8) 390# define DYN_PER_SIMD_PG_ENABLE (1 << 27) 391# define LB_CNT_SPIM_ACTIVE (1 << 30) 392# define LOAD_BALANCE_ENABLE (1 << 31) 393 394#define RLC_HB_BASE 0x3f10 395#define RLC_HB_CNTL 0x3f0c 396#define RLC_HB_RPTR 0x3f20 397#define RLC_HB_WPTR 0x3f1c 398#define RLC_HB_WPTR_LSB_ADDR 0x3f14 399#define RLC_HB_WPTR_MSB_ADDR 0x3f18 400#define RLC_MC_CNTL 0x3f44 401#define RLC_UCODE_CNTL 0x3f48 402#define RLC_UCODE_ADDR 0x3f2c 403#define RLC_UCODE_DATA 0x3f30 404 405/* new for TN */ 406#define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 407#define TN_RLC_LB_CNTR_MAX 0x3f14 408#define TN_RLC_LB_CNTR_INIT 0x3f18 409#define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 410#define TN_RLC_LB_INIT_SIMD_MASK 0x3fe4 411#define TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK 0x3fe8 412#define TN_RLC_LB_PARAMS 0x3fec 413 414#define GRBM_GFX_INDEX 0x802C 415#define INSTANCE_INDEX(x) ((x) << 0) 416#define SE_INDEX(x) ((x) << 16) 417#define INSTANCE_BROADCAST_WRITES (1 << 30) 418#define SE_BROADCAST_WRITES (1U << 31) 419#define RLC_GFX_INDEX 0x3fC4 420#define CC_GC_SHADER_PIPE_CONFIG 0x8950 421#define WRITE_DIS (1 << 0) 422#define CC_RB_BACKEND_DISABLE 0x98F4 423#define BACKEND_DISABLE(x) ((x) << 16) 424#define GB_ADDR_CONFIG 0x98F8 425#define NUM_PIPES(x) ((x) << 0) 426#define NUM_PIPES_MASK 0x0000000f 427#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 428#define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 429#define NUM_SHADER_ENGINES(x) ((x) << 12) 430#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 431#define NUM_GPUS(x) ((x) << 20) 432#define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 433#define ROW_SIZE(x) ((x) << 28) 434#define GB_BACKEND_MAP 0x98FC 435#define DMIF_ADDR_CONFIG 0xBD4 436#define HDP_ADDR_CONFIG 0x2F48 437#define HDP_MISC_CNTL 0x2F4C 438#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 439 440#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 441#define GC_USER_RB_BACKEND_DISABLE 0x9B7C 442 443#define CGTS_SYS_TCC_DISABLE 0x3F90 444#define CGTS_TCC_DISABLE 0x9148 445#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 446#define CGTS_USER_TCC_DISABLE 0x914C 447 448#define CONFIG_MEMSIZE 0x5428 449 450#define BIF_FB_EN 0x5490 451#define FB_READ_EN (1 << 0) 452#define FB_WRITE_EN (1 << 1) 453 454#define CP_STRMOUT_CNTL 0x84FC 455 456#define CP_COHER_CNTL 0x85F0 457#define CP_COHER_SIZE 0x85F4 458#define CP_COHER_BASE 0x85F8 459#define CP_STALLED_STAT1 0x8674 460#define CP_STALLED_STAT2 0x8678 461#define CP_BUSY_STAT 0x867C 462#define CP_STAT 0x8680 463#define CP_ME_CNTL 0x86D8 464#define CP_ME_HALT (1 << 28) 465#define CP_PFP_HALT (1 << 26) 466#define CP_ME_RAM_DATA 0xC160 467#define CP_ME_RAM_RADDR 0xC158 468#define CP_ME_RAM_WADDR 0xC15C 469#define CP_MEQ_THRESHOLDS 0x8764 470#define STQ_SPLIT(x) ((x) << 0) 471#define CP_PERFMON_CNTL 0x87FC 472#define CP_PFP_UCODE_ADDR 0xC150 473#define CP_PFP_UCODE_DATA 0xC154 474#define CP_QUEUE_THRESHOLDS 0x8760 475#define ROQ_IB1_START(x) ((x) << 0) 476#define ROQ_IB2_START(x) ((x) << 8) 477#define CP_RB_BASE 0xC100 478#define CP_RB_CNTL 0xC104 479#define RB_BUFSZ(x) ((x) << 0) 480#define RB_BLKSZ(x) ((x) << 8) 481#define RB_NO_UPDATE (1 << 27) 482#define RB_RPTR_WR_ENA (1U << 31) 483#define BUF_SWAP_32BIT (2 << 16) 484#define CP_RB_RPTR 0x8700 485#define CP_RB_RPTR_ADDR 0xC10C 486#define RB_RPTR_SWAP(x) ((x) << 0) 487#define CP_RB_RPTR_ADDR_HI 0xC110 488#define CP_RB_RPTR_WR 0xC108 489#define CP_RB_WPTR 0xC114 490#define CP_RB_WPTR_ADDR 0xC118 491#define CP_RB_WPTR_ADDR_HI 0xC11C 492#define CP_RB_WPTR_DELAY 0x8704 493#define CP_SEM_WAIT_TIMER 0x85BC 494#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 495#define CP_DEBUG 0xC1FC 496 497/* Audio clocks */ 498#define DCCG_AUDIO_DTO_SOURCE 0x05ac 499# define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ 500# define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ 501 502#define DCCG_AUDIO_DTO0_PHASE 0x05b0 503#define DCCG_AUDIO_DTO0_MODULE 0x05b4 504#define DCCG_AUDIO_DTO0_LOAD 0x05b8 505#define DCCG_AUDIO_DTO0_CNTL 0x05bc 506# define DCCG_AUDIO_DTO_WALLCLOCK_RATIO(x) (((x) & 7) << 0) 507# define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK 7 508# define DCCG_AUDIO_DTO_WALLCLOCK_RATIO_SHIFT 0 509 510#define DCCG_AUDIO_DTO1_PHASE 0x05c0 511#define DCCG_AUDIO_DTO1_MODULE 0x05c4 512#define DCCG_AUDIO_DTO1_LOAD 0x05c8 513#define DCCG_AUDIO_DTO1_CNTL 0x05cc 514# define DCCG_AUDIO_DTO1_USE_512FBR_DTO (1 << 3) 515 516#define DCE41_DENTIST_DISPCLK_CNTL 0x049c 517# define DENTIST_DPREFCLK_WDIVIDER(x) (((x) & 0x7f) << 24) 518# define DENTIST_DPREFCLK_WDIVIDER_MASK (0x7f << 24) 519# define DENTIST_DPREFCLK_WDIVIDER_SHIFT 24 520 521/* DCE 4.0 AFMT */ 522#define HDMI_CONTROL 0x7030 523# define HDMI_KEEPOUT_MODE (1 << 0) 524# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 525# define HDMI_ERROR_ACK (1 << 8) 526# define HDMI_ERROR_MASK (1 << 9) 527# define HDMI_DEEP_COLOR_ENABLE (1 << 24) 528# define HDMI_DEEP_COLOR_DEPTH(x) (((x) & 3) << 28) 529# define HDMI_24BIT_DEEP_COLOR 0 530# define HDMI_30BIT_DEEP_COLOR 1 531# define HDMI_36BIT_DEEP_COLOR 2 532# define HDMI_DEEP_COLOR_DEPTH_MASK (3 << 28) 533#define HDMI_STATUS 0x7034 534# define HDMI_ACTIVE_AVMUTE (1 << 0) 535# define HDMI_AUDIO_PACKET_ERROR (1 << 16) 536# define HDMI_VBI_PACKET_ERROR (1 << 20) 537#define HDMI_AUDIO_PACKET_CONTROL 0x7038 538# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 539# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 540#define HDMI_ACR_PACKET_CONTROL 0x703c 541# define HDMI_ACR_SEND (1 << 0) 542# define HDMI_ACR_CONT (1 << 1) 543# define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 544# define HDMI_ACR_HW 0 545# define HDMI_ACR_32 1 546# define HDMI_ACR_44 2 547# define HDMI_ACR_48 3 548# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 549# define HDMI_ACR_AUTO_SEND (1 << 12) 550# define HDMI_ACR_N_MULTIPLE(x) (((x) & 7) << 16) 551# define HDMI_ACR_X1 1 552# define HDMI_ACR_X2 2 553# define HDMI_ACR_X4 4 554# define HDMI_ACR_AUDIO_PRIORITY (1 << 31) 555#define HDMI_VBI_PACKET_CONTROL 0x7040 556# define HDMI_NULL_SEND (1 << 0) 557# define HDMI_GC_SEND (1 << 4) 558# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 559#define HDMI_INFOFRAME_CONTROL0 0x7044 560# define HDMI_AVI_INFO_SEND (1 << 0) 561# define HDMI_AVI_INFO_CONT (1 << 1) 562# define HDMI_AUDIO_INFO_SEND (1 << 4) 563# define HDMI_AUDIO_INFO_CONT (1 << 5) 564# define HDMI_MPEG_INFO_SEND (1 << 8) 565# define HDMI_MPEG_INFO_CONT (1 << 9) 566#define HDMI_INFOFRAME_CONTROL1 0x7048 567# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 568# define HDMI_AVI_INFO_LINE_MASK (0x3f << 0) 569# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 570# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 571#define HDMI_GENERIC_PACKET_CONTROL 0x704c 572# define HDMI_GENERIC0_SEND (1 << 0) 573# define HDMI_GENERIC0_CONT (1 << 1) 574# define HDMI_GENERIC1_SEND (1 << 4) 575# define HDMI_GENERIC1_CONT (1 << 5) 576# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 577# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 578#define HDMI_GC 0x7058 579# define HDMI_GC_AVMUTE (1 << 0) 580# define HDMI_GC_AVMUTE_CONT (1 << 2) 581#define AFMT_AUDIO_PACKET_CONTROL2 0x705c 582# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 583# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 584# define AFMT_60958_CS_SOURCE (1 << 4) 585# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 586# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 587#define AFMT_AVI_INFO0 0x7084 588# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 589# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 590# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 591# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 592# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 593# define AFMT_AVI_INFO_Y_RGB 0 594# define AFMT_AVI_INFO_Y_YCBCR422 1 595# define AFMT_AVI_INFO_Y_YCBCR444 2 596# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 597# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 598# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 599# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 600# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 601# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 602# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 603# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 604# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 605# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 606#define AFMT_AVI_INFO1 0x7088 607# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 608# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 609# define AFMT_AVI_INFO_CN(x) (((x) & 0x3) << 12) 610# define AFMT_AVI_INFO_YQ(x) (((x) & 0x3) << 14) 611# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 612#define AFMT_AVI_INFO2 0x708c 613# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 614# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 615#define AFMT_AVI_INFO3 0x7090 616# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 617# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 618#define AFMT_MPEG_INFO0 0x7094 619# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 620# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 621# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 622# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 623#define AFMT_MPEG_INFO1 0x7098 624# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 625# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 626# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 627#define AFMT_GENERIC0_HDR 0x709c 628#define AFMT_GENERIC0_0 0x70a0 629#define AFMT_GENERIC0_1 0x70a4 630#define AFMT_GENERIC0_2 0x70a8 631#define AFMT_GENERIC0_3 0x70ac 632#define AFMT_GENERIC0_4 0x70b0 633#define AFMT_GENERIC0_5 0x70b4 634#define AFMT_GENERIC0_6 0x70b8 635#define AFMT_GENERIC1_HDR 0x70bc 636#define AFMT_GENERIC1_0 0x70c0 637#define AFMT_GENERIC1_1 0x70c4 638#define AFMT_GENERIC1_2 0x70c8 639#define AFMT_GENERIC1_3 0x70cc 640#define AFMT_GENERIC1_4 0x70d0 641#define AFMT_GENERIC1_5 0x70d4 642#define AFMT_GENERIC1_6 0x70d8 643#define HDMI_ACR_32_0 0x70dc 644# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 645#define HDMI_ACR_32_1 0x70e0 646# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 647#define HDMI_ACR_44_0 0x70e4 648# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 649#define HDMI_ACR_44_1 0x70e8 650# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 651#define HDMI_ACR_48_0 0x70ec 652# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 653#define HDMI_ACR_48_1 0x70f0 654# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 655#define HDMI_ACR_STATUS_0 0x70f4 656#define HDMI_ACR_STATUS_1 0x70f8 657#define AFMT_AUDIO_INFO0 0x70fc 658# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 659# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 660# define AFMT_AUDIO_INFO_CT(x) (((x) & 0xf) << 11) 661# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 662# define AFMT_AUDIO_INFO_CXT(x) (((x) & 0x1f) << 24) 663#define AFMT_AUDIO_INFO1 0x7100 664# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 665# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 666# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 667# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 668# define AFMT_AUDIO_INFO_LFEBPL(x) (((x) & 3) << 16) 669#define AFMT_60958_0 0x7104 670# define AFMT_60958_CS_A(x) (((x) & 1) << 0) 671# define AFMT_60958_CS_B(x) (((x) & 1) << 1) 672# define AFMT_60958_CS_C(x) (((x) & 1) << 2) 673# define AFMT_60958_CS_D(x) (((x) & 3) << 3) 674# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 675# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 676# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 677# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 678# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 679# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 680#define AFMT_60958_1 0x7108 681# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 682# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 683# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 684# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 685# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 686#define AFMT_AUDIO_CRC_CONTROL 0x710c 687# define AFMT_AUDIO_CRC_EN (1 << 0) 688#define AFMT_RAMP_CONTROL0 0x7110 689# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 690# define AFMT_RAMP_DATA_SIGN (1 << 31) 691#define AFMT_RAMP_CONTROL1 0x7114 692# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 693# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 694#define AFMT_RAMP_CONTROL2 0x7118 695# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 696#define AFMT_RAMP_CONTROL3 0x711c 697# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 698#define AFMT_60958_2 0x7120 699# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 700# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 701# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 702# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 703# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 704# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 705#define AFMT_STATUS 0x7128 706# define AFMT_AUDIO_ENABLE (1 << 4) 707# define AFMT_AUDIO_HBR_ENABLE (1 << 8) 708# define AFMT_AZ_FORMAT_WTRIG (1 << 28) 709# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 710# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 711#define AFMT_AUDIO_PACKET_CONTROL 0x712c 712# define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 713# define AFMT_RESET_FIFO_WHEN_AUDIO_DIS (1 << 11) /* set to 1 */ 714# define AFMT_AUDIO_TEST_EN (1 << 12) 715# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 716# define AFMT_60958_CS_UPDATE (1 << 26) 717# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 718# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 719# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 720# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 721#define AFMT_VBI_PACKET_CONTROL 0x7130 722# define AFMT_GENERIC0_UPDATE (1 << 2) 723#define AFMT_INFOFRAME_CONTROL0 0x7134 724# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - afmt regs */ 725# define AFMT_AUDIO_INFO_UPDATE (1 << 7) 726# define AFMT_MPEG_INFO_UPDATE (1 << 10) 727#define AFMT_GENERIC0_7 0x7138 728 729/* DCE4/5 ELD audio interface */ 730#define AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER 0x5f78 731#define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) 732#define SPEAKER_ALLOCATION_MASK (0x7f << 0) 733#define SPEAKER_ALLOCATION_SHIFT 0 734#define HDMI_CONNECTION (1 << 16) 735#define DP_CONNECTION (1 << 17) 736 737#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x5f84 /* LPCM */ 738#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x5f88 /* AC3 */ 739#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x5f8c /* MPEG1 */ 740#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x5f90 /* MP3 */ 741#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x5f94 /* MPEG2 */ 742#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x5f98 /* AAC */ 743#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x5f9c /* DTS */ 744#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x5fa0 /* ATRAC */ 745#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x5fa4 /* one bit audio - leave at 0 (default) */ 746#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x5fa8 /* Dolby Digital */ 747#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x5fac /* DTS-HD */ 748#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x5fb0 /* MAT-MLP */ 749#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x5fb4 /* DTS */ 750#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x5fb8 /* WMA Pro */ 751# define MAX_CHANNELS(x) (((x) & 0x7) << 0) 752/* max channels minus one. 7 = 8 channels */ 753# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 754# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 755# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 756/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 757 * bit0 = 32 kHz 758 * bit1 = 44.1 kHz 759 * bit2 = 48 kHz 760 * bit3 = 88.2 kHz 761 * bit4 = 96 kHz 762 * bit5 = 176.4 kHz 763 * bit6 = 192 kHz 764 */ 765 766#define AZ_CHANNEL_COUNT_CONTROL 0x5fe4 767# define HBR_CHANNEL_COUNT(x) (((x) & 0x7) << 0) 768# define COMPRESSED_CHANNEL_COUNT(x) (((x) & 0x7) << 4) 769/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT 770 * 0 = use stream header 771 * 1-7 = channel count - 1 772 */ 773#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC 0x5fe8 774# define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0) 775# define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8) 776/* VIDEO_LIPSYNC, AUDIO_LIPSYNC 777 * 0 = invalid 778 * x = legal delay value 779 * 255 = sync not supported 780 */ 781#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR 0x5fec 782# define HBR_CAPABLE (1 << 0) /* enabled by default */ 783 784#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4 785# define DISPLAY0_TYPE(x) (((x) & 0x3) << 0) 786# define DISPLAY_TYPE_NONE 0 787# define DISPLAY_TYPE_HDMI 1 788# define DISPLAY_TYPE_DP 2 789# define DISPLAY0_ID(x) (((x) & 0x3f) << 2) 790# define DISPLAY1_TYPE(x) (((x) & 0x3) << 8) 791# define DISPLAY1_ID(x) (((x) & 0x3f) << 10) 792# define DISPLAY2_TYPE(x) (((x) & 0x3) << 16) 793# define DISPLAY2_ID(x) (((x) & 0x3f) << 18) 794# define DISPLAY3_TYPE(x) (((x) & 0x3) << 24) 795# define DISPLAY3_ID(x) (((x) & 0x3f) << 26) 796#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8 797# define DISPLAY4_TYPE(x) (((x) & 0x3) << 0) 798# define DISPLAY4_ID(x) (((x) & 0x3f) << 2) 799# define DISPLAY5_TYPE(x) (((x) & 0x3) << 8) 800# define DISPLAY5_ID(x) (((x) & 0x3f) << 10) 801#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER 0x5ffc 802# define NUMBER_OF_DISPLAY_ID(x) (((x) & 0x7) << 0) 803 804#define AZ_HOT_PLUG_CONTROL 0x5e78 805# define AZ_FORCE_CODEC_WAKE (1 << 0) 806# define PIN0_JACK_DETECTION_ENABLE (1 << 4) 807# define PIN1_JACK_DETECTION_ENABLE (1 << 5) 808# define PIN2_JACK_DETECTION_ENABLE (1 << 6) 809# define PIN3_JACK_DETECTION_ENABLE (1 << 7) 810# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) 811# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) 812# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) 813# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) 814# define CODEC_HOT_PLUG_ENABLE (1 << 12) 815# define PIN0_AUDIO_ENABLED (1 << 24) 816# define PIN1_AUDIO_ENABLED (1 << 25) 817# define PIN2_AUDIO_ENABLED (1 << 26) 818# define PIN3_AUDIO_ENABLED (1 << 27) 819# define AUDIO_ENABLED (1U << 31) 820 821 822#define GC_USER_SHADER_PIPE_CONFIG 0x8954 823#define INACTIVE_QD_PIPES(x) ((x) << 8) 824#define INACTIVE_QD_PIPES_MASK 0x0000FF00 825#define INACTIVE_SIMDS(x) ((x) << 16) 826#define INACTIVE_SIMDS_MASK 0x00FF0000 827 828#define GRBM_CNTL 0x8000 829#define GRBM_READ_TIMEOUT(x) ((x) << 0) 830#define GRBM_SOFT_RESET 0x8020 831#define SOFT_RESET_CP (1 << 0) 832#define SOFT_RESET_CB (1 << 1) 833#define SOFT_RESET_DB (1 << 3) 834#define SOFT_RESET_PA (1 << 5) 835#define SOFT_RESET_SC (1 << 6) 836#define SOFT_RESET_SPI (1 << 8) 837#define SOFT_RESET_SH (1 << 9) 838#define SOFT_RESET_SX (1 << 10) 839#define SOFT_RESET_TC (1 << 11) 840#define SOFT_RESET_TA (1 << 12) 841#define SOFT_RESET_VC (1 << 13) 842#define SOFT_RESET_VGT (1 << 14) 843 844#define GRBM_STATUS 0x8010 845#define CMDFIFO_AVAIL_MASK 0x0000000F 846#define SRBM_RQ_PENDING (1 << 5) 847#define CF_RQ_PENDING (1 << 7) 848#define PF_RQ_PENDING (1 << 8) 849#define GRBM_EE_BUSY (1 << 10) 850#define SX_CLEAN (1 << 11) 851#define DB_CLEAN (1 << 12) 852#define CB_CLEAN (1 << 13) 853#define TA_BUSY (1 << 14) 854#define VGT_BUSY_NO_DMA (1 << 16) 855#define VGT_BUSY (1 << 17) 856#define SX_BUSY (1 << 20) 857#define SH_BUSY (1 << 21) 858#define SPI_BUSY (1 << 22) 859#define SC_BUSY (1 << 24) 860#define PA_BUSY (1 << 25) 861#define DB_BUSY (1 << 26) 862#define CP_COHERENCY_BUSY (1 << 28) 863#define CP_BUSY (1 << 29) 864#define CB_BUSY (1 << 30) 865#define GUI_ACTIVE (1 << 31) 866#define GRBM_STATUS_SE0 0x8014 867#define GRBM_STATUS_SE1 0x8018 868#define SE_SX_CLEAN (1 << 0) 869#define SE_DB_CLEAN (1 << 1) 870#define SE_CB_CLEAN (1 << 2) 871#define SE_TA_BUSY (1 << 25) 872#define SE_SX_BUSY (1 << 26) 873#define SE_SPI_BUSY (1 << 27) 874#define SE_SH_BUSY (1 << 28) 875#define SE_SC_BUSY (1 << 29) 876#define SE_DB_BUSY (1 << 30) 877#define SE_CB_BUSY (1 << 31) 878/* evergreen */ 879#define CG_THERMAL_CTRL 0x72c 880#define TOFFSET_MASK 0x00003FE0 881#define TOFFSET_SHIFT 5 882#define DIG_THERM_DPM(x) ((x) << 14) 883#define DIG_THERM_DPM_MASK 0x003FC000 884#define DIG_THERM_DPM_SHIFT 14 885 886#define CG_THERMAL_INT 0x734 887#define DIG_THERM_INTH(x) ((x) << 8) 888#define DIG_THERM_INTH_MASK 0x0000FF00 889#define DIG_THERM_INTH_SHIFT 8 890#define DIG_THERM_INTL(x) ((x) << 16) 891#define DIG_THERM_INTL_MASK 0x00FF0000 892#define DIG_THERM_INTL_SHIFT 16 893#define THERM_INT_MASK_HIGH (1 << 24) 894#define THERM_INT_MASK_LOW (1 << 25) 895 896#define TN_CG_THERMAL_INT_CTRL 0x738 897#define TN_DIG_THERM_INTH(x) ((x) << 0) 898#define TN_DIG_THERM_INTH_MASK 0x000000FF 899#define TN_DIG_THERM_INTH_SHIFT 0 900#define TN_DIG_THERM_INTL(x) ((x) << 8) 901#define TN_DIG_THERM_INTL_MASK 0x0000FF00 902#define TN_DIG_THERM_INTL_SHIFT 8 903#define TN_THERM_INT_MASK_HIGH (1 << 24) 904#define TN_THERM_INT_MASK_LOW (1 << 25) 905 906#define CG_MULT_THERMAL_STATUS 0x740 907#define ASIC_T(x) ((x) << 16) 908#define ASIC_T_MASK 0x07FF0000 909#define ASIC_T_SHIFT 16 910#define CG_TS0_STATUS 0x760 911#define TS0_ADC_DOUT_MASK 0x000003FF 912#define TS0_ADC_DOUT_SHIFT 0 913 914/* APU */ 915#define CG_THERMAL_STATUS 0x678 916 917#define HDP_HOST_PATH_CNTL 0x2C00 918#define HDP_NONSURFACE_BASE 0x2C04 919#define HDP_NONSURFACE_INFO 0x2C08 920#define HDP_NONSURFACE_SIZE 0x2C0C 921#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 922#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 923#define HDP_TILING_CONFIG 0x2F3C 924 925#define MC_SHARED_CHMAP 0x2004 926#define NOOFCHAN_SHIFT 12 927#define NOOFCHAN_MASK 0x00003000 928#define MC_SHARED_CHREMAP 0x2008 929 930#define MC_SHARED_BLACKOUT_CNTL 0x20ac 931#define BLACKOUT_MODE_MASK 0x00000007 932 933#define MC_ARB_RAMCFG 0x2760 934#define NOOFBANK_SHIFT 0 935#define NOOFBANK_MASK 0x00000003 936#define NOOFRANK_SHIFT 2 937#define NOOFRANK_MASK 0x00000004 938#define NOOFROWS_SHIFT 3 939#define NOOFROWS_MASK 0x00000038 940#define NOOFCOLS_SHIFT 6 941#define NOOFCOLS_MASK 0x000000C0 942#define CHANSIZE_SHIFT 8 943#define CHANSIZE_MASK 0x00000100 944#define BURSTLENGTH_SHIFT 9 945#define BURSTLENGTH_MASK 0x00000200 946#define CHANSIZE_OVERRIDE (1 << 11) 947#define FUS_MC_ARB_RAMCFG 0x2768 948#define MC_VM_AGP_TOP 0x2028 949#define MC_VM_AGP_BOT 0x202C 950#define MC_VM_AGP_BASE 0x2030 951#define MC_VM_FB_LOCATION 0x2024 952#define MC_FUS_VM_FB_OFFSET 0x2898 953#define MC_VM_MB_L1_TLB0_CNTL 0x2234 954#define MC_VM_MB_L1_TLB1_CNTL 0x2238 955#define MC_VM_MB_L1_TLB2_CNTL 0x223C 956#define MC_VM_MB_L1_TLB3_CNTL 0x2240 957#define ENABLE_L1_TLB (1 << 0) 958#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 959#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 960#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 961#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 962#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 963#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 964#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 965#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 966#define MC_VM_MD_L1_TLB0_CNTL 0x2654 967#define MC_VM_MD_L1_TLB1_CNTL 0x2658 968#define MC_VM_MD_L1_TLB2_CNTL 0x265C 969#define MC_VM_MD_L1_TLB3_CNTL 0x2698 970 971#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C 972#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660 973#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664 974 975#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 976#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 977#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 978 979#define PA_CL_ENHANCE 0x8A14 980#define CLIP_VTX_REORDER_ENA (1 << 0) 981#define NUM_CLIP_SEQ(x) ((x) << 1) 982#define PA_SC_ENHANCE 0x8BF0 983#define PA_SC_AA_CONFIG 0x28C04 984#define MSAA_NUM_SAMPLES_SHIFT 0 985#define MSAA_NUM_SAMPLES_MASK 0x3 986#define PA_SC_CLIPRECT_RULE 0x2820C 987#define PA_SC_EDGERULE 0x28230 988#define PA_SC_FIFO_SIZE 0x8BCC 989#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 990#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 991#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 992#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 993#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 994#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 995#define PA_SC_LINE_STIPPLE 0x28A0C 996#define PA_SU_LINE_STIPPLE_VALUE 0x8A60 997#define PA_SC_LINE_STIPPLE_STATE 0x8B10 998 999#define SCRATCH_REG0 0x8500 1000#define SCRATCH_REG1 0x8504 1001#define SCRATCH_REG2 0x8508 1002#define SCRATCH_REG3 0x850C 1003#define SCRATCH_REG4 0x8510 1004#define SCRATCH_REG5 0x8514 1005#define SCRATCH_REG6 0x8518 1006#define SCRATCH_REG7 0x851C 1007#define SCRATCH_UMSK 0x8540 1008#define SCRATCH_ADDR 0x8544 1009 1010#define SMX_SAR_CTL0 0xA008 1011#define SMX_DC_CTL0 0xA020 1012#define USE_HASH_FUNCTION (1 << 0) 1013#define NUMBER_OF_SETS(x) ((x) << 1) 1014#define FLUSH_ALL_ON_EVENT (1 << 10) 1015#define STALL_ON_EVENT (1 << 11) 1016#define SMX_EVENT_CTL 0xA02C 1017#define ES_FLUSH_CTL(x) ((x) << 0) 1018#define GS_FLUSH_CTL(x) ((x) << 3) 1019#define ACK_FLUSH_CTL(x) ((x) << 6) 1020#define SYNC_FLUSH_CTL (1 << 8) 1021 1022#define SPI_CONFIG_CNTL 0x9100 1023#define GPR_WRITE_PRIORITY(x) ((x) << 0) 1024#define SPI_CONFIG_CNTL_1 0x913C 1025#define VTX_DONE_DELAY(x) ((x) << 0) 1026#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 1027#define SPI_INPUT_Z 0x286D8 1028#define SPI_PS_IN_CONTROL_0 0x286CC 1029#define NUM_INTERP(x) ((x)<<0) 1030#define POSITION_ENA (1<<8) 1031#define POSITION_CENTROID (1<<9) 1032#define POSITION_ADDR(x) ((x)<<10) 1033#define PARAM_GEN(x) ((x)<<15) 1034#define PARAM_GEN_ADDR(x) ((x)<<19) 1035#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 1036#define PERSP_GRADIENT_ENA (1<<28) 1037#define LINEAR_GRADIENT_ENA (1<<29) 1038#define POSITION_SAMPLE (1<<30) 1039#define BARYC_AT_SAMPLE_ENA (1<<31) 1040 1041#define SQ_CONFIG 0x8C00 1042#define VC_ENABLE (1 << 0) 1043#define EXPORT_SRC_C (1 << 1) 1044#define CS_PRIO(x) ((x) << 18) 1045#define LS_PRIO(x) ((x) << 20) 1046#define HS_PRIO(x) ((x) << 22) 1047#define PS_PRIO(x) ((x) << 24) 1048#define VS_PRIO(x) ((x) << 26) 1049#define GS_PRIO(x) ((x) << 28) 1050#define ES_PRIO(x) ((u32)(x) << 30) 1051#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 1052#define NUM_PS_GPRS(x) ((x) << 0) 1053#define NUM_VS_GPRS(x) ((x) << 16) 1054#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 1055#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 1056#define NUM_GS_GPRS(x) ((x) << 0) 1057#define NUM_ES_GPRS(x) ((x) << 16) 1058#define SQ_GPR_RESOURCE_MGMT_3 0x8C0C 1059#define NUM_HS_GPRS(x) ((x) << 0) 1060#define NUM_LS_GPRS(x) ((x) << 16) 1061#define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 1062#define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 1063#define SQ_THREAD_RESOURCE_MGMT 0x8C18 1064#define NUM_PS_THREADS(x) ((x) << 0) 1065#define NUM_VS_THREADS(x) ((x) << 8) 1066#define NUM_GS_THREADS(x) ((x) << 16) 1067#define NUM_ES_THREADS(x) ((x) << 24) 1068#define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C 1069#define NUM_HS_THREADS(x) ((x) << 0) 1070#define NUM_LS_THREADS(x) ((x) << 8) 1071#define SQ_STACK_RESOURCE_MGMT_1 0x8C20 1072#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 1073#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 1074#define SQ_STACK_RESOURCE_MGMT_2 0x8C24 1075#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 1076#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 1077#define SQ_STACK_RESOURCE_MGMT_3 0x8C28 1078#define NUM_HS_STACK_ENTRIES(x) ((x) << 0) 1079#define NUM_LS_STACK_ENTRIES(x) ((x) << 16) 1080#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 1081#define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 1082#define SQ_STATIC_THREAD_MGMT_1 0x8E20 1083#define SQ_STATIC_THREAD_MGMT_2 0x8E24 1084#define SQ_STATIC_THREAD_MGMT_3 0x8E28 1085#define SQ_LDS_RESOURCE_MGMT 0x8E2C 1086 1087#define SQ_MS_FIFO_SIZES 0x8CF0 1088#define CACHE_FIFO_SIZE(x) ((x) << 0) 1089#define FETCH_FIFO_HIWATER(x) ((x) << 8) 1090#define DONE_FIFO_HIWATER(x) ((x) << 16) 1091#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 1092 1093#define SX_DEBUG_1 0x9058 1094#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 1095#define SX_EXPORT_BUFFER_SIZES 0x900C 1096#define COLOR_BUFFER_SIZE(x) ((x) << 0) 1097#define POSITION_BUFFER_SIZE(x) ((x) << 8) 1098#define SMX_BUFFER_SIZE(x) ((x) << 16) 1099#define SX_MEMORY_EXPORT_BASE 0x9010 1100#define SX_MISC 0x28350 1101 1102#define CB_PERF_CTR0_SEL_0 0x9A20 1103#define CB_PERF_CTR0_SEL_1 0x9A24 1104#define CB_PERF_CTR1_SEL_0 0x9A28 1105#define CB_PERF_CTR1_SEL_1 0x9A2C 1106#define CB_PERF_CTR2_SEL_0 0x9A30 1107#define CB_PERF_CTR2_SEL_1 0x9A34 1108#define CB_PERF_CTR3_SEL_0 0x9A38 1109#define CB_PERF_CTR3_SEL_1 0x9A3C 1110 1111#define TA_CNTL_AUX 0x9508 1112#define DISABLE_CUBE_WRAP (1 << 0) 1113#define DISABLE_CUBE_ANISO (1 << 1) 1114#define SYNC_GRADIENT (1 << 24) 1115#define SYNC_WALKER (1 << 25) 1116#define SYNC_ALIGNER (1 << 26) 1117 1118#define TCP_CHAN_STEER_LO 0x960c 1119#define TCP_CHAN_STEER_HI 0x9610 1120 1121#define VGT_CACHE_INVALIDATION 0x88C4 1122#define CACHE_INVALIDATION(x) ((x) << 0) 1123#define VC_ONLY 0 1124#define TC_ONLY 1 1125#define VC_AND_TC 2 1126#define AUTO_INVLD_EN(x) ((x) << 6) 1127#define NO_AUTO 0 1128#define ES_AUTO 1 1129#define GS_AUTO 2 1130#define ES_AND_GS_AUTO 3 1131#define VGT_GS_VERTEX_REUSE 0x88D4 1132#define VGT_NUM_INSTANCES 0x8974 1133#define VGT_OUT_DEALLOC_CNTL 0x28C5C 1134#define DEALLOC_DIST_MASK 0x0000007F 1135#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 1136#define VTX_REUSE_DEPTH_MASK 0x000000FF 1137 1138#define VM_CONTEXT0_CNTL 0x1410 1139#define ENABLE_CONTEXT (1 << 0) 1140#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 1141#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 1142#define VM_CONTEXT1_CNTL 0x1414 1143#define VM_CONTEXT1_CNTL2 0x1434 1144#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 1145#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 1146#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 1147#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 1148#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 1149#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 1150#define RESPONSE_TYPE_MASK 0x000000F0 1151#define RESPONSE_TYPE_SHIFT 4 1152#define VM_L2_CNTL 0x1400 1153#define ENABLE_L2_CACHE (1 << 0) 1154#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 1155#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 1156#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 1157#define VM_L2_CNTL2 0x1404 1158#define INVALIDATE_ALL_L1_TLBS (1 << 0) 1159#define INVALIDATE_L2_CACHE (1 << 1) 1160#define VM_L2_CNTL3 0x1408 1161#define BANK_SELECT(x) ((x) << 0) 1162#define CACHE_UPDATE_MODE(x) ((x) << 6) 1163#define VM_L2_STATUS 0x140C 1164#define L2_BUSY (1 << 0) 1165#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 1166#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 1167 1168#define WAIT_UNTIL 0x8040 1169 1170#define SRBM_STATUS 0x0E50 1171#define RLC_RQ_PENDING (1 << 3) 1172#define GRBM_RQ_PENDING (1 << 5) 1173#define VMC_BUSY (1 << 8) 1174#define MCB_BUSY (1 << 9) 1175#define MCB_NON_DISPLAY_BUSY (1 << 10) 1176#define MCC_BUSY (1 << 11) 1177#define MCD_BUSY (1 << 12) 1178#define SEM_BUSY (1 << 14) 1179#define RLC_BUSY (1 << 15) 1180#define IH_BUSY (1 << 17) 1181#define SRBM_STATUS2 0x0EC4 1182#define DMA_BUSY (1 << 5) 1183#define SRBM_SOFT_RESET 0x0E60 1184#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 1185#define SOFT_RESET_BIF (1 << 1) 1186#define SOFT_RESET_CG (1 << 2) 1187#define SOFT_RESET_DC (1 << 5) 1188#define SOFT_RESET_GRBM (1 << 8) 1189#define SOFT_RESET_HDP (1 << 9) 1190#define SOFT_RESET_IH (1 << 10) 1191#define SOFT_RESET_MC (1 << 11) 1192#define SOFT_RESET_RLC (1 << 13) 1193#define SOFT_RESET_ROM (1 << 14) 1194#define SOFT_RESET_SEM (1 << 15) 1195#define SOFT_RESET_VMC (1 << 17) 1196#define SOFT_RESET_DMA (1 << 20) 1197#define SOFT_RESET_TST (1 << 21) 1198#define SOFT_RESET_REGBB (1 << 22) 1199#define SOFT_RESET_ORB (1 << 23) 1200 1201#define SRBM_READ_ERROR 0xE98 1202#define SRBM_INT_CNTL 0xEA0 1203#define SRBM_INT_ACK 0xEA8 1204 1205/* display watermarks */ 1206#define DC_LB_MEMORY_SPLIT 0x6b0c 1207#define PRIORITY_A_CNT 0x6b18 1208#define PRIORITY_MARK_MASK 0x7fff 1209#define PRIORITY_OFF (1 << 16) 1210#define PRIORITY_ALWAYS_ON (1 << 20) 1211#define PRIORITY_B_CNT 0x6b1c 1212#define PIPE0_ARBITRATION_CONTROL3 0x0bf0 1213# define LATENCY_WATERMARK_MASK(x) ((x) << 16) 1214#define PIPE0_LATENCY_CONTROL 0x0bf4 1215# define LATENCY_LOW_WATERMARK(x) ((x) << 0) 1216# define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 1217 1218#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 1219# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 1220# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 1221 1222#define IH_RB_CNTL 0x3e00 1223# define IH_RB_ENABLE (1 << 0) 1224# define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 1225# define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 1226# define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 1227# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 1228# define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 1229# define IH_WPTR_OVERFLOW_CLEAR (1 << 31) 1230#define IH_RB_BASE 0x3e04 1231#define IH_RB_RPTR 0x3e08 1232#define IH_RB_WPTR 0x3e0c 1233# define RB_OVERFLOW (1 << 0) 1234# define WPTR_OFFSET_MASK 0x3fffc 1235#define IH_RB_WPTR_ADDR_HI 0x3e10 1236#define IH_RB_WPTR_ADDR_LO 0x3e14 1237#define IH_CNTL 0x3e18 1238# define ENABLE_INTR (1 << 0) 1239# define IH_MC_SWAP(x) ((x) << 1) 1240# define IH_MC_SWAP_NONE 0 1241# define IH_MC_SWAP_16BIT 1 1242# define IH_MC_SWAP_32BIT 2 1243# define IH_MC_SWAP_64BIT 3 1244# define RPTR_REARM (1 << 4) 1245# define MC_WRREQ_CREDIT(x) ((x) << 15) 1246# define MC_WR_CLEAN_CNT(x) ((x) << 20) 1247 1248#define CP_INT_CNTL 0xc124 1249# define CNTX_BUSY_INT_ENABLE (1 << 19) 1250# define CNTX_EMPTY_INT_ENABLE (1 << 20) 1251# define SCRATCH_INT_ENABLE (1 << 25) 1252# define TIME_STAMP_INT_ENABLE (1 << 26) 1253# define IB2_INT_ENABLE (1 << 29) 1254# define IB1_INT_ENABLE (1 << 30) 1255# define RB_INT_ENABLE (1U << 31) 1256#define CP_INT_STATUS 0xc128 1257# define SCRATCH_INT_STAT (1 << 25) 1258# define TIME_STAMP_INT_STAT (1 << 26) 1259# define IB2_INT_STAT (1 << 29) 1260# define IB1_INT_STAT (1 << 30) 1261# define RB_INT_STAT (1 << 31) 1262 1263#define GRBM_INT_CNTL 0x8060 1264# define RDERR_INT_ENABLE (1 << 0) 1265# define GUI_IDLE_INT_ENABLE (1 << 19) 1266 1267/* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 1268#define CRTC_STATUS_FRAME_COUNT 0x6e98 1269 1270/* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 1271#define VLINE_STATUS 0x6bb8 1272# define VLINE_OCCURRED (1 << 0) 1273# define VLINE_ACK (1 << 4) 1274# define VLINE_STAT (1 << 12) 1275# define VLINE_INTERRUPT (1 << 16) 1276# define VLINE_INTERRUPT_TYPE (1 << 17) 1277/* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 1278#define VBLANK_STATUS 0x6bbc 1279# define VBLANK_OCCURRED (1 << 0) 1280# define VBLANK_ACK (1 << 4) 1281# define VBLANK_STAT (1 << 12) 1282# define VBLANK_INTERRUPT (1 << 16) 1283# define VBLANK_INTERRUPT_TYPE (1 << 17) 1284 1285/* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 1286#define INT_MASK 0x6b40 1287# define VBLANK_INT_MASK (1 << 0) 1288# define VLINE_INT_MASK (1 << 4) 1289 1290#define DISP_INTERRUPT_STATUS 0x60f4 1291# define LB_D1_VLINE_INTERRUPT (1 << 2) 1292# define LB_D1_VBLANK_INTERRUPT (1 << 3) 1293# define DC_HPD1_INTERRUPT (1 << 17) 1294# define DC_HPD1_RX_INTERRUPT (1 << 18) 1295# define DACA_AUTODETECT_INTERRUPT (1 << 22) 1296# define DACB_AUTODETECT_INTERRUPT (1 << 23) 1297# define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 1298# define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 1299#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 1300# define LB_D2_VLINE_INTERRUPT (1 << 2) 1301# define LB_D2_VBLANK_INTERRUPT (1 << 3) 1302# define DC_HPD2_INTERRUPT (1 << 17) 1303# define DC_HPD2_RX_INTERRUPT (1 << 18) 1304# define DISP_TIMER_INTERRUPT (1 << 24) 1305#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 1306# define LB_D3_VLINE_INTERRUPT (1 << 2) 1307# define LB_D3_VBLANK_INTERRUPT (1 << 3) 1308# define DC_HPD3_INTERRUPT (1 << 17) 1309# define DC_HPD3_RX_INTERRUPT (1 << 18) 1310#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 1311# define LB_D4_VLINE_INTERRUPT (1 << 2) 1312# define LB_D4_VBLANK_INTERRUPT (1 << 3) 1313# define DC_HPD4_INTERRUPT (1 << 17) 1314# define DC_HPD4_RX_INTERRUPT (1 << 18) 1315#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 1316# define LB_D5_VLINE_INTERRUPT (1 << 2) 1317# define LB_D5_VBLANK_INTERRUPT (1 << 3) 1318# define DC_HPD5_INTERRUPT (1 << 17) 1319# define DC_HPD5_RX_INTERRUPT (1 << 18) 1320#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 1321# define LB_D6_VLINE_INTERRUPT (1 << 2) 1322# define LB_D6_VBLANK_INTERRUPT (1 << 3) 1323# define DC_HPD6_INTERRUPT (1 << 17) 1324# define DC_HPD6_RX_INTERRUPT (1 << 18) 1325 1326/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 1327#define GRPH_INT_STATUS 0x6858 1328# define GRPH_PFLIP_INT_OCCURRED (1 << 0) 1329# define GRPH_PFLIP_INT_CLEAR (1 << 8) 1330/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 1331#define GRPH_INT_CONTROL 0x685c 1332# define GRPH_PFLIP_INT_MASK (1 << 0) 1333# define GRPH_PFLIP_INT_TYPE (1 << 8) 1334 1335#define DACA_AUTODETECT_INT_CONTROL 0x66c8 1336#define DACB_AUTODETECT_INT_CONTROL 0x67c8 1337 1338#define DC_HPD1_INT_STATUS 0x601c 1339#define DC_HPD2_INT_STATUS 0x6028 1340#define DC_HPD3_INT_STATUS 0x6034 1341#define DC_HPD4_INT_STATUS 0x6040 1342#define DC_HPD5_INT_STATUS 0x604c 1343#define DC_HPD6_INT_STATUS 0x6058 1344# define DC_HPDx_INT_STATUS (1 << 0) 1345# define DC_HPDx_SENSE (1 << 1) 1346# define DC_HPDx_RX_INT_STATUS (1 << 8) 1347 1348#define DC_HPD1_INT_CONTROL 0x6020 1349#define DC_HPD2_INT_CONTROL 0x602c 1350#define DC_HPD3_INT_CONTROL 0x6038 1351#define DC_HPD4_INT_CONTROL 0x6044 1352#define DC_HPD5_INT_CONTROL 0x6050 1353#define DC_HPD6_INT_CONTROL 0x605c 1354# define DC_HPDx_INT_ACK (1 << 0) 1355# define DC_HPDx_INT_POLARITY (1 << 8) 1356# define DC_HPDx_INT_EN (1 << 16) 1357# define DC_HPDx_RX_INT_ACK (1 << 20) 1358# define DC_HPDx_RX_INT_EN (1 << 24) 1359 1360#define DC_HPD1_CONTROL 0x6024 1361#define DC_HPD2_CONTROL 0x6030 1362#define DC_HPD3_CONTROL 0x603c 1363#define DC_HPD4_CONTROL 0x6048 1364#define DC_HPD5_CONTROL 0x6054 1365#define DC_HPD6_CONTROL 0x6060 1366# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 1367# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 1368# define DC_HPDx_EN (1 << 28) 1369 1370/* DCE4/5/6 FMT blocks */ 1371#define FMT_DYNAMIC_EXP_CNTL 0x6fb4 1372# define FMT_DYNAMIC_EXP_EN (1 << 0) 1373# define FMT_DYNAMIC_EXP_MODE (1 << 4) 1374 /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */ 1375#define FMT_CONTROL 0x6fb8 1376# define FMT_PIXEL_ENCODING (1 << 16) 1377 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */ 1378#define FMT_BIT_DEPTH_CONTROL 0x6fc8 1379# define FMT_TRUNCATE_EN (1 << 0) 1380# define FMT_TRUNCATE_DEPTH (1 << 4) 1381# define FMT_SPATIAL_DITHER_EN (1 << 8) 1382# define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) 1383# define FMT_SPATIAL_DITHER_DEPTH (1 << 12) 1384# define FMT_FRAME_RANDOM_ENABLE (1 << 13) 1385# define FMT_RGB_RANDOM_ENABLE (1 << 14) 1386# define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15) 1387# define FMT_TEMPORAL_DITHER_EN (1 << 16) 1388# define FMT_TEMPORAL_DITHER_DEPTH (1 << 20) 1389# define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) 1390# define FMT_TEMPORAL_LEVEL (1 << 24) 1391# define FMT_TEMPORAL_DITHER_RESET (1 << 25) 1392# define FMT_25FRC_SEL(x) ((x) << 26) 1393# define FMT_50FRC_SEL(x) ((x) << 28) 1394# define FMT_75FRC_SEL(x) ((x) << 30) 1395#define FMT_CLAMP_CONTROL 0x6fe4 1396# define FMT_CLAMP_DATA_EN (1 << 0) 1397# define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) 1398# define FMT_CLAMP_6BPC 0 1399# define FMT_CLAMP_8BPC 1 1400# define FMT_CLAMP_10BPC 2 1401 1402/* ASYNC DMA */ 1403#define DMA_RB_RPTR 0xd008 1404#define DMA_RB_WPTR 0xd00c 1405 1406#define DMA_CNTL 0xd02c 1407# define TRAP_ENABLE (1 << 0) 1408# define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1409# define SEM_WAIT_INT_ENABLE (1 << 2) 1410# define DATA_SWAP_ENABLE (1 << 3) 1411# define FENCE_SWAP_ENABLE (1 << 4) 1412# define CTXEMPTY_INT_ENABLE (1 << 28) 1413#define DMA_TILING_CONFIG 0xD0B8 1414 1415#define CAYMAN_DMA1_CNTL 0xd82c 1416 1417/* async DMA packets */ 1418#define DMA_PACKET(cmd, sub_cmd, n) ((((uint32_t)(cmd) & 0xF) << 28) | \ 1419 (((sub_cmd) & 0xFF) << 20) |\ 1420 (((n) & 0xFFFFF) << 0)) 1421#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28) 1422#define GET_DMA_COUNT(h) ((h) & 0x000fffff) 1423#define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20) 1424 1425/* async DMA Packet types */ 1426#define DMA_PACKET_WRITE 0x2 1427#define DMA_PACKET_COPY 0x3 1428#define DMA_PACKET_INDIRECT_BUFFER 0x4 1429#define DMA_PACKET_SEMAPHORE 0x5 1430#define DMA_PACKET_FENCE 0x6 1431#define DMA_PACKET_TRAP 0x7 1432#define DMA_PACKET_SRBM_WRITE 0x9 1433#define DMA_PACKET_CONSTANT_FILL 0xd 1434#define DMA_PACKET_NOP 0xf 1435 1436/* PIF PHY0 indirect regs */ 1437#define PB0_PIF_CNTL 0x10 1438# define LS2_EXIT_TIME(x) ((x) << 17) 1439# define LS2_EXIT_TIME_MASK (0x7 << 17) 1440# define LS2_EXIT_TIME_SHIFT 17 1441#define PB0_PIF_PAIRING 0x11 1442# define MULTI_PIF (1 << 25) 1443#define PB0_PIF_PWRDOWN_0 0x12 1444# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 1445# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 1446# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 1447# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 1448# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 1449# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 1450# define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 1451# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 1452# define PLL_RAMP_UP_TIME_0_SHIFT 24 1453#define PB0_PIF_PWRDOWN_1 0x13 1454# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 1455# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 1456# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 1457# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 1458# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 1459# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 1460# define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 1461# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 1462# define PLL_RAMP_UP_TIME_1_SHIFT 24 1463/* PIF PHY1 indirect regs */ 1464#define PB1_PIF_CNTL 0x10 1465#define PB1_PIF_PAIRING 0x11 1466#define PB1_PIF_PWRDOWN_0 0x12 1467#define PB1_PIF_PWRDOWN_1 0x13 1468/* PCIE PORT indirect regs */ 1469#define PCIE_LC_CNTL 0xa0 1470# define LC_L0S_INACTIVITY(x) ((x) << 8) 1471# define LC_L0S_INACTIVITY_MASK (0xf << 8) 1472# define LC_L0S_INACTIVITY_SHIFT 8 1473# define LC_L1_INACTIVITY(x) ((x) << 12) 1474# define LC_L1_INACTIVITY_MASK (0xf << 12) 1475# define LC_L1_INACTIVITY_SHIFT 12 1476# define LC_PMI_TO_L1_DIS (1 << 16) 1477# define LC_ASPM_TO_L1_DIS (1 << 24) 1478#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 1479#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 1480# define LC_LINK_WIDTH_SHIFT 0 1481# define LC_LINK_WIDTH_MASK 0x7 1482# define LC_LINK_WIDTH_X0 0 1483# define LC_LINK_WIDTH_X1 1 1484# define LC_LINK_WIDTH_X2 2 1485# define LC_LINK_WIDTH_X4 3 1486# define LC_LINK_WIDTH_X8 4 1487# define LC_LINK_WIDTH_X16 6 1488# define LC_LINK_WIDTH_RD_SHIFT 4 1489# define LC_LINK_WIDTH_RD_MASK 0x70 1490# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 1491# define LC_RECONFIG_NOW (1 << 8) 1492# define LC_RENEGOTIATION_SUPPORT (1 << 9) 1493# define LC_RENEGOTIATE_EN (1 << 10) 1494# define LC_SHORT_RECONFIG_EN (1 << 11) 1495# define LC_UPCONFIGURE_SUPPORT (1 << 12) 1496# define LC_UPCONFIGURE_DIS (1 << 13) 1497# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 1498# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 1499# define LC_DYN_LANES_PWR_STATE_SHIFT 21 1500#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 1501# define LC_GEN2_EN_STRAP (1 << 0) 1502# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 1503# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 1504# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 1505# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 1506# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 1507# define LC_CURRENT_DATA_RATE (1 << 11) 1508# define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 1509# define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 1510# define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 1511# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 1512# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 1513# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 1514# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 1515#define MM_CFGREGS_CNTL 0x544c 1516# define MM_WR_TO_CFG_EN (1 << 3) 1517#define LINK_CNTL2 0x88 /* F0 */ 1518# define TARGET_LINK_SPEED_MASK (0xf << 0) 1519# define SELECTABLE_DEEMPHASIS (1 << 6) 1520 1521 1522/* 1523 * UVD 1524 */ 1525#define UVD_UDEC_ADDR_CONFIG 0xef4c 1526#define UVD_UDEC_DB_ADDR_CONFIG 0xef50 1527#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54 1528#define UVD_NO_OP 0xeffc 1529#define UVD_RBC_RB_RPTR 0xf690 1530#define UVD_RBC_RB_WPTR 0xf694 1531#define UVD_STATUS 0xf6bc 1532 1533/* 1534 * PM4 1535 */ 1536#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1537 (((reg) >> 2) & 0xFFFF) | \ 1538 ((n) & 0x3FFF) << 16) 1539#define CP_PACKET2 0x80000000 1540#define PACKET2_PAD_SHIFT 0 1541#define PACKET2_PAD_MASK (0x3fffffff << 0) 1542 1543#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1544 1545#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1546 (((op) & 0xFF) << 8) | \ 1547 ((n) & 0x3FFF) << 16) 1548 1549/* Packet 3 types */ 1550#define PACKET3_NOP 0x10 1551#define PACKET3_SET_BASE 0x11 1552#define PACKET3_CLEAR_STATE 0x12 1553#define PACKET3_INDEX_BUFFER_SIZE 0x13 1554#define PACKET3_DISPATCH_DIRECT 0x15 1555#define PACKET3_DISPATCH_INDIRECT 0x16 1556#define PACKET3_INDIRECT_BUFFER_END 0x17 1557#define PACKET3_MODE_CONTROL 0x18 1558#define PACKET3_SET_PREDICATION 0x20 1559#define PACKET3_REG_RMW 0x21 1560#define PACKET3_COND_EXEC 0x22 1561#define PACKET3_PRED_EXEC 0x23 1562#define PACKET3_DRAW_INDIRECT 0x24 1563#define PACKET3_DRAW_INDEX_INDIRECT 0x25 1564#define PACKET3_INDEX_BASE 0x26 1565#define PACKET3_DRAW_INDEX_2 0x27 1566#define PACKET3_CONTEXT_CONTROL 0x28 1567#define PACKET3_DRAW_INDEX_OFFSET 0x29 1568#define PACKET3_INDEX_TYPE 0x2A 1569#define PACKET3_DRAW_INDEX 0x2B 1570#define PACKET3_DRAW_INDEX_AUTO 0x2D 1571#define PACKET3_DRAW_INDEX_IMMD 0x2E 1572#define PACKET3_NUM_INSTANCES 0x2F 1573#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1574#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1575#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1576#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1577#define PACKET3_MEM_SEMAPHORE 0x39 1578#define PACKET3_MPEG_INDEX 0x3A 1579#define PACKET3_COPY_DW 0x3B 1580#define PACKET3_WAIT_REG_MEM 0x3C 1581#define PACKET3_MEM_WRITE 0x3D 1582#define PACKET3_INDIRECT_BUFFER 0x32 1583#define PACKET3_CP_DMA 0x41 1584/* 1. header 1585 * 2. SRC_ADDR_LO or DATA [31:0] 1586 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 1587 * SRC_ADDR_HI [7:0] 1588 * 4. DST_ADDR_LO [31:0] 1589 * 5. DST_ADDR_HI [7:0] 1590 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1591 */ 1592# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1593 /* 0 - DST_ADDR 1594 * 1 - GDS 1595 */ 1596# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 1597 /* 0 - ME 1598 * 1 - PFP 1599 */ 1600# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 1601 /* 0 - SRC_ADDR 1602 * 1 - GDS 1603 * 2 - DATA 1604 */ 1605# define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1606/* COMMAND */ 1607# define PACKET3_CP_DMA_DIS_WC (1 << 21) 1608# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1609 /* 0 - none 1610 * 1 - 8 in 16 1611 * 2 - 8 in 32 1612 * 3 - 8 in 64 1613 */ 1614# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1615 /* 0 - none 1616 * 1 - 8 in 16 1617 * 2 - 8 in 32 1618 * 3 - 8 in 64 1619 */ 1620# define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1621 /* 0 - memory 1622 * 1 - register 1623 */ 1624# define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1625 /* 0 - memory 1626 * 1 - register 1627 */ 1628# define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1629# define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1630#define PACKET3_PFP_SYNC_ME 0x42 1631#define PACKET3_SURFACE_SYNC 0x43 1632# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1633# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1634# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1635# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1636# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1637# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1638# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1639# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1640# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1641# define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 1642# define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 1643# define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 1644# define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 1645# define PACKET3_FULL_CACHE_ENA (1 << 20) 1646# define PACKET3_TC_ACTION_ENA (1 << 23) 1647# define PACKET3_VC_ACTION_ENA (1 << 24) 1648# define PACKET3_CB_ACTION_ENA (1 << 25) 1649# define PACKET3_DB_ACTION_ENA (1 << 26) 1650# define PACKET3_SH_ACTION_ENA (1 << 27) 1651# define PACKET3_SX_ACTION_ENA (1 << 28) 1652#define PACKET3_ME_INITIALIZE 0x44 1653#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1654#define PACKET3_COND_WRITE 0x45 1655#define PACKET3_EVENT_WRITE 0x46 1656#define PACKET3_EVENT_WRITE_EOP 0x47 1657#define PACKET3_EVENT_WRITE_EOS 0x48 1658#define PACKET3_PREAMBLE_CNTL 0x4A 1659# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1660# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1661#define PACKET3_RB_OFFSET 0x4B 1662#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 1663#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 1664#define PACKET3_ALU_PS_CONST_UPDATE 0x4E 1665#define PACKET3_ALU_VS_CONST_UPDATE 0x4F 1666#define PACKET3_ONE_REG_WRITE 0x57 1667#define PACKET3_SET_CONFIG_REG 0x68 1668#define PACKET3_SET_CONFIG_REG_START 0x00008000 1669#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1670#define PACKET3_SET_CONTEXT_REG 0x69 1671#define PACKET3_SET_CONTEXT_REG_START 0x00028000 1672#define PACKET3_SET_CONTEXT_REG_END 0x00029000 1673#define PACKET3_SET_ALU_CONST 0x6A 1674/* alu const buffers only; no reg file */ 1675#define PACKET3_SET_BOOL_CONST 0x6B 1676#define PACKET3_SET_BOOL_CONST_START 0x0003a500 1677#define PACKET3_SET_BOOL_CONST_END 0x0003a518 1678#define PACKET3_SET_LOOP_CONST 0x6C 1679#define PACKET3_SET_LOOP_CONST_START 0x0003a200 1680#define PACKET3_SET_LOOP_CONST_END 0x0003a500 1681#define PACKET3_SET_RESOURCE 0x6D 1682#define PACKET3_SET_RESOURCE_START 0x00030000 1683#define PACKET3_SET_RESOURCE_END 0x00038000 1684#define PACKET3_SET_SAMPLER 0x6E 1685#define PACKET3_SET_SAMPLER_START 0x0003c000 1686#define PACKET3_SET_SAMPLER_END 0x0003c600 1687#define PACKET3_SET_CTL_CONST 0x6F 1688#define PACKET3_SET_CTL_CONST_START 0x0003cff0 1689#define PACKET3_SET_CTL_CONST_END 0x0003ff0c 1690#define PACKET3_SET_RESOURCE_OFFSET 0x70 1691#define PACKET3_SET_ALU_CONST_VS 0x71 1692#define PACKET3_SET_ALU_CONST_DI 0x72 1693#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1694#define PACKET3_SET_RESOURCE_INDIRECT 0x74 1695#define PACKET3_SET_APPEND_CNT 0x75 1696/* SET_APPEND_CNT - documentation 1697 * 1. header 1698 * 2. COMMAND 1699 * 1:0 - SOURCE SEL 1700 * 15:2 - Reserved 1701 * 31:16 - WR_REG_OFFSET - context register to write source data to. 1702 * (one of R_02872C_GDS_APPEND_COUNT_0-11) 1703 * 3. CONTROL 1704 * (for source == mem) 1705 * 31:2 SRC_ADDRESS_LO 1706 * 0:1 SWAP 1707 * (for source == GDS) 1708 * 31:0 GDS offset 1709 * (for source == DATA) 1710 * 31:0 DATA 1711 * (for source == REG) 1712 * 31:0 REG 1713 * 4. SRC_ADDRESS_HI[7:0] 1714 * kernel driver 2.44 only supports SRC == MEM. 1715 */ 1716#define PACKET3_SET_APPEND_CNT_SRC_SELECT(x) ((x) << 0) 1717#define G_PACKET3_SET_APPEND_CNT_SRC_SELECT(x) ((x & 0x3) >> 0) 1718/* source is from the data in CONTROL */ 1719#define PACKET3_SAC_SRC_SEL_DATA 0x0 1720/* source is from register */ 1721#define PACKET3_SAC_SRC_SEL_REG 0x1 1722/* source is from GDS offset in CONTROL */ 1723#define PACKET3_SAC_SRC_SEL_GDS 0x2 1724/* source is from memory address */ 1725#define PACKET3_SAC_SRC_SEL_MEM 0x3 1726 1727#define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c 1728#define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30) 1729#define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3) 1730#define SQ_TEX_VTX_INVALID_TEXTURE 0x0 1731#define SQ_TEX_VTX_INVALID_BUFFER 0x1 1732#define SQ_TEX_VTX_VALID_TEXTURE 0x2 1733#define SQ_TEX_VTX_VALID_BUFFER 0x3 1734 1735#define VGT_VTX_VECT_EJECT_REG 0x88b0 1736 1737#define SQ_CONST_MEM_BASE 0x8df8 1738 1739#define SQ_ESGS_RING_BASE 0x8c40 1740#define SQ_ESGS_RING_SIZE 0x8c44 1741#define SQ_GSVS_RING_BASE 0x8c48 1742#define SQ_GSVS_RING_SIZE 0x8c4c 1743#define SQ_ESTMP_RING_BASE 0x8c50 1744#define SQ_ESTMP_RING_SIZE 0x8c54 1745#define SQ_GSTMP_RING_BASE 0x8c58 1746#define SQ_GSTMP_RING_SIZE 0x8c5c 1747#define SQ_VSTMP_RING_BASE 0x8c60 1748#define SQ_VSTMP_RING_SIZE 0x8c64 1749#define SQ_PSTMP_RING_BASE 0x8c68 1750#define SQ_PSTMP_RING_SIZE 0x8c6c 1751#define SQ_LSTMP_RING_BASE 0x8e10 1752#define SQ_LSTMP_RING_SIZE 0x8e14 1753#define SQ_HSTMP_RING_BASE 0x8e18 1754#define SQ_HSTMP_RING_SIZE 0x8e1c 1755#define VGT_TF_RING_SIZE 0x8988 1756 1757#define SQ_ESGS_RING_ITEMSIZE 0x28900 1758#define SQ_GSVS_RING_ITEMSIZE 0x28904 1759#define SQ_ESTMP_RING_ITEMSIZE 0x28908 1760#define SQ_GSTMP_RING_ITEMSIZE 0x2890c 1761#define SQ_VSTMP_RING_ITEMSIZE 0x28910 1762#define SQ_PSTMP_RING_ITEMSIZE 0x28914 1763#define SQ_LSTMP_RING_ITEMSIZE 0x28830 1764#define SQ_HSTMP_RING_ITEMSIZE 0x28834 1765 1766#define SQ_GS_VERT_ITEMSIZE 0x2891c 1767#define SQ_GS_VERT_ITEMSIZE_1 0x28920 1768#define SQ_GS_VERT_ITEMSIZE_2 0x28924 1769#define SQ_GS_VERT_ITEMSIZE_3 0x28928 1770#define SQ_GSVS_RING_OFFSET_1 0x2892c 1771#define SQ_GSVS_RING_OFFSET_2 0x28930 1772#define SQ_GSVS_RING_OFFSET_3 0x28934 1773 1774#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140 1775#define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80 1776 1777#define SQ_ALU_CONST_CACHE_PS_0 0x28940 1778#define SQ_ALU_CONST_CACHE_PS_1 0x28944 1779#define SQ_ALU_CONST_CACHE_PS_2 0x28948 1780#define SQ_ALU_CONST_CACHE_PS_3 0x2894c 1781#define SQ_ALU_CONST_CACHE_PS_4 0x28950 1782#define SQ_ALU_CONST_CACHE_PS_5 0x28954 1783#define SQ_ALU_CONST_CACHE_PS_6 0x28958 1784#define SQ_ALU_CONST_CACHE_PS_7 0x2895c 1785#define SQ_ALU_CONST_CACHE_PS_8 0x28960 1786#define SQ_ALU_CONST_CACHE_PS_9 0x28964 1787#define SQ_ALU_CONST_CACHE_PS_10 0x28968 1788#define SQ_ALU_CONST_CACHE_PS_11 0x2896c 1789#define SQ_ALU_CONST_CACHE_PS_12 0x28970 1790#define SQ_ALU_CONST_CACHE_PS_13 0x28974 1791#define SQ_ALU_CONST_CACHE_PS_14 0x28978 1792#define SQ_ALU_CONST_CACHE_PS_15 0x2897c 1793#define SQ_ALU_CONST_CACHE_VS_0 0x28980 1794#define SQ_ALU_CONST_CACHE_VS_1 0x28984 1795#define SQ_ALU_CONST_CACHE_VS_2 0x28988 1796#define SQ_ALU_CONST_CACHE_VS_3 0x2898c 1797#define SQ_ALU_CONST_CACHE_VS_4 0x28990 1798#define SQ_ALU_CONST_CACHE_VS_5 0x28994 1799#define SQ_ALU_CONST_CACHE_VS_6 0x28998 1800#define SQ_ALU_CONST_CACHE_VS_7 0x2899c 1801#define SQ_ALU_CONST_CACHE_VS_8 0x289a0 1802#define SQ_ALU_CONST_CACHE_VS_9 0x289a4 1803#define SQ_ALU_CONST_CACHE_VS_10 0x289a8 1804#define SQ_ALU_CONST_CACHE_VS_11 0x289ac 1805#define SQ_ALU_CONST_CACHE_VS_12 0x289b0 1806#define SQ_ALU_CONST_CACHE_VS_13 0x289b4 1807#define SQ_ALU_CONST_CACHE_VS_14 0x289b8 1808#define SQ_ALU_CONST_CACHE_VS_15 0x289bc 1809#define SQ_ALU_CONST_CACHE_GS_0 0x289c0 1810#define SQ_ALU_CONST_CACHE_GS_1 0x289c4 1811#define SQ_ALU_CONST_CACHE_GS_2 0x289c8 1812#define SQ_ALU_CONST_CACHE_GS_3 0x289cc 1813#define SQ_ALU_CONST_CACHE_GS_4 0x289d0 1814#define SQ_ALU_CONST_CACHE_GS_5 0x289d4 1815#define SQ_ALU_CONST_CACHE_GS_6 0x289d8 1816#define SQ_ALU_CONST_CACHE_GS_7 0x289dc 1817#define SQ_ALU_CONST_CACHE_GS_8 0x289e0 1818#define SQ_ALU_CONST_CACHE_GS_9 0x289e4 1819#define SQ_ALU_CONST_CACHE_GS_10 0x289e8 1820#define SQ_ALU_CONST_CACHE_GS_11 0x289ec 1821#define SQ_ALU_CONST_CACHE_GS_12 0x289f0 1822#define SQ_ALU_CONST_CACHE_GS_13 0x289f4 1823#define SQ_ALU_CONST_CACHE_GS_14 0x289f8 1824#define SQ_ALU_CONST_CACHE_GS_15 0x289fc 1825#define SQ_ALU_CONST_CACHE_HS_0 0x28f00 1826#define SQ_ALU_CONST_CACHE_HS_1 0x28f04 1827#define SQ_ALU_CONST_CACHE_HS_2 0x28f08 1828#define SQ_ALU_CONST_CACHE_HS_3 0x28f0c 1829#define SQ_ALU_CONST_CACHE_HS_4 0x28f10 1830#define SQ_ALU_CONST_CACHE_HS_5 0x28f14 1831#define SQ_ALU_CONST_CACHE_HS_6 0x28f18 1832#define SQ_ALU_CONST_CACHE_HS_7 0x28f1c 1833#define SQ_ALU_CONST_CACHE_HS_8 0x28f20 1834#define SQ_ALU_CONST_CACHE_HS_9 0x28f24 1835#define SQ_ALU_CONST_CACHE_HS_10 0x28f28 1836#define SQ_ALU_CONST_CACHE_HS_11 0x28f2c 1837#define SQ_ALU_CONST_CACHE_HS_12 0x28f30 1838#define SQ_ALU_CONST_CACHE_HS_13 0x28f34 1839#define SQ_ALU_CONST_CACHE_HS_14 0x28f38 1840#define SQ_ALU_CONST_CACHE_HS_15 0x28f3c 1841#define SQ_ALU_CONST_CACHE_LS_0 0x28f40 1842#define SQ_ALU_CONST_CACHE_LS_1 0x28f44 1843#define SQ_ALU_CONST_CACHE_LS_2 0x28f48 1844#define SQ_ALU_CONST_CACHE_LS_3 0x28f4c 1845#define SQ_ALU_CONST_CACHE_LS_4 0x28f50 1846#define SQ_ALU_CONST_CACHE_LS_5 0x28f54 1847#define SQ_ALU_CONST_CACHE_LS_6 0x28f58 1848#define SQ_ALU_CONST_CACHE_LS_7 0x28f5c 1849#define SQ_ALU_CONST_CACHE_LS_8 0x28f60 1850#define SQ_ALU_CONST_CACHE_LS_9 0x28f64 1851#define SQ_ALU_CONST_CACHE_LS_10 0x28f68 1852#define SQ_ALU_CONST_CACHE_LS_11 0x28f6c 1853#define SQ_ALU_CONST_CACHE_LS_12 0x28f70 1854#define SQ_ALU_CONST_CACHE_LS_13 0x28f74 1855#define SQ_ALU_CONST_CACHE_LS_14 0x28f78 1856#define SQ_ALU_CONST_CACHE_LS_15 0x28f7c 1857 1858#define PA_SC_SCREEN_SCISSOR_TL 0x28030 1859#define PA_SC_GENERIC_SCISSOR_TL 0x28240 1860#define PA_SC_WINDOW_SCISSOR_TL 0x28204 1861 1862#define VGT_PRIMITIVE_TYPE 0x8958 1863#define VGT_INDEX_TYPE 0x895C 1864 1865#define VGT_NUM_INDICES 0x8970 1866 1867#define VGT_COMPUTE_DIM_X 0x8990 1868#define VGT_COMPUTE_DIM_Y 0x8994 1869#define VGT_COMPUTE_DIM_Z 0x8998 1870#define VGT_COMPUTE_START_X 0x899C 1871#define VGT_COMPUTE_START_Y 0x89A0 1872#define VGT_COMPUTE_START_Z 0x89A4 1873#define VGT_COMPUTE_INDEX 0x89A8 1874#define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC 1875#define VGT_HS_OFFCHIP_PARAM 0x89B0 1876 1877#define DB_DEBUG 0x9830 1878#define DB_DEBUG2 0x9834 1879#define DB_DEBUG3 0x9838 1880#define DB_DEBUG4 0x983C 1881#define DB_WATERMARKS 0x9854 1882#define DB_DEPTH_CONTROL 0x28800 1883#define R_028800_DB_DEPTH_CONTROL 0x028800 1884#define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1885#define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1886#define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1887#define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1888#define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1889#define C_028800_Z_ENABLE 0xFFFFFFFD 1890#define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1891#define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1892#define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1893#define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1894#define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1895#define C_028800_ZFUNC 0xFFFFFF8F 1896#define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1897#define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1898#define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1899#define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1900#define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1901#define C_028800_STENCILFUNC 0xFFFFF8FF 1902#define V_028800_STENCILFUNC_NEVER 0x00000000 1903#define V_028800_STENCILFUNC_LESS 0x00000001 1904#define V_028800_STENCILFUNC_EQUAL 0x00000002 1905#define V_028800_STENCILFUNC_LEQUAL 0x00000003 1906#define V_028800_STENCILFUNC_GREATER 0x00000004 1907#define V_028800_STENCILFUNC_NOTEQUAL 0x00000005 1908#define V_028800_STENCILFUNC_GEQUAL 0x00000006 1909#define V_028800_STENCILFUNC_ALWAYS 0x00000007 1910#define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1911#define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1912#define C_028800_STENCILFAIL 0xFFFFC7FF 1913#define V_028800_STENCIL_KEEP 0x00000000 1914#define V_028800_STENCIL_ZERO 0x00000001 1915#define V_028800_STENCIL_REPLACE 0x00000002 1916#define V_028800_STENCIL_INCR 0x00000003 1917#define V_028800_STENCIL_DECR 0x00000004 1918#define V_028800_STENCIL_INVERT 0x00000005 1919#define V_028800_STENCIL_INCR_WRAP 0x00000006 1920#define V_028800_STENCIL_DECR_WRAP 0x00000007 1921#define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1922#define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1923#define C_028800_STENCILZPASS 0xFFFE3FFF 1924#define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1925#define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1926#define C_028800_STENCILZFAIL 0xFFF1FFFF 1927#define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1928#define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1929#define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1930#define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1931#define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1932#define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1933#define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1934#define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1935#define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1936#define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1937#define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1938#define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1939#define DB_DEPTH_VIEW 0x28008 1940#define R_028008_DB_DEPTH_VIEW 0x00028008 1941#define S_028008_SLICE_START(x) (((x) & 0x7FF) << 0) 1942#define G_028008_SLICE_START(x) (((x) >> 0) & 0x7FF) 1943#define C_028008_SLICE_START 0xFFFFF800 1944#define S_028008_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1945#define G_028008_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1946#define C_028008_SLICE_MAX 0xFF001FFF 1947#define DB_HTILE_DATA_BASE 0x28014 1948#define DB_HTILE_SURFACE 0x28abc 1949#define S_028ABC_HTILE_WIDTH(x) (((x) & 0x1) << 0) 1950#define G_028ABC_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 1951#define C_028ABC_HTILE_WIDTH 0xFFFFFFFE 1952#define S_028ABC_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 1953#define G_028ABC_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 1954#define C_028ABC_HTILE_HEIGHT 0xFFFFFFFD 1955#define G_028ABC_LINEAR(x) (((x) >> 2) & 0x1) 1956#define DB_Z_INFO 0x28040 1957# define Z_ARRAY_MODE(x) ((x) << 4) 1958# define DB_TILE_SPLIT(x) (((x) & 0x7) << 8) 1959# define DB_NUM_BANKS(x) (((x) & 0x3) << 12) 1960# define DB_BANK_WIDTH(x) (((x) & 0x3) << 16) 1961# define DB_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1962# define DB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1963#define R_028040_DB_Z_INFO 0x028040 1964#define S_028040_FORMAT(x) (((x) & 0x3) << 0) 1965#define G_028040_FORMAT(x) (((x) >> 0) & 0x3) 1966#define C_028040_FORMAT 0xFFFFFFFC 1967#define V_028040_Z_INVALID 0x00000000 1968#define V_028040_Z_16 0x00000001 1969#define V_028040_Z_24 0x00000002 1970#define V_028040_Z_32_FLOAT 0x00000003 1971#define S_028040_ARRAY_MODE(x) (((x) & 0xF) << 4) 1972#define G_028040_ARRAY_MODE(x) (((x) >> 4) & 0xF) 1973#define C_028040_ARRAY_MODE 0xFFFFFF0F 1974#define S_028040_READ_SIZE(x) (((x) & 0x1) << 28) 1975#define G_028040_READ_SIZE(x) (((x) >> 28) & 0x1) 1976#define C_028040_READ_SIZE 0xEFFFFFFF 1977#define S_028040_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 29) 1978#define G_028040_TILE_SURFACE_ENABLE(x) (((x) >> 29) & 0x1) 1979#define C_028040_TILE_SURFACE_ENABLE 0xDFFFFFFF 1980#define S_028040_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1981#define G_028040_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1982#define C_028040_ZRANGE_PRECISION 0x7FFFFFFF 1983#define S_028040_TILE_SPLIT(x) (((x) & 0x7) << 8) 1984#define G_028040_TILE_SPLIT(x) (((x) >> 8) & 0x7) 1985#define S_028040_NUM_BANKS(x) (((x) & 0x3) << 12) 1986#define G_028040_NUM_BANKS(x) (((x) >> 12) & 0x3) 1987#define S_028040_BANK_WIDTH(x) (((x) & 0x3) << 16) 1988#define G_028040_BANK_WIDTH(x) (((x) >> 16) & 0x3) 1989#define S_028040_BANK_HEIGHT(x) (((x) & 0x3) << 20) 1990#define G_028040_BANK_HEIGHT(x) (((x) >> 20) & 0x3) 1991#define S_028040_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 24) 1992#define G_028040_MACRO_TILE_ASPECT(x) (((x) >> 24) & 0x3) 1993#define DB_STENCIL_INFO 0x28044 1994#define R_028044_DB_STENCIL_INFO 0x028044 1995#define S_028044_FORMAT(x) (((x) & 0x1) << 0) 1996#define G_028044_FORMAT(x) (((x) >> 0) & 0x1) 1997#define C_028044_FORMAT 0xFFFFFFFE 1998#define V_028044_STENCIL_INVALID 0 1999#define V_028044_STENCIL_8 1 2000#define G_028044_TILE_SPLIT(x) (((x) >> 8) & 0x7) 2001#define DB_Z_READ_BASE 0x28048 2002#define DB_STENCIL_READ_BASE 0x2804c 2003#define DB_Z_WRITE_BASE 0x28050 2004#define DB_STENCIL_WRITE_BASE 0x28054 2005#define DB_DEPTH_SIZE 0x28058 2006#define R_028058_DB_DEPTH_SIZE 0x028058 2007#define S_028058_PITCH_TILE_MAX(x) (((x) & 0x7FF) << 0) 2008#define G_028058_PITCH_TILE_MAX(x) (((x) >> 0) & 0x7FF) 2009#define C_028058_PITCH_TILE_MAX 0xFFFFF800 2010#define S_028058_HEIGHT_TILE_MAX(x) (((x) & 0x7FF) << 11) 2011#define G_028058_HEIGHT_TILE_MAX(x) (((x) >> 11) & 0x7FF) 2012#define C_028058_HEIGHT_TILE_MAX 0xFFC007FF 2013#define R_02805C_DB_DEPTH_SLICE 0x02805C 2014#define S_02805C_SLICE_TILE_MAX(x) (((x) & 0x3FFFFF) << 0) 2015#define G_02805C_SLICE_TILE_MAX(x) (((x) >> 0) & 0x3FFFFF) 2016#define C_02805C_SLICE_TILE_MAX 0xFFC00000 2017 2018#define SQ_PGM_START_PS 0x28840 2019#define SQ_PGM_START_VS 0x2885c 2020#define SQ_PGM_START_GS 0x28874 2021#define SQ_PGM_START_ES 0x2888c 2022#define SQ_PGM_START_FS 0x288a4 2023#define SQ_PGM_START_HS 0x288b8 2024#define SQ_PGM_START_LS 0x288d0 2025 2026#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 2027#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 2028#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 2029#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 2030#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 2031#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 2032#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 2033#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 2034#define VGT_STRMOUT_CONFIG 0x28b94 2035#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 2036 2037#define CB_TARGET_MASK 0x28238 2038#define CB_SHADER_MASK 0x2823c 2039 2040#define GDS_ADDR_BASE 0x28720 2041 2042#define GDS_APPEND_COUNT_0 0x2872C 2043#define GDS_APPEND_COUNT_1 0x28730 2044#define GDS_APPEND_COUNT_2 0x28734 2045#define GDS_APPEND_COUNT_3 0x28738 2046#define GDS_APPEND_COUNT_4 0x2873C 2047#define GDS_APPEND_COUNT_5 0x28740 2048#define GDS_APPEND_COUNT_6 0x28744 2049#define GDS_APPEND_COUNT_7 0x28748 2050#define GDS_APPEND_COUNT_8 0x2874c 2051#define GDS_APPEND_COUNT_9 0x28750 2052#define GDS_APPEND_COUNT_10 0x28754 2053#define GDS_APPEND_COUNT_11 0x28758 2054 2055#define CB_IMMED0_BASE 0x28b9c 2056#define CB_IMMED1_BASE 0x28ba0 2057#define CB_IMMED2_BASE 0x28ba4 2058#define CB_IMMED3_BASE 0x28ba8 2059#define CB_IMMED4_BASE 0x28bac 2060#define CB_IMMED5_BASE 0x28bb0 2061#define CB_IMMED6_BASE 0x28bb4 2062#define CB_IMMED7_BASE 0x28bb8 2063#define CB_IMMED8_BASE 0x28bbc 2064#define CB_IMMED9_BASE 0x28bc0 2065#define CB_IMMED10_BASE 0x28bc4 2066#define CB_IMMED11_BASE 0x28bc8 2067 2068/* all 12 CB blocks have these regs */ 2069#define CB_COLOR0_BASE 0x28c60 2070#define CB_COLOR0_PITCH 0x28c64 2071#define CB_COLOR0_SLICE 0x28c68 2072#define CB_COLOR0_VIEW 0x28c6c 2073#define R_028C6C_CB_COLOR0_VIEW 0x00028C6C 2074#define S_028C6C_SLICE_START(x) (((x) & 0x7FF) << 0) 2075#define G_028C6C_SLICE_START(x) (((x) >> 0) & 0x7FF) 2076#define C_028C6C_SLICE_START 0xFFFFF800 2077#define S_028C6C_SLICE_MAX(x) (((x) & 0x7FF) << 13) 2078#define G_028C6C_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 2079#define C_028C6C_SLICE_MAX 0xFF001FFF 2080#define R_028C70_CB_COLOR0_INFO 0x028C70 2081#define S_028C70_ENDIAN(x) (((x) & 0x3) << 0) 2082#define G_028C70_ENDIAN(x) (((x) >> 0) & 0x3) 2083#define C_028C70_ENDIAN 0xFFFFFFFC 2084#define S_028C70_FORMAT(x) (((x) & 0x3F) << 2) 2085#define G_028C70_FORMAT(x) (((x) >> 2) & 0x3F) 2086#define C_028C70_FORMAT 0xFFFFFF03 2087#define V_028C70_COLOR_INVALID 0x00000000 2088#define V_028C70_COLOR_8 0x00000001 2089#define V_028C70_COLOR_4_4 0x00000002 2090#define V_028C70_COLOR_3_3_2 0x00000003 2091#define V_028C70_COLOR_16 0x00000005 2092#define V_028C70_COLOR_16_FLOAT 0x00000006 2093#define V_028C70_COLOR_8_8 0x00000007 2094#define V_028C70_COLOR_5_6_5 0x00000008 2095#define V_028C70_COLOR_6_5_5 0x00000009 2096#define V_028C70_COLOR_1_5_5_5 0x0000000A 2097#define V_028C70_COLOR_4_4_4_4 0x0000000B 2098#define V_028C70_COLOR_5_5_5_1 0x0000000C 2099#define V_028C70_COLOR_32 0x0000000D 2100#define V_028C70_COLOR_32_FLOAT 0x0000000E 2101#define V_028C70_COLOR_16_16 0x0000000F 2102#define V_028C70_COLOR_16_16_FLOAT 0x00000010 2103#define V_028C70_COLOR_8_24 0x00000011 2104#define V_028C70_COLOR_8_24_FLOAT 0x00000012 2105#define V_028C70_COLOR_24_8 0x00000013 2106#define V_028C70_COLOR_24_8_FLOAT 0x00000014 2107#define V_028C70_COLOR_10_11_11 0x00000015 2108#define V_028C70_COLOR_10_11_11_FLOAT 0x00000016 2109#define V_028C70_COLOR_11_11_10 0x00000017 2110#define V_028C70_COLOR_11_11_10_FLOAT 0x00000018 2111#define V_028C70_COLOR_2_10_10_10 0x00000019 2112#define V_028C70_COLOR_8_8_8_8 0x0000001A 2113#define V_028C70_COLOR_10_10_10_2 0x0000001B 2114#define V_028C70_COLOR_X24_8_32_FLOAT 0x0000001C 2115#define V_028C70_COLOR_32_32 0x0000001D 2116#define V_028C70_COLOR_32_32_FLOAT 0x0000001E 2117#define V_028C70_COLOR_16_16_16_16 0x0000001F 2118#define V_028C70_COLOR_16_16_16_16_FLOAT 0x00000020 2119#define V_028C70_COLOR_32_32_32_32 0x00000022 2120#define V_028C70_COLOR_32_32_32_32_FLOAT 0x00000023 2121#define V_028C70_COLOR_32_32_32_FLOAT 0x00000030 2122#define S_028C70_ARRAY_MODE(x) (((x) & 0xF) << 8) 2123#define G_028C70_ARRAY_MODE(x) (((x) >> 8) & 0xF) 2124#define C_028C70_ARRAY_MODE 0xFFFFF0FF 2125#define V_028C70_ARRAY_LINEAR_GENERAL 0x00000000 2126#define V_028C70_ARRAY_LINEAR_ALIGNED 0x00000001 2127#define V_028C70_ARRAY_1D_TILED_THIN1 0x00000002 2128#define V_028C70_ARRAY_2D_TILED_THIN1 0x00000004 2129#define S_028C70_NUMBER_TYPE(x) (((x) & 0x7) << 12) 2130#define G_028C70_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 2131#define C_028C70_NUMBER_TYPE 0xFFFF8FFF 2132#define V_028C70_NUMBER_UNORM 0x00000000 2133#define V_028C70_NUMBER_SNORM 0x00000001 2134#define V_028C70_NUMBER_USCALED 0x00000002 2135#define V_028C70_NUMBER_SSCALED 0x00000003 2136#define V_028C70_NUMBER_UINT 0x00000004 2137#define V_028C70_NUMBER_SINT 0x00000005 2138#define V_028C70_NUMBER_SRGB 0x00000006 2139#define V_028C70_NUMBER_FLOAT 0x00000007 2140#define S_028C70_COMP_SWAP(x) (((x) & 0x3) << 15) 2141#define G_028C70_COMP_SWAP(x) (((x) >> 15) & 0x3) 2142#define C_028C70_COMP_SWAP 0xFFFE7FFF 2143#define V_028C70_SWAP_STD 0x00000000 2144#define V_028C70_SWAP_ALT 0x00000001 2145#define V_028C70_SWAP_STD_REV 0x00000002 2146#define V_028C70_SWAP_ALT_REV 0x00000003 2147#define S_028C70_FAST_CLEAR(x) (((x) & 0x1) << 17) 2148#define G_028C70_FAST_CLEAR(x) (((x) >> 17) & 0x1) 2149#define C_028C70_FAST_CLEAR 0xFFFDFFFF 2150#define S_028C70_COMPRESSION(x) (((x) & 0x3) << 18) 2151#define G_028C70_COMPRESSION(x) (((x) >> 18) & 0x3) 2152#define C_028C70_COMPRESSION 0xFFF3FFFF 2153#define S_028C70_BLEND_CLAMP(x) (((x) & 0x1) << 19) 2154#define G_028C70_BLEND_CLAMP(x) (((x) >> 19) & 0x1) 2155#define C_028C70_BLEND_CLAMP 0xFFF7FFFF 2156#define S_028C70_BLEND_BYPASS(x) (((x) & 0x1) << 20) 2157#define G_028C70_BLEND_BYPASS(x) (((x) >> 20) & 0x1) 2158#define C_028C70_BLEND_BYPASS 0xFFEFFFFF 2159#define S_028C70_SIMPLE_FLOAT(x) (((x) & 0x1) << 21) 2160#define G_028C70_SIMPLE_FLOAT(x) (((x) >> 21) & 0x1) 2161#define C_028C70_SIMPLE_FLOAT 0xFFDFFFFF 2162#define S_028C70_ROUND_MODE(x) (((x) & 0x1) << 22) 2163#define G_028C70_ROUND_MODE(x) (((x) >> 22) & 0x1) 2164#define C_028C70_ROUND_MODE 0xFFBFFFFF 2165#define S_028C70_TILE_COMPACT(x) (((x) & 0x1) << 23) 2166#define G_028C70_TILE_COMPACT(x) (((x) >> 23) & 0x1) 2167#define C_028C70_TILE_COMPACT 0xFF7FFFFF 2168#define S_028C70_SOURCE_FORMAT(x) (((x) & 0x3) << 24) 2169#define G_028C70_SOURCE_FORMAT(x) (((x) >> 24) & 0x3) 2170#define C_028C70_SOURCE_FORMAT 0xFCFFFFFF 2171#define V_028C70_EXPORT_4C_32BPC 0x0 2172#define V_028C70_EXPORT_4C_16BPC 0x1 2173#define V_028C70_EXPORT_2C_32BPC 0x2 /* Do not use */ 2174#define S_028C70_RAT(x) (((x) & 0x1) << 26) 2175#define G_028C70_RAT(x) (((x) >> 26) & 0x1) 2176#define C_028C70_RAT 0xFBFFFFFF 2177#define S_028C70_RESOURCE_TYPE(x) (((x) & 0x7) << 27) 2178#define G_028C70_RESOURCE_TYPE(x) (((x) >> 27) & 0x7) 2179#define C_028C70_RESOURCE_TYPE 0xC7FFFFFF 2180 2181#define CB_COLOR0_INFO 0x28c70 2182# define CB_FORMAT(x) ((x) << 2) 2183# define CB_ARRAY_MODE(x) ((x) << 8) 2184# define ARRAY_LINEAR_GENERAL 0 2185# define ARRAY_LINEAR_ALIGNED 1 2186# define ARRAY_1D_TILED_THIN1 2 2187# define ARRAY_2D_TILED_THIN1 4 2188# define CB_SOURCE_FORMAT(x) ((x) << 24) 2189# define CB_SF_EXPORT_FULL 0 2190# define CB_SF_EXPORT_NORM 1 2191#define R_028C74_CB_COLOR0_ATTRIB 0x028C74 2192#define S_028C74_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 4) 2193#define G_028C74_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x1) 2194#define C_028C74_NON_DISP_TILING_ORDER 0xFFFFFFEF 2195#define S_028C74_TILE_SPLIT(x) (((x) & 0xf) << 5) 2196#define G_028C74_TILE_SPLIT(x) (((x) >> 5) & 0xf) 2197#define S_028C74_NUM_BANKS(x) (((x) & 0x3) << 10) 2198#define G_028C74_NUM_BANKS(x) (((x) >> 10) & 0x3) 2199#define S_028C74_BANK_WIDTH(x) (((x) & 0x3) << 13) 2200#define G_028C74_BANK_WIDTH(x) (((x) >> 13) & 0x3) 2201#define S_028C74_BANK_HEIGHT(x) (((x) & 0x3) << 16) 2202#define G_028C74_BANK_HEIGHT(x) (((x) >> 16) & 0x3) 2203#define S_028C74_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 2204#define G_028C74_MACRO_TILE_ASPECT(x) (((x) >> 19) & 0x3) 2205#define CB_COLOR0_ATTRIB 0x28c74 2206# define CB_TILE_SPLIT(x) (((x) & 0x7) << 5) 2207# define ADDR_SURF_TILE_SPLIT_64B 0 2208# define ADDR_SURF_TILE_SPLIT_128B 1 2209# define ADDR_SURF_TILE_SPLIT_256B 2 2210# define ADDR_SURF_TILE_SPLIT_512B 3 2211# define ADDR_SURF_TILE_SPLIT_1KB 4 2212# define ADDR_SURF_TILE_SPLIT_2KB 5 2213# define ADDR_SURF_TILE_SPLIT_4KB 6 2214# define CB_NUM_BANKS(x) (((x) & 0x3) << 10) 2215# define ADDR_SURF_2_BANK 0 2216# define ADDR_SURF_4_BANK 1 2217# define ADDR_SURF_8_BANK 2 2218# define ADDR_SURF_16_BANK 3 2219# define CB_BANK_WIDTH(x) (((x) & 0x3) << 13) 2220# define ADDR_SURF_BANK_WIDTH_1 0 2221# define ADDR_SURF_BANK_WIDTH_2 1 2222# define ADDR_SURF_BANK_WIDTH_4 2 2223# define ADDR_SURF_BANK_WIDTH_8 3 2224# define CB_BANK_HEIGHT(x) (((x) & 0x3) << 16) 2225# define ADDR_SURF_BANK_HEIGHT_1 0 2226# define ADDR_SURF_BANK_HEIGHT_2 1 2227# define ADDR_SURF_BANK_HEIGHT_4 2 2228# define ADDR_SURF_BANK_HEIGHT_8 3 2229# define CB_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 19) 2230#define CB_COLOR0_DIM 0x28c78 2231/* only CB0-7 blocks have these regs */ 2232#define CB_COLOR0_CMASK 0x28c7c 2233#define CB_COLOR0_CMASK_SLICE 0x28c80 2234#define CB_COLOR0_FMASK 0x28c84 2235#define CB_COLOR0_FMASK_SLICE 0x28c88 2236#define CB_COLOR0_CLEAR_WORD0 0x28c8c 2237#define CB_COLOR0_CLEAR_WORD1 0x28c90 2238#define CB_COLOR0_CLEAR_WORD2 0x28c94 2239#define CB_COLOR0_CLEAR_WORD3 0x28c98 2240 2241#define CB_COLOR1_BASE 0x28c9c 2242#define CB_COLOR2_BASE 0x28cd8 2243#define CB_COLOR3_BASE 0x28d14 2244#define CB_COLOR4_BASE 0x28d50 2245#define CB_COLOR5_BASE 0x28d8c 2246#define CB_COLOR6_BASE 0x28dc8 2247#define CB_COLOR7_BASE 0x28e04 2248#define CB_COLOR8_BASE 0x28e40 2249#define CB_COLOR9_BASE 0x28e5c 2250#define CB_COLOR10_BASE 0x28e78 2251#define CB_COLOR11_BASE 0x28e94 2252 2253#define CB_COLOR1_PITCH 0x28ca0 2254#define CB_COLOR2_PITCH 0x28cdc 2255#define CB_COLOR3_PITCH 0x28d18 2256#define CB_COLOR4_PITCH 0x28d54 2257#define CB_COLOR5_PITCH 0x28d90 2258#define CB_COLOR6_PITCH 0x28dcc 2259#define CB_COLOR7_PITCH 0x28e08 2260#define CB_COLOR8_PITCH 0x28e44 2261#define CB_COLOR9_PITCH 0x28e60 2262#define CB_COLOR10_PITCH 0x28e7c 2263#define CB_COLOR11_PITCH 0x28e98 2264 2265#define CB_COLOR1_SLICE 0x28ca4 2266#define CB_COLOR2_SLICE 0x28ce0 2267#define CB_COLOR3_SLICE 0x28d1c 2268#define CB_COLOR4_SLICE 0x28d58 2269#define CB_COLOR5_SLICE 0x28d94 2270#define CB_COLOR6_SLICE 0x28dd0 2271#define CB_COLOR7_SLICE 0x28e0c 2272#define CB_COLOR8_SLICE 0x28e48 2273#define CB_COLOR9_SLICE 0x28e64 2274#define CB_COLOR10_SLICE 0x28e80 2275#define CB_COLOR11_SLICE 0x28e9c 2276 2277#define CB_COLOR1_VIEW 0x28ca8 2278#define CB_COLOR2_VIEW 0x28ce4 2279#define CB_COLOR3_VIEW 0x28d20 2280#define CB_COLOR4_VIEW 0x28d5c 2281#define CB_COLOR5_VIEW 0x28d98 2282#define CB_COLOR6_VIEW 0x28dd4 2283#define CB_COLOR7_VIEW 0x28e10 2284#define CB_COLOR8_VIEW 0x28e4c 2285#define CB_COLOR9_VIEW 0x28e68 2286#define CB_COLOR10_VIEW 0x28e84 2287#define CB_COLOR11_VIEW 0x28ea0 2288 2289#define CB_COLOR1_INFO 0x28cac 2290#define CB_COLOR2_INFO 0x28ce8 2291#define CB_COLOR3_INFO 0x28d24 2292#define CB_COLOR4_INFO 0x28d60 2293#define CB_COLOR5_INFO 0x28d9c 2294#define CB_COLOR6_INFO 0x28dd8 2295#define CB_COLOR7_INFO 0x28e14 2296#define CB_COLOR8_INFO 0x28e50 2297#define CB_COLOR9_INFO 0x28e6c 2298#define CB_COLOR10_INFO 0x28e88 2299#define CB_COLOR11_INFO 0x28ea4 2300 2301#define CB_COLOR1_ATTRIB 0x28cb0 2302#define CB_COLOR2_ATTRIB 0x28cec 2303#define CB_COLOR3_ATTRIB 0x28d28 2304#define CB_COLOR4_ATTRIB 0x28d64 2305#define CB_COLOR5_ATTRIB 0x28da0 2306#define CB_COLOR6_ATTRIB 0x28ddc 2307#define CB_COLOR7_ATTRIB 0x28e18 2308#define CB_COLOR8_ATTRIB 0x28e54 2309#define CB_COLOR9_ATTRIB 0x28e70 2310#define CB_COLOR10_ATTRIB 0x28e8c 2311#define CB_COLOR11_ATTRIB 0x28ea8 2312 2313#define CB_COLOR1_DIM 0x28cb4 2314#define CB_COLOR2_DIM 0x28cf0 2315#define CB_COLOR3_DIM 0x28d2c 2316#define CB_COLOR4_DIM 0x28d68 2317#define CB_COLOR5_DIM 0x28da4 2318#define CB_COLOR6_DIM 0x28de0 2319#define CB_COLOR7_DIM 0x28e1c 2320#define CB_COLOR8_DIM 0x28e58 2321#define CB_COLOR9_DIM 0x28e74 2322#define CB_COLOR10_DIM 0x28e90 2323#define CB_COLOR11_DIM 0x28eac 2324 2325#define CB_COLOR1_CMASK 0x28cb8 2326#define CB_COLOR2_CMASK 0x28cf4 2327#define CB_COLOR3_CMASK 0x28d30 2328#define CB_COLOR4_CMASK 0x28d6c 2329#define CB_COLOR5_CMASK 0x28da8 2330#define CB_COLOR6_CMASK 0x28de4 2331#define CB_COLOR7_CMASK 0x28e20 2332 2333#define CB_COLOR1_CMASK_SLICE 0x28cbc 2334#define CB_COLOR2_CMASK_SLICE 0x28cf8 2335#define CB_COLOR3_CMASK_SLICE 0x28d34 2336#define CB_COLOR4_CMASK_SLICE 0x28d70 2337#define CB_COLOR5_CMASK_SLICE 0x28dac 2338#define CB_COLOR6_CMASK_SLICE 0x28de8 2339#define CB_COLOR7_CMASK_SLICE 0x28e24 2340 2341#define CB_COLOR1_FMASK 0x28cc0 2342#define CB_COLOR2_FMASK 0x28cfc 2343#define CB_COLOR3_FMASK 0x28d38 2344#define CB_COLOR4_FMASK 0x28d74 2345#define CB_COLOR5_FMASK 0x28db0 2346#define CB_COLOR6_FMASK 0x28dec 2347#define CB_COLOR7_FMASK 0x28e28 2348 2349#define CB_COLOR1_FMASK_SLICE 0x28cc4 2350#define CB_COLOR2_FMASK_SLICE 0x28d00 2351#define CB_COLOR3_FMASK_SLICE 0x28d3c 2352#define CB_COLOR4_FMASK_SLICE 0x28d78 2353#define CB_COLOR5_FMASK_SLICE 0x28db4 2354#define CB_COLOR6_FMASK_SLICE 0x28df0 2355#define CB_COLOR7_FMASK_SLICE 0x28e2c 2356 2357#define CB_COLOR1_CLEAR_WORD0 0x28cc8 2358#define CB_COLOR2_CLEAR_WORD0 0x28d04 2359#define CB_COLOR3_CLEAR_WORD0 0x28d40 2360#define CB_COLOR4_CLEAR_WORD0 0x28d7c 2361#define CB_COLOR5_CLEAR_WORD0 0x28db8 2362#define CB_COLOR6_CLEAR_WORD0 0x28df4 2363#define CB_COLOR7_CLEAR_WORD0 0x28e30 2364 2365#define CB_COLOR1_CLEAR_WORD1 0x28ccc 2366#define CB_COLOR2_CLEAR_WORD1 0x28d08 2367#define CB_COLOR3_CLEAR_WORD1 0x28d44 2368#define CB_COLOR4_CLEAR_WORD1 0x28d80 2369#define CB_COLOR5_CLEAR_WORD1 0x28dbc 2370#define CB_COLOR6_CLEAR_WORD1 0x28df8 2371#define CB_COLOR7_CLEAR_WORD1 0x28e34 2372 2373#define CB_COLOR1_CLEAR_WORD2 0x28cd0 2374#define CB_COLOR2_CLEAR_WORD2 0x28d0c 2375#define CB_COLOR3_CLEAR_WORD2 0x28d48 2376#define CB_COLOR4_CLEAR_WORD2 0x28d84 2377#define CB_COLOR5_CLEAR_WORD2 0x28dc0 2378#define CB_COLOR6_CLEAR_WORD2 0x28dfc 2379#define CB_COLOR7_CLEAR_WORD2 0x28e38 2380 2381#define CB_COLOR1_CLEAR_WORD3 0x28cd4 2382#define CB_COLOR2_CLEAR_WORD3 0x28d10 2383#define CB_COLOR3_CLEAR_WORD3 0x28d4c 2384#define CB_COLOR4_CLEAR_WORD3 0x28d88 2385#define CB_COLOR5_CLEAR_WORD3 0x28dc4 2386#define CB_COLOR6_CLEAR_WORD3 0x28e00 2387#define CB_COLOR7_CLEAR_WORD3 0x28e3c 2388 2389#define SQ_TEX_RESOURCE_WORD0_0 0x30000 2390# define TEX_DIM(x) ((x) << 0) 2391# define SQ_TEX_DIM_1D 0 2392# define SQ_TEX_DIM_2D 1 2393# define SQ_TEX_DIM_3D 2 2394# define SQ_TEX_DIM_CUBEMAP 3 2395# define SQ_TEX_DIM_1D_ARRAY 4 2396# define SQ_TEX_DIM_2D_ARRAY 5 2397# define SQ_TEX_DIM_2D_MSAA 6 2398# define SQ_TEX_DIM_2D_ARRAY_MSAA 7 2399#define SQ_TEX_RESOURCE_WORD1_0 0x30004 2400# define TEX_ARRAY_MODE(x) ((x) << 28) 2401#define SQ_TEX_RESOURCE_WORD2_0 0x30008 2402#define SQ_TEX_RESOURCE_WORD3_0 0x3000C 2403#define SQ_TEX_RESOURCE_WORD4_0 0x30010 2404# define TEX_DST_SEL_X(x) ((x) << 16) 2405# define TEX_DST_SEL_Y(x) ((x) << 19) 2406# define TEX_DST_SEL_Z(x) ((x) << 22) 2407# define TEX_DST_SEL_W(x) ((x) << 25) 2408# define SQ_SEL_X 0 2409# define SQ_SEL_Y 1 2410# define SQ_SEL_Z 2 2411# define SQ_SEL_W 3 2412# define SQ_SEL_0 4 2413# define SQ_SEL_1 5 2414#define SQ_TEX_RESOURCE_WORD5_0 0x30014 2415#define SQ_TEX_RESOURCE_WORD6_0 0x30018 2416# define TEX_TILE_SPLIT(x) (((x) & 0x7) << 29) 2417#define SQ_TEX_RESOURCE_WORD7_0 0x3001c 2418# define MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 2419# define TEX_BANK_WIDTH(x) (((x) & 0x3) << 8) 2420# define TEX_BANK_HEIGHT(x) (((x) & 0x3) << 10) 2421# define TEX_NUM_BANKS(x) (((x) & 0x3) << 16) 2422#define R_030000_SQ_TEX_RESOURCE_WORD0_0 0x030000 2423#define S_030000_DIM(x) (((x) & 0x7) << 0) 2424#define G_030000_DIM(x) (((x) >> 0) & 0x7) 2425#define C_030000_DIM 0xFFFFFFF8 2426#define V_030000_SQ_TEX_DIM_1D 0x00000000 2427#define V_030000_SQ_TEX_DIM_2D 0x00000001 2428#define V_030000_SQ_TEX_DIM_3D 0x00000002 2429#define V_030000_SQ_TEX_DIM_CUBEMAP 0x00000003 2430#define V_030000_SQ_TEX_DIM_1D_ARRAY 0x00000004 2431#define V_030000_SQ_TEX_DIM_2D_ARRAY 0x00000005 2432#define V_030000_SQ_TEX_DIM_2D_MSAA 0x00000006 2433#define V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 2434#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5) 2435#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1) 2436#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF 2437#define S_030000_PITCH(x) (((x) & 0xFFF) << 6) 2438#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF) 2439#define C_030000_PITCH 0xFFFC003F 2440#define S_030000_TEX_WIDTH(x) (((x) & 0x3FFF) << 18) 2441#define G_030000_TEX_WIDTH(x) (((x) >> 18) & 0x3FFF) 2442#define C_030000_TEX_WIDTH 0x0003FFFF 2443#define R_030004_SQ_TEX_RESOURCE_WORD1_0 0x030004 2444#define S_030004_TEX_HEIGHT(x) (((x) & 0x3FFF) << 0) 2445#define G_030004_TEX_HEIGHT(x) (((x) >> 0) & 0x3FFF) 2446#define C_030004_TEX_HEIGHT 0xFFFFC000 2447#define S_030004_TEX_DEPTH(x) (((x) & 0x1FFF) << 14) 2448#define G_030004_TEX_DEPTH(x) (((x) >> 14) & 0x1FFF) 2449#define C_030004_TEX_DEPTH 0xF8003FFF 2450#define S_030004_ARRAY_MODE(x) (((x) & 0xF) << 28) 2451#define G_030004_ARRAY_MODE(x) (((x) >> 28) & 0xF) 2452#define C_030004_ARRAY_MODE 0x0FFFFFFF 2453#define R_030008_SQ_TEX_RESOURCE_WORD2_0 0x030008 2454#define S_030008_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 2455#define G_030008_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 2456#define C_030008_BASE_ADDRESS 0x00000000 2457#define R_03000C_SQ_TEX_RESOURCE_WORD3_0 0x03000C 2458#define S_03000C_MIP_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 2459#define G_03000C_MIP_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 2460#define C_03000C_MIP_ADDRESS 0x00000000 2461#define R_030010_SQ_TEX_RESOURCE_WORD4_0 0x030010 2462#define S_030010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 2463#define G_030010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 2464#define C_030010_FORMAT_COMP_X 0xFFFFFFFC 2465#define V_030010_SQ_FORMAT_COMP_UNSIGNED 0x00000000 2466#define V_030010_SQ_FORMAT_COMP_SIGNED 0x00000001 2467#define V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED 0x00000002 2468#define S_030010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 2469#define G_030010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 2470#define C_030010_FORMAT_COMP_Y 0xFFFFFFF3 2471#define S_030010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 2472#define G_030010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 2473#define C_030010_FORMAT_COMP_Z 0xFFFFFFCF 2474#define S_030010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 2475#define G_030010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 2476#define C_030010_FORMAT_COMP_W 0xFFFFFF3F 2477#define S_030010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 2478#define G_030010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 2479#define C_030010_NUM_FORMAT_ALL 0xFFFFFCFF 2480#define V_030010_SQ_NUM_FORMAT_NORM 0x00000000 2481#define V_030010_SQ_NUM_FORMAT_INT 0x00000001 2482#define V_030010_SQ_NUM_FORMAT_SCALED 0x00000002 2483#define S_030010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 2484#define G_030010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 2485#define C_030010_SRF_MODE_ALL 0xFFFFFBFF 2486#define V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE 0x00000000 2487#define V_030010_SRF_MODE_NO_ZERO 0x00000001 2488#define S_030010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 2489#define G_030010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 2490#define C_030010_FORCE_DEGAMMA 0xFFFFF7FF 2491#define S_030010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 2492#define G_030010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 2493#define C_030010_ENDIAN_SWAP 0xFFFFCFFF 2494#define S_030010_DST_SEL_X(x) (((x) & 0x7) << 16) 2495#define G_030010_DST_SEL_X(x) (((x) >> 16) & 0x7) 2496#define C_030010_DST_SEL_X 0xFFF8FFFF 2497#define V_030010_SQ_SEL_X 0x00000000 2498#define V_030010_SQ_SEL_Y 0x00000001 2499#define V_030010_SQ_SEL_Z 0x00000002 2500#define V_030010_SQ_SEL_W 0x00000003 2501#define V_030010_SQ_SEL_0 0x00000004 2502#define V_030010_SQ_SEL_1 0x00000005 2503#define S_030010_DST_SEL_Y(x) (((x) & 0x7) << 19) 2504#define G_030010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 2505#define C_030010_DST_SEL_Y 0xFFC7FFFF 2506#define S_030010_DST_SEL_Z(x) (((x) & 0x7) << 22) 2507#define G_030010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 2508#define C_030010_DST_SEL_Z 0xFE3FFFFF 2509#define S_030010_DST_SEL_W(x) (((x) & 0x7) << 25) 2510#define G_030010_DST_SEL_W(x) (((x) >> 25) & 0x7) 2511#define C_030010_DST_SEL_W 0xF1FFFFFF 2512#define S_030010_BASE_LEVEL(x) (((x) & 0xF) << 28) 2513#define G_030010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 2514#define C_030010_BASE_LEVEL 0x0FFFFFFF 2515#define R_030014_SQ_TEX_RESOURCE_WORD5_0 0x030014 2516#define S_030014_LAST_LEVEL(x) (((x) & 0xF) << 0) 2517#define G_030014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 2518#define C_030014_LAST_LEVEL 0xFFFFFFF0 2519#define S_030014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 2520#define G_030014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 2521#define C_030014_BASE_ARRAY 0xFFFE000F 2522#define S_030014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 2523#define G_030014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 2524#define C_030014_LAST_ARRAY 0xC001FFFF 2525#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018 2526#define S_030018_MAX_ANISO(x) (((x) & 0x7) << 0) 2527#define G_030018_MAX_ANISO(x) (((x) >> 0) & 0x7) 2528#define C_030018_MAX_ANISO 0xFFFFFFF8 2529#define S_030018_PERF_MODULATION(x) (((x) & 0x7) << 3) 2530#define G_030018_PERF_MODULATION(x) (((x) >> 3) & 0x7) 2531#define C_030018_PERF_MODULATION 0xFFFFFFC7 2532#define S_030018_INTERLACED(x) (((x) & 0x1) << 6) 2533#define G_030018_INTERLACED(x) (((x) >> 6) & 0x1) 2534#define C_030018_INTERLACED 0xFFFFFFBF 2535#define S_030018_TILE_SPLIT(x) (((x) & 0x7) << 29) 2536#define G_030018_TILE_SPLIT(x) (((x) >> 29) & 0x7) 2537#define R_03001C_SQ_TEX_RESOURCE_WORD7_0 0x03001C 2538#define S_03001C_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 6) 2539#define G_03001C_MACRO_TILE_ASPECT(x) (((x) >> 6) & 0x3) 2540#define S_03001C_BANK_WIDTH(x) (((x) & 0x3) << 8) 2541#define G_03001C_BANK_WIDTH(x) (((x) >> 8) & 0x3) 2542#define S_03001C_BANK_HEIGHT(x) (((x) & 0x3) << 10) 2543#define G_03001C_BANK_HEIGHT(x) (((x) >> 10) & 0x3) 2544#define S_03001C_NUM_BANKS(x) (((x) & 0x3) << 16) 2545#define G_03001C_NUM_BANKS(x) (((x) >> 16) & 0x3) 2546#define S_03001C_TYPE(x) (((x) & 0x3) << 30) 2547#define G_03001C_TYPE(x) (((x) >> 30) & 0x3) 2548#define C_03001C_TYPE 0x3FFFFFFF 2549#define V_03001C_SQ_TEX_VTX_INVALID_TEXTURE 0x00000000 2550#define V_03001C_SQ_TEX_VTX_INVALID_BUFFER 0x00000001 2551#define V_03001C_SQ_TEX_VTX_VALID_TEXTURE 0x00000002 2552#define V_03001C_SQ_TEX_VTX_VALID_BUFFER 0x00000003 2553#define S_03001C_DATA_FORMAT(x) (((x) & 0x3F) << 0) 2554#define G_03001C_DATA_FORMAT(x) (((x) >> 0) & 0x3F) 2555#define C_03001C_DATA_FORMAT 0xFFFFFFC0 2556 2557#define SQ_VTX_CONSTANT_WORD0_0 0x30000 2558#define SQ_VTX_CONSTANT_WORD1_0 0x30004 2559#define SQ_VTX_CONSTANT_WORD2_0 0x30008 2560# define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 2561# define SQ_VTXC_STRIDE(x) ((x) << 8) 2562# define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 2563# define SQ_ENDIAN_NONE 0 2564# define SQ_ENDIAN_8IN16 1 2565# define SQ_ENDIAN_8IN32 2 2566#define SQ_VTX_CONSTANT_WORD3_0 0x3000C 2567# define SQ_VTCX_SEL_X(x) ((x) << 3) 2568# define SQ_VTCX_SEL_Y(x) ((x) << 6) 2569# define SQ_VTCX_SEL_Z(x) ((x) << 9) 2570# define SQ_VTCX_SEL_W(x) ((x) << 12) 2571#define SQ_VTX_CONSTANT_WORD4_0 0x30010 2572#define SQ_VTX_CONSTANT_WORD5_0 0x30014 2573#define SQ_VTX_CONSTANT_WORD6_0 0x30018 2574#define SQ_VTX_CONSTANT_WORD7_0 0x3001c 2575 2576#define TD_PS_BORDER_COLOR_INDEX 0xA400 2577#define TD_PS_BORDER_COLOR_RED 0xA404 2578#define TD_PS_BORDER_COLOR_GREEN 0xA408 2579#define TD_PS_BORDER_COLOR_BLUE 0xA40C 2580#define TD_PS_BORDER_COLOR_ALPHA 0xA410 2581#define TD_VS_BORDER_COLOR_INDEX 0xA414 2582#define TD_VS_BORDER_COLOR_RED 0xA418 2583#define TD_VS_BORDER_COLOR_GREEN 0xA41C 2584#define TD_VS_BORDER_COLOR_BLUE 0xA420 2585#define TD_VS_BORDER_COLOR_ALPHA 0xA424 2586#define TD_GS_BORDER_COLOR_INDEX 0xA428 2587#define TD_GS_BORDER_COLOR_RED 0xA42C 2588#define TD_GS_BORDER_COLOR_GREEN 0xA430 2589#define TD_GS_BORDER_COLOR_BLUE 0xA434 2590#define TD_GS_BORDER_COLOR_ALPHA 0xA438 2591#define TD_HS_BORDER_COLOR_INDEX 0xA43C 2592#define TD_HS_BORDER_COLOR_RED 0xA440 2593#define TD_HS_BORDER_COLOR_GREEN 0xA444 2594#define TD_HS_BORDER_COLOR_BLUE 0xA448 2595#define TD_HS_BORDER_COLOR_ALPHA 0xA44C 2596#define TD_LS_BORDER_COLOR_INDEX 0xA450 2597#define TD_LS_BORDER_COLOR_RED 0xA454 2598#define TD_LS_BORDER_COLOR_GREEN 0xA458 2599#define TD_LS_BORDER_COLOR_BLUE 0xA45C 2600#define TD_LS_BORDER_COLOR_ALPHA 0xA460 2601#define TD_CS_BORDER_COLOR_INDEX 0xA464 2602#define TD_CS_BORDER_COLOR_RED 0xA468 2603#define TD_CS_BORDER_COLOR_GREEN 0xA46C 2604#define TD_CS_BORDER_COLOR_BLUE 0xA470 2605#define TD_CS_BORDER_COLOR_ALPHA 0xA474 2606 2607/* cayman 3D regs */ 2608#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 2609#define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 2610#define CAYMAN_DB_EQAA 0x28804 2611#define CAYMAN_DB_DEPTH_INFO 0x2803C 2612#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 2613#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0 2614#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7 2615#define CAYMAN_SX_SCATTER_EXPORT_BASE 0x28358 2616/* cayman packet3 addition */ 2617#define CAYMAN_PACKET3_DEALLOC_STATE 0x14 2618 2619/* DMA regs common on r6xx/r7xx/evergreen/ni */ 2620#define DMA_RB_CNTL 0xd000 2621# define DMA_RB_ENABLE (1 << 0) 2622# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 2623# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 2624# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 2625# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 2626# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 2627#define DMA_STATUS_REG 0xd034 2628# define DMA_IDLE (1 << 0) 2629 2630#endif 2631