1164898Sdavidxu/* $NetBSD: rv740d.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2164898Sdavidxu 3164898Sdavidxu/* 4164898Sdavidxu * Copyright 2011 Advanced Micro Devices, Inc. 5164898Sdavidxu * 6164898Sdavidxu * Permission is hereby granted, free of charge, to any person obtaining a 7164898Sdavidxu * copy of this software and associated documentation files (the "Software"), 8164898Sdavidxu * to deal in the Software without restriction, including without limitation 9164898Sdavidxu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10164898Sdavidxu * and/or sell copies of the Software, and to permit persons to whom the 11164898Sdavidxu * Software is furnished to do so, subject to the following conditions: 12164898Sdavidxu * 13164898Sdavidxu * The above copyright notice and this permission notice shall be included in 14164898Sdavidxu * all copies or substantial portions of the Software. 15164898Sdavidxu * 16164898Sdavidxu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17164898Sdavidxu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18164898Sdavidxu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19164898Sdavidxu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20164898Sdavidxu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21164898Sdavidxu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22164898Sdavidxu * OTHER DEALINGS IN THE SOFTWARE. 23164898Sdavidxu * 24164898Sdavidxu */ 25164898Sdavidxu#ifndef RV740_H 26164898Sdavidxu#define RV740_H 27164898Sdavidxu 28164898Sdavidxu#define CG_SPLL_FUNC_CNTL 0x600 29164898Sdavidxu#define SPLL_RESET (1 << 0) 30164898Sdavidxu#define SPLL_SLEEP (1 << 1) 31253384Skevlo#define SPLL_BYPASS_EN (1 << 3) 32164898Sdavidxu#define SPLL_REF_DIV(x) ((x) << 4) 33164898Sdavidxu#define SPLL_REF_DIV_MASK (0x3f << 4) 34164898Sdavidxu#define SPLL_PDIV_A(x) ((x) << 20) 35164928Sdavidxu#define SPLL_PDIV_A_MASK (0x7f << 20) 36164928Sdavidxu#define CG_SPLL_FUNC_CNTL_2 0x604 37164898Sdavidxu#define SCLK_MUX_SEL(x) ((x) << 0) 38164898Sdavidxu#define SCLK_MUX_SEL_MASK (0x1ff << 0) 39164898Sdavidxu#define CG_SPLL_FUNC_CNTL_3 0x608 40164898Sdavidxu#define SPLL_FB_DIV(x) ((x) << 0) 41164898Sdavidxu#define SPLL_FB_DIV_MASK (0x3ffffff << 0) 42164898Sdavidxu#define SPLL_DITHEN (1 << 28) 43164898Sdavidxu 44164898Sdavidxu#define MPLL_CNTL_MODE 0x61c 45164898Sdavidxu#define SS_SSEN (1 << 24) 46164898Sdavidxu 47164898Sdavidxu#define MPLL_AD_FUNC_CNTL 0x624 48164898Sdavidxu#define CLKF(x) ((x) << 0) 49164898Sdavidxu#define CLKF_MASK (0x7f << 0) 50164898Sdavidxu#define CLKR(x) ((x) << 7) 51164898Sdavidxu#define CLKR_MASK (0x1f << 7) 52164898Sdavidxu#define CLKFRAC(x) ((x) << 12) 53164898Sdavidxu#define CLKFRAC_MASK (0x1f << 12) 54164898Sdavidxu#define YCLK_POST_DIV(x) ((x) << 17) 55164898Sdavidxu#define YCLK_POST_DIV_MASK (3 << 17) 56164898Sdavidxu#define IBIAS(x) ((x) << 20) 57164898Sdavidxu#define IBIAS_MASK (0x3ff << 20) 58164898Sdavidxu#define RESET (1 << 30) 59164898Sdavidxu#define PDNB (1 << 31) 60164898Sdavidxu#define MPLL_AD_FUNC_CNTL_2 0x628 61164898Sdavidxu#define BYPASS (1 << 19) 62164898Sdavidxu#define BIAS_GEN_PDNB (1 << 24) 63164898Sdavidxu#define RESET_EN (1 << 25) 64164898Sdavidxu#define VCO_MODE (1 << 29) 65164898Sdavidxu#define MPLL_DQ_FUNC_CNTL 0x62c 66164898Sdavidxu#define MPLL_DQ_FUNC_CNTL_2 0x630 67164898Sdavidxu 68164898Sdavidxu#define MCLK_PWRMGT_CNTL 0x648 69164898Sdavidxu#define DLL_SPEED(x) ((x) << 0) 70164898Sdavidxu#define DLL_SPEED_MASK (0x1f << 0) 71164898Sdavidxu# define MPLL_PWRMGT_OFF (1 << 5) 72164898Sdavidxu# define DLL_READY (1 << 6) 73164898Sdavidxu# define MC_INT_CNTL (1 << 7) 74164898Sdavidxu# define MRDCKA0_SLEEP (1 << 8) 75164898Sdavidxu# define MRDCKA1_SLEEP (1 << 9) 76164898Sdavidxu# define MRDCKB0_SLEEP (1 << 10) 77164899Sdavidxu# define MRDCKB1_SLEEP (1 << 11) 78164898Sdavidxu# define MRDCKC0_SLEEP (1 << 12) 79164898Sdavidxu# define MRDCKC1_SLEEP (1 << 13) 80164898Sdavidxu# define MRDCKD0_SLEEP (1 << 14) 81164898Sdavidxu# define MRDCKD1_SLEEP (1 << 15) 82164898Sdavidxu# define MRDCKA0_RESET (1 << 16) 83164898Sdavidxu# define MRDCKA1_RESET (1 << 17) 84164898Sdavidxu# define MRDCKB0_RESET (1 << 18) 85164898Sdavidxu# define MRDCKB1_RESET (1 << 19) 86164898Sdavidxu# define MRDCKC0_RESET (1 << 20) 87# define MRDCKC1_RESET (1 << 21) 88# define MRDCKD0_RESET (1 << 22) 89# define MRDCKD1_RESET (1 << 23) 90# define DLL_READY_READ (1 << 24) 91# define USE_DISPLAY_GAP (1 << 25) 92# define USE_DISPLAY_URGENT_NORMAL (1 << 26) 93# define MPLL_TURNOFF_D2 (1 << 28) 94#define DLL_CNTL 0x64c 95# define MRDCKA0_BYPASS (1 << 24) 96# define MRDCKA1_BYPASS (1 << 25) 97# define MRDCKB0_BYPASS (1 << 26) 98# define MRDCKB1_BYPASS (1 << 27) 99# define MRDCKC0_BYPASS (1 << 28) 100# define MRDCKC1_BYPASS (1 << 29) 101# define MRDCKD0_BYPASS (1 << 30) 102# define MRDCKD1_BYPASS (1 << 31) 103 104#define CG_SPLL_SPREAD_SPECTRUM 0x790 105#define SSEN (1 << 0) 106#define CLK_S(x) ((x) << 4) 107#define CLK_S_MASK (0xfff << 4) 108#define CG_SPLL_SPREAD_SPECTRUM_2 0x794 109#define CLK_V(x) ((x) << 0) 110#define CLK_V_MASK (0x3ffffff << 0) 111 112#define MPLL_SS1 0x85c 113#define CLKV(x) ((x) << 0) 114#define CLKV_MASK (0x3ffffff << 0) 115#define MPLL_SS2 0x860 116#define CLKS(x) ((x) << 0) 117#define CLKS_MASK (0xfff << 0) 118 119#endif 120