1/* $NetBSD: rv6xxd.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2 3/* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25#ifndef RV6XXD_H 26#define RV6XXD_H 27 28/* RV6xx power management */ 29#define SPLL_CNTL_MODE 0x60c 30# define SPLL_DIV_SYNC (1 << 5) 31 32#define GENERAL_PWRMGT 0x618 33# define GLOBAL_PWRMGT_EN (1 << 0) 34# define STATIC_PM_EN (1 << 1) 35# define MOBILE_SU (1 << 2) 36# define THERMAL_PROTECTION_DIS (1 << 3) 37# define THERMAL_PROTECTION_TYPE (1 << 4) 38# define ENABLE_GEN2PCIE (1 << 5) 39# define SW_GPIO_INDEX(x) ((x) << 6) 40# define SW_GPIO_INDEX_MASK (3 << 6) 41# define LOW_VOLT_D2_ACPI (1 << 8) 42# define LOW_VOLT_D3_ACPI (1 << 9) 43# define VOLT_PWRMGT_EN (1 << 10) 44# define BACKBIAS_PAD_EN (1 << 16) 45# define BACKBIAS_VALUE (1 << 17) 46# define BACKBIAS_DPM_CNTL (1 << 18) 47# define DYN_SPREAD_SPECTRUM_EN (1 << 21) 48 49#define MCLK_PWRMGT_CNTL 0x624 50# define MPLL_PWRMGT_OFF (1 << 0) 51# define YCLK_TURNOFF (1 << 1) 52# define MPLL_TURNOFF (1 << 2) 53# define SU_MCLK_USE_BCLK (1 << 3) 54# define DLL_READY (1 << 4) 55# define MC_BUSY (1 << 5) 56# define MC_INT_CNTL (1 << 7) 57# define MRDCKA_SLEEP (1 << 8) 58# define MRDCKB_SLEEP (1 << 9) 59# define MRDCKC_SLEEP (1 << 10) 60# define MRDCKD_SLEEP (1 << 11) 61# define MRDCKE_SLEEP (1 << 12) 62# define MRDCKF_SLEEP (1 << 13) 63# define MRDCKG_SLEEP (1 << 14) 64# define MRDCKH_SLEEP (1 << 15) 65# define MRDCKA_RESET (1 << 16) 66# define MRDCKB_RESET (1 << 17) 67# define MRDCKC_RESET (1 << 18) 68# define MRDCKD_RESET (1 << 19) 69# define MRDCKE_RESET (1 << 20) 70# define MRDCKF_RESET (1 << 21) 71# define MRDCKG_RESET (1 << 22) 72# define MRDCKH_RESET (1 << 23) 73# define DLL_READY_READ (1 << 24) 74# define USE_DISPLAY_GAP (1 << 25) 75# define USE_DISPLAY_URGENT_NORMAL (1 << 26) 76# define USE_DISPLAY_GAP_CTXSW (1 << 27) 77# define MPLL_TURNOFF_D2 (1 << 28) 78# define USE_DISPLAY_URGENT_CTXSW (1 << 29) 79 80#define MPLL_FREQ_LEVEL_0 0x6e8 81# define LEVEL0_MPLL_POST_DIV(x) ((x) << 0) 82# define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0) 83# define LEVEL0_MPLL_FB_DIV(x) ((x) << 8) 84# define LEVEL0_MPLL_FB_DIV_MASK (0xfff << 8) 85# define LEVEL0_MPLL_REF_DIV(x) ((x) << 20) 86# define LEVEL0_MPLL_REF_DIV_MASK (0x3f << 20) 87# define LEVEL0_MPLL_DIV_EN (1 << 28) 88# define LEVEL0_DLL_BYPASS (1 << 29) 89# define LEVEL0_DLL_RESET (1 << 30) 90 91#define VID_RT 0x6f8 92# define VID_CRT(x) ((x) << 0) 93# define VID_CRT_MASK (0x1fff << 0) 94# define VID_CRTU(x) ((x) << 13) 95# define VID_CRTU_MASK (7 << 13) 96# define SSTU(x) ((x) << 16) 97# define SSTU_MASK (7 << 16) 98# define VID_SWT(x) ((x) << 19) 99# define VID_SWT_MASK (0x1f << 19) 100# define BRT(x) ((x) << 24) 101# define BRT_MASK (0xff << 24) 102 103#define TARGET_AND_CURRENT_PROFILE_INDEX 0x70c 104# define TARGET_PROFILE_INDEX_MASK (3 << 0) 105# define TARGET_PROFILE_INDEX_SHIFT 0 106# define CURRENT_PROFILE_INDEX_MASK (3 << 2) 107# define CURRENT_PROFILE_INDEX_SHIFT 2 108# define DYN_PWR_ENTER_INDEX(x) ((x) << 4) 109# define DYN_PWR_ENTER_INDEX_MASK (3 << 4) 110# define DYN_PWR_ENTER_INDEX_SHIFT 4 111# define CURR_MCLK_INDEX_MASK (3 << 6) 112# define CURR_MCLK_INDEX_SHIFT 6 113# define CURR_SCLK_INDEX_MASK (0x1f << 8) 114# define CURR_SCLK_INDEX_SHIFT 8 115# define CURR_VID_INDEX_MASK (3 << 13) 116# define CURR_VID_INDEX_SHIFT 13 117 118#define VID_UPPER_GPIO_CNTL 0x740 119# define CTXSW_UPPER_GPIO_VALUES(x) ((x) << 0) 120# define CTXSW_UPPER_GPIO_VALUES_MASK (7 << 0) 121# define HIGH_UPPER_GPIO_VALUES(x) ((x) << 3) 122# define HIGH_UPPER_GPIO_VALUES_MASK (7 << 3) 123# define MEDIUM_UPPER_GPIO_VALUES(x) ((x) << 6) 124# define MEDIUM_UPPER_GPIO_VALUES_MASK (7 << 6) 125# define LOW_UPPER_GPIO_VALUES(x) ((x) << 9) 126# define LOW_UPPER_GPIO_VALUES_MASK (7 << 9) 127# define CTXSW_BACKBIAS_VALUE (1 << 12) 128# define HIGH_BACKBIAS_VALUE (1 << 13) 129# define MEDIUM_BACKBIAS_VALUE (1 << 14) 130# define LOW_BACKBIAS_VALUE (1 << 15) 131 132#define CG_DISPLAY_GAP_CNTL 0x7dc 133# define DISP1_GAP(x) ((x) << 0) 134# define DISP1_GAP_MASK (3 << 0) 135# define DISP2_GAP(x) ((x) << 2) 136# define DISP2_GAP_MASK (3 << 2) 137# define VBI_TIMER_COUNT(x) ((x) << 4) 138# define VBI_TIMER_COUNT_MASK (0x3fff << 4) 139# define VBI_TIMER_UNIT(x) ((x) << 20) 140# define VBI_TIMER_UNIT_MASK (7 << 20) 141# define DISP1_GAP_MCHG(x) ((x) << 24) 142# define DISP1_GAP_MCHG_MASK (3 << 24) 143# define DISP2_GAP_MCHG(x) ((x) << 26) 144# define DISP2_GAP_MCHG_MASK (3 << 26) 145 146#define CG_THERMAL_CTRL 0x7f0 147# define DPM_EVENT_SRC(x) ((x) << 0) 148# define DPM_EVENT_SRC_MASK (7 << 0) 149# define THERM_INC_CLK (1 << 3) 150# define TOFFSET(x) ((x) << 4) 151# define TOFFSET_MASK (0xff << 4) 152# define DIG_THERM_DPM(x) ((x) << 12) 153# define DIG_THERM_DPM_MASK (0xff << 12) 154# define CTF_SEL(x) ((x) << 20) 155# define CTF_SEL_MASK (7 << 20) 156# define CTF_PAD_POLARITY (1 << 23) 157# define CTF_PAD_EN (1 << 24) 158 159#define CG_SPLL_SPREAD_SPECTRUM_LOW 0x820 160# define SSEN (1 << 0) 161# define CLKS(x) ((x) << 3) 162# define CLKS_MASK (0xff << 3) 163# define CLKS_SHIFT 3 164# define CLKV(x) ((x) << 11) 165# define CLKV_MASK (0x7ff << 11) 166# define CLKV_SHIFT 11 167#define CG_MPLL_SPREAD_SPECTRUM 0x830 168 169#define CITF_CNTL 0x200c 170# define BLACKOUT_RD (1 << 0) 171# define BLACKOUT_WR (1 << 1) 172 173#define RAMCFG 0x2408 174#define NOOFBANK_SHIFT 0 175#define NOOFBANK_MASK 0x00000001 176#define NOOFRANK_SHIFT 1 177#define NOOFRANK_MASK 0x00000002 178#define NOOFROWS_SHIFT 2 179#define NOOFROWS_MASK 0x0000001C 180#define NOOFCOLS_SHIFT 5 181#define NOOFCOLS_MASK 0x00000060 182#define CHANSIZE_SHIFT 7 183#define CHANSIZE_MASK 0x00000080 184#define BURSTLENGTH_SHIFT 8 185#define BURSTLENGTH_MASK 0x00000100 186#define CHANSIZE_OVERRIDE (1 << 10) 187 188#define SQM_RATIO 0x2424 189# define STATE0(x) ((x) << 0) 190# define STATE0_MASK (0xff << 0) 191# define STATE1(x) ((x) << 8) 192# define STATE1_MASK (0xff << 8) 193# define STATE2(x) ((x) << 16) 194# define STATE2_MASK (0xff << 16) 195# define STATE3(x) ((x) << 24) 196# define STATE3_MASK (0xff << 24) 197 198#define ARB_RFSH_CNTL 0x2460 199# define ENABLE (1 << 0) 200#define ARB_RFSH_RATE 0x2464 201# define POWERMODE0(x) ((x) << 0) 202# define POWERMODE0_MASK (0xff << 0) 203# define POWERMODE1(x) ((x) << 8) 204# define POWERMODE1_MASK (0xff << 8) 205# define POWERMODE2(x) ((x) << 16) 206# define POWERMODE2_MASK (0xff << 16) 207# define POWERMODE3(x) ((x) << 24) 208# define POWERMODE3_MASK (0xff << 24) 209 210#define MC_SEQ_DRAM 0x2608 211# define CKE_DYN (1 << 12) 212 213#define MC_SEQ_CMD 0x26c4 214 215#define MC_SEQ_RESERVE_S 0x2890 216#define MC_SEQ_RESERVE_M 0x2894 217 218#define LVTMA_DATA_SYNCHRONIZATION 0x7adc 219# define LVTMA_PFREQCHG (1 << 8) 220#define DCE3_LVTMA_DATA_SYNCHRONIZATION 0x7f98 221 222/* PCIE indirect regs */ 223#define PCIE_P_CNTL 0x40 224# define P_PLL_PWRDN_IN_L1L23 (1 << 3) 225# define P_PLL_BUF_PDNB (1 << 4) 226# define P_PLL_PDNB (1 << 9) 227# define P_ALLOW_PRX_FRONTEND_SHUTOFF (1 << 12) 228/* PCIE PORT indirect regs */ 229#define PCIE_LC_CNTL 0xa0 230# define LC_L0S_INACTIVITY(x) ((x) << 8) 231# define LC_L0S_INACTIVITY_MASK (0xf << 8) 232# define LC_L0S_INACTIVITY_SHIFT 8 233# define LC_L1_INACTIVITY(x) ((x) << 12) 234# define LC_L1_INACTIVITY_MASK (0xf << 12) 235# define LC_L1_INACTIVITY_SHIFT 12 236# define LC_PMI_TO_L1_DIS (1 << 16) 237# define LC_ASPM_TO_L1_DIS (1 << 24) 238#define PCIE_LC_SPEED_CNTL 0xa4 239# define LC_GEN2_EN (1 << 0) 240# define LC_INITIATE_LINK_SPEED_CHANGE (1 << 7) 241# define LC_CURRENT_DATA_RATE (1 << 11) 242# define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 243# define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 244# define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 245# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 246# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 247 248#endif 249