1/* $NetBSD: rv770d.h,v 1.4 2021/12/18 23:45:43 riastradh Exp $ */ 2 3/* 4 * Copyright 2009 Advanced Micro Devices, Inc. 5 * Copyright 2009 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29#ifndef RV770_H 30#define RV770_H 31 32#define R7XX_MAX_SH_GPRS 256 33#define R7XX_MAX_TEMP_GPRS 16 34#define R7XX_MAX_SH_THREADS 256 35#define R7XX_MAX_SH_STACK_ENTRIES 4096 36#define R7XX_MAX_BACKENDS 8 37#define R7XX_MAX_BACKENDS_MASK 0xff 38#define R7XX_MAX_SIMDS 16 39#define R7XX_MAX_SIMDS_MASK 0xffff 40#define R7XX_MAX_PIPES 8 41#define R7XX_MAX_PIPES_MASK 0xff 42 43/* discrete uvd clocks */ 44#define CG_UPLL_FUNC_CNTL 0x718 45# define UPLL_RESET_MASK 0x00000001 46# define UPLL_SLEEP_MASK 0x00000002 47# define UPLL_BYPASS_EN_MASK 0x00000004 48# define UPLL_CTLREQ_MASK 0x00000008 49# define UPLL_REF_DIV(x) ((x) << 16) 50# define UPLL_REF_DIV_MASK 0x003F0000 51# define UPLL_CTLACK_MASK 0x40000000 52# define UPLL_CTLACK2_MASK 0x80000000 53#define CG_UPLL_FUNC_CNTL_2 0x71c 54# define UPLL_SW_HILEN(x) ((x) << 0) 55# define UPLL_SW_LOLEN(x) ((x) << 4) 56# define UPLL_SW_HILEN2(x) ((x) << 8) 57# define UPLL_SW_LOLEN2(x) ((x) << 12) 58# define UPLL_SW_MASK 0x0000FFFF 59# define VCLK_SRC_SEL(x) ((x) << 20) 60# define VCLK_SRC_SEL_MASK 0x01F00000 61# define DCLK_SRC_SEL(x) ((x) << 25) 62# define DCLK_SRC_SEL_MASK 0x3E000000 63#define CG_UPLL_FUNC_CNTL_3 0x720 64# define UPLL_FB_DIV(x) ((x) << 0) 65# define UPLL_FB_DIV_MASK 0x01FFFFFF 66 67/* pm registers */ 68#define SMC_SRAM_ADDR 0x200 69#define SMC_SRAM_AUTO_INC_DIS (1 << 16) 70#define SMC_SRAM_DATA 0x204 71#define SMC_IO 0x208 72#define SMC_RST_N (1 << 0) 73#define SMC_STOP_MODE (1 << 2) 74#define SMC_CLK_EN (1 << 11) 75#define SMC_MSG 0x20c 76#define HOST_SMC_MSG(x) ((x) << 0) 77#define HOST_SMC_MSG_MASK (0xff << 0) 78#define HOST_SMC_MSG_SHIFT 0 79#define HOST_SMC_RESP(x) ((x) << 8) 80#define HOST_SMC_RESP_MASK (0xff << 8) 81#define HOST_SMC_RESP_SHIFT 8 82#define SMC_HOST_MSG(x) ((x) << 16) 83#define SMC_HOST_MSG_MASK (0xff << 16) 84#define SMC_HOST_MSG_SHIFT 16 85#define SMC_HOST_RESP(x) ((x) << 24) 86#define SMC_HOST_RESP_MASK (0xff << 24) 87#define SMC_HOST_RESP_SHIFT 24 88 89#define SMC_ISR_FFD8_FFDB 0x218 90 91#define CG_SPLL_FUNC_CNTL 0x600 92#define SPLL_RESET (1 << 0) 93#define SPLL_SLEEP (1 << 1) 94#define SPLL_DIVEN (1 << 2) 95#define SPLL_BYPASS_EN (1 << 3) 96#define SPLL_REF_DIV(x) ((x) << 4) 97#define SPLL_REF_DIV_MASK (0x3f << 4) 98#define SPLL_HILEN(x) ((x) << 12) 99#define SPLL_HILEN_MASK (0xf << 12) 100#define SPLL_LOLEN(x) ((x) << 16) 101#define SPLL_LOLEN_MASK (0xf << 16) 102#define CG_SPLL_FUNC_CNTL_2 0x604 103#define SCLK_MUX_SEL(x) ((x) << 0) 104#define SCLK_MUX_SEL_MASK (0x1ff << 0) 105#define SCLK_MUX_UPDATE (1 << 26) 106#define CG_SPLL_FUNC_CNTL_3 0x608 107#define SPLL_FB_DIV(x) ((x) << 0) 108#define SPLL_FB_DIV_MASK (0x3ffffff << 0) 109#define SPLL_DITHEN (1 << 28) 110#define CG_SPLL_STATUS 0x60c 111#define SPLL_CHG_STATUS (1 << 1) 112 113#define SPLL_CNTL_MODE 0x610 114#define SPLL_DIV_SYNC (1 << 5) 115 116#define MPLL_CNTL_MODE 0x61c 117# define MPLL_MCLK_SEL (1 << 11) 118# define RV730_MPLL_MCLK_SEL (1 << 25) 119 120#define MPLL_AD_FUNC_CNTL 0x624 121#define CLKF(x) ((x) << 0) 122#define CLKF_MASK (0x7f << 0) 123#define CLKR(x) ((x) << 7) 124#define CLKR_MASK (0x1f << 7) 125#define CLKFRAC(x) ((x) << 12) 126#define CLKFRAC_MASK (0x1f << 12) 127#define YCLK_POST_DIV(x) ((x) << 17) 128#define YCLK_POST_DIV_MASK (3 << 17) 129#define IBIAS(x) ((x) << 20) 130#define IBIAS_MASK (0x3ff << 20) 131#define RESET (1 << 30) 132#define PDNB (1 << 31) 133#define MPLL_AD_FUNC_CNTL_2 0x628 134#define BYPASS (1 << 19) 135#define BIAS_GEN_PDNB (1 << 24) 136#define RESET_EN (1 << 25) 137#define VCO_MODE (1 << 29) 138#define MPLL_DQ_FUNC_CNTL 0x62c 139#define MPLL_DQ_FUNC_CNTL_2 0x630 140 141#define GENERAL_PWRMGT 0x63c 142# define GLOBAL_PWRMGT_EN (1 << 0) 143# define STATIC_PM_EN (1 << 1) 144# define THERMAL_PROTECTION_DIS (1 << 2) 145# define THERMAL_PROTECTION_TYPE (1 << 3) 146# define ENABLE_GEN2PCIE (1 << 4) 147# define ENABLE_GEN2XSP (1 << 5) 148# define SW_SMIO_INDEX(x) ((x) << 6) 149# define SW_SMIO_INDEX_MASK (3 << 6) 150# define SW_SMIO_INDEX_SHIFT 6 151# define LOW_VOLT_D2_ACPI (1 << 8) 152# define LOW_VOLT_D3_ACPI (1 << 9) 153# define VOLT_PWRMGT_EN (1 << 10) 154# define BACKBIAS_PAD_EN (1 << 18) 155# define BACKBIAS_VALUE (1 << 19) 156# define DYN_SPREAD_SPECTRUM_EN (1 << 23) 157# define AC_DC_SW (1 << 24) 158 159#define CG_TPC 0x640 160#define SCLK_PWRMGT_CNTL 0x644 161# define SCLK_PWRMGT_OFF (1 << 0) 162# define SCLK_LOW_D1 (1 << 1) 163# define FIR_RESET (1 << 4) 164# define FIR_FORCE_TREND_SEL (1 << 5) 165# define FIR_TREND_MODE (1 << 6) 166# define DYN_GFX_CLK_OFF_EN (1 << 7) 167# define GFX_CLK_FORCE_ON (1 << 8) 168# define GFX_CLK_REQUEST_OFF (1 << 9) 169# define GFX_CLK_FORCE_OFF (1 << 10) 170# define GFX_CLK_OFF_ACPI_D1 (1 << 11) 171# define GFX_CLK_OFF_ACPI_D2 (1 << 12) 172# define GFX_CLK_OFF_ACPI_D3 (1 << 13) 173#define MCLK_PWRMGT_CNTL 0x648 174# define DLL_SPEED(x) ((x) << 0) 175# define DLL_SPEED_MASK (0x1f << 0) 176# define MPLL_PWRMGT_OFF (1 << 5) 177# define DLL_READY (1 << 6) 178# define MC_INT_CNTL (1 << 7) 179# define MRDCKA0_SLEEP (1 << 8) 180# define MRDCKA1_SLEEP (1 << 9) 181# define MRDCKB0_SLEEP (1 << 10) 182# define MRDCKB1_SLEEP (1 << 11) 183# define MRDCKC0_SLEEP (1 << 12) 184# define MRDCKC1_SLEEP (1 << 13) 185# define MRDCKD0_SLEEP (1 << 14) 186# define MRDCKD1_SLEEP (1 << 15) 187# define MRDCKA0_RESET (1 << 16) 188# define MRDCKA1_RESET (1 << 17) 189# define MRDCKB0_RESET (1 << 18) 190# define MRDCKB1_RESET (1 << 19) 191# define MRDCKC0_RESET (1 << 20) 192# define MRDCKC1_RESET (1 << 21) 193# define MRDCKD0_RESET (1 << 22) 194# define MRDCKD1_RESET (1 << 23) 195# define DLL_READY_READ (1 << 24) 196# define USE_DISPLAY_GAP (1 << 25) 197# define USE_DISPLAY_URGENT_NORMAL (1 << 26) 198# define MPLL_TURNOFF_D2 (1 << 28) 199#define DLL_CNTL 0x64c 200# define MRDCKA0_BYPASS (1 << 24) 201# define MRDCKA1_BYPASS (1 << 25) 202# define MRDCKB0_BYPASS (1 << 26) 203# define MRDCKB1_BYPASS (1 << 27) 204# define MRDCKC0_BYPASS (1 << 28) 205# define MRDCKC1_BYPASS (1 << 29) 206# define MRDCKD0_BYPASS (1 << 30) 207# define MRDCKD1_BYPASS (1 << 31) 208 209#define MPLL_TIME 0x654 210# define MPLL_LOCK_TIME(x) ((x) << 0) 211# define MPLL_LOCK_TIME_MASK (0xffff << 0) 212# define MPLL_RESET_TIME(x) ((x) << 16) 213# define MPLL_RESET_TIME_MASK (0xffff << 16) 214 215#define CG_CLKPIN_CNTL 0x660 216# define MUX_TCLK_TO_XCLK (1 << 8) 217# define XTALIN_DIVIDE (1 << 9) 218 219#define TARGET_AND_CURRENT_PROFILE_INDEX 0x66c 220# define CURRENT_PROFILE_INDEX_MASK (0xf << 4) 221# define CURRENT_PROFILE_INDEX_SHIFT 4 222 223#define S0_VID_LOWER_SMIO_CNTL 0x678 224#define S1_VID_LOWER_SMIO_CNTL 0x67c 225#define S2_VID_LOWER_SMIO_CNTL 0x680 226#define S3_VID_LOWER_SMIO_CNTL 0x684 227 228#define CG_FTV 0x690 229#define CG_FFCT_0 0x694 230# define UTC_0(x) ((x) << 0) 231# define UTC_0_MASK (0x3ff << 0) 232# define DTC_0(x) ((x) << 10) 233# define DTC_0_MASK (0x3ff << 10) 234 235#define CG_BSP 0x6d0 236# define BSP(x) ((x) << 0) 237# define BSP_MASK (0xffff << 0) 238# define BSU(x) ((x) << 16) 239# define BSU_MASK (0xf << 16) 240#define CG_AT 0x6d4 241# define CG_R(x) ((x) << 0) 242# define CG_R_MASK (0xffff << 0) 243# define CG_L(x) ((x) << 16) 244# define CG_L_MASK (0xffff << 16) 245#define CG_GIT 0x6d8 246# define CG_GICST(x) ((x) << 0) 247# define CG_GICST_MASK (0xffff << 0) 248# define CG_GIPOT(x) ((x) << 16) 249# define CG_GIPOT_MASK (0xffff << 16) 250 251#define CG_SSP 0x6e8 252# define SST(x) ((x) << 0) 253# define SST_MASK (0xffff << 0) 254# define SSTU(x) ((x) << 16) 255# define SSTU_MASK (0xf << 16) 256 257#define CG_DISPLAY_GAP_CNTL 0x714 258# define DISP1_GAP(x) ((x) << 0) 259# define DISP1_GAP_MASK (3 << 0) 260# define DISP2_GAP(x) ((x) << 2) 261# define DISP2_GAP_MASK (3 << 2) 262# define VBI_TIMER_COUNT(x) ((x) << 4) 263# define VBI_TIMER_COUNT_MASK (0x3fff << 4) 264# define VBI_TIMER_UNIT(x) ((x) << 20) 265# define VBI_TIMER_UNIT_MASK (7 << 20) 266# define DISP1_GAP_MCHG(x) ((x) << 24) 267# define DISP1_GAP_MCHG_MASK (3 << 24) 268# define DISP2_GAP_MCHG(x) ((x) << 26) 269# define DISP2_GAP_MCHG_MASK (3 << 26) 270 271#define CG_SPLL_SPREAD_SPECTRUM 0x790 272#define SSEN (1 << 0) 273#define CLKS(x) ((x) << 4) 274#define CLKS_MASK (0xfff << 4) 275#define CG_SPLL_SPREAD_SPECTRUM_2 0x794 276#define CLKV(x) ((x) << 0) 277#define CLKV_MASK (0x3ffffff << 0) 278#define CG_MPLL_SPREAD_SPECTRUM 0x798 279#define CG_UPLL_SPREAD_SPECTRUM 0x79c 280# define SSEN_MASK 0x00000001 281 282#define CG_CGTT_LOCAL_0 0x7d0 283#define CG_CGTT_LOCAL_1 0x7d4 284 285#define BIOS_SCRATCH_4 0x1734 286 287#define MC_SEQ_MISC0 0x2a00 288#define MC_SEQ_MISC0_GDDR5_SHIFT 28 289#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 290#define MC_SEQ_MISC0_GDDR5_VALUE 5 291 292#define MC_ARB_SQM_RATIO 0x2770 293#define STATE0(x) ((x) << 0) 294#define STATE0_MASK (0xff << 0) 295#define STATE1(x) ((x) << 8) 296#define STATE1_MASK (0xff << 8) 297#define STATE2(x) ((x) << 16) 298#define STATE2_MASK (0xff << 16) 299#define STATE3(x) ((x) << 24) 300#define STATE3_MASK (0xff << 24) 301 302#define MC_ARB_RFSH_RATE 0x27b0 303#define POWERMODE0(x) ((x) << 0) 304#define POWERMODE0_MASK (0xff << 0) 305#define POWERMODE1(x) ((x) << 8) 306#define POWERMODE1_MASK (0xff << 8) 307#define POWERMODE2(x) ((x) << 16) 308#define POWERMODE2_MASK (0xff << 16) 309#define POWERMODE3(x) ((x) << 24) 310#define POWERMODE3_MASK (0xff << 24) 311 312#define CGTS_SM_CTRL_REG 0x9150 313 314/* Registers */ 315#define CB_COLOR0_BASE 0x28040 316#define CB_COLOR1_BASE 0x28044 317#define CB_COLOR2_BASE 0x28048 318#define CB_COLOR3_BASE 0x2804C 319#define CB_COLOR4_BASE 0x28050 320#define CB_COLOR5_BASE 0x28054 321#define CB_COLOR6_BASE 0x28058 322#define CB_COLOR7_BASE 0x2805C 323#define CB_COLOR7_FRAG 0x280FC 324 325#define CC_GC_SHADER_PIPE_CONFIG 0x8950 326#define CC_RB_BACKEND_DISABLE 0x98F4 327#define BACKEND_DISABLE(x) ((x) << 16) 328#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 329 330#define CGTS_SYS_TCC_DISABLE 0x3F90 331#define CGTS_TCC_DISABLE 0x9148 332#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 333#define CGTS_USER_TCC_DISABLE 0x914C 334 335#define CONFIG_MEMSIZE 0x5428 336 337#define CP_ME_CNTL 0x86D8 338#define CP_ME_HALT (1 << 28) 339#define CP_PFP_HALT (1 << 26) 340#define CP_ME_RAM_DATA 0xC160 341#define CP_ME_RAM_RADDR 0xC158 342#define CP_ME_RAM_WADDR 0xC15C 343#define CP_MEQ_THRESHOLDS 0x8764 344#define STQ_SPLIT(x) ((x) << 0) 345#define CP_PERFMON_CNTL 0x87FC 346#define CP_PFP_UCODE_ADDR 0xC150 347#define CP_PFP_UCODE_DATA 0xC154 348#define CP_QUEUE_THRESHOLDS 0x8760 349#define ROQ_IB1_START(x) ((x) << 0) 350#define ROQ_IB2_START(x) ((x) << 8) 351#define CP_RB_CNTL 0xC104 352#define RB_BUFSZ(x) ((x) << 0) 353#define RB_BLKSZ(x) ((x) << 8) 354#define RB_NO_UPDATE (1 << 27) 355#define RB_RPTR_WR_ENA (1 << 31) 356#define BUF_SWAP_32BIT (2 << 16) 357#define CP_RB_RPTR 0x8700 358#define CP_RB_RPTR_ADDR 0xC10C 359#define CP_RB_RPTR_ADDR_HI 0xC110 360#define CP_RB_RPTR_WR 0xC108 361#define CP_RB_WPTR 0xC114 362#define CP_RB_WPTR_ADDR 0xC118 363#define CP_RB_WPTR_ADDR_HI 0xC11C 364#define CP_RB_WPTR_DELAY 0x8704 365#define CP_SEM_WAIT_TIMER 0x85BC 366 367#define DB_DEBUG3 0x98B0 368#define DB_CLK_OFF_DELAY(x) ((x) << 11) 369#define DB_DEBUG4 0x9B8C 370#define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 371 372#define DCP_TILING_CONFIG 0x6CA0 373#define PIPE_TILING(x) ((x) << 1) 374#define BANK_TILING(x) ((x) << 4) 375#define GROUP_SIZE(x) ((x) << 6) 376#define ROW_TILING(x) ((x) << 8) 377#define BANK_SWAPS(x) ((x) << 11) 378#define SAMPLE_SPLIT(x) ((x) << 14) 379#define BACKEND_MAP(x) ((x) << 16) 380 381#define GB_TILING_CONFIG 0x98F0 382#define PIPE_TILING__SHIFT 1 383#define PIPE_TILING__MASK 0x0000000e 384 385#define DMA_TILING_CONFIG 0x3ec8 386#define DMA_TILING_CONFIG2 0xd0b8 387 388/* RV730 only */ 389#define UVD_UDEC_TILING_CONFIG 0xef40 390#define UVD_UDEC_DB_TILING_CONFIG 0xef44 391#define UVD_UDEC_DBW_TILING_CONFIG 0xef48 392#define UVD_NO_OP 0xeffc 393 394#define GC_USER_SHADER_PIPE_CONFIG 0x8954 395#define INACTIVE_QD_PIPES(x) ((x) << 8) 396#define INACTIVE_QD_PIPES_MASK 0x0000FF00 397#define INACTIVE_QD_PIPES_SHIFT 8 398#define INACTIVE_SIMDS(x) ((x) << 16) 399#define INACTIVE_SIMDS_MASK 0x00FF0000 400 401#define GRBM_CNTL 0x8000 402#define GRBM_READ_TIMEOUT(x) ((x) << 0) 403#define GRBM_SOFT_RESET 0x8020 404#define SOFT_RESET_CP (1<<0) 405#define GRBM_STATUS 0x8010 406#define CMDFIFO_AVAIL_MASK 0x0000000F 407#define GUI_ACTIVE (1<<31) 408#define GRBM_STATUS2 0x8014 409 410#define CG_THERMAL_CTRL 0x72C 411#define DPM_EVENT_SRC(x) ((x) << 0) 412#define DPM_EVENT_SRC_MASK (7 << 0) 413#define DIG_THERM_DPM(x) ((x) << 14) 414#define DIG_THERM_DPM_MASK 0x003FC000 415#define DIG_THERM_DPM_SHIFT 14 416 417#define CG_THERMAL_INT 0x734 418#define DIG_THERM_INTH(x) ((x) << 8) 419#define DIG_THERM_INTH_MASK 0x0000FF00 420#define DIG_THERM_INTH_SHIFT 8 421#define DIG_THERM_INTL(x) ((x) << 16) 422#define DIG_THERM_INTL_MASK 0x00FF0000 423#define DIG_THERM_INTL_SHIFT 16 424#define THERM_INT_MASK_HIGH (1 << 24) 425#define THERM_INT_MASK_LOW (1 << 25) 426 427#define CG_MULT_THERMAL_STATUS 0x740 428#define ASIC_T(x) ((x) << 16) 429#define ASIC_T_MASK 0x3FF0000 430#define ASIC_T_SHIFT 16 431 432#define HDP_HOST_PATH_CNTL 0x2C00 433#define HDP_NONSURFACE_BASE 0x2C04 434#define HDP_NONSURFACE_INFO 0x2C08 435#define HDP_NONSURFACE_SIZE 0x2C0C 436#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 437#define HDP_TILING_CONFIG 0x2F3C 438#define HDP_DEBUG1 0x2F34 439 440#define MC_SHARED_CHMAP 0x2004 441#define NOOFCHAN_SHIFT 12 442#define NOOFCHAN_MASK 0x00003000 443#define MC_SHARED_CHREMAP 0x2008 444 445#define MC_ARB_RAMCFG 0x2760 446#define NOOFBANK_SHIFT 0 447#define NOOFBANK_MASK 0x00000003 448#define NOOFRANK_SHIFT 2 449#define NOOFRANK_MASK 0x00000004 450#define NOOFROWS_SHIFT 3 451#define NOOFROWS_MASK 0x00000038 452#define NOOFCOLS_SHIFT 6 453#define NOOFCOLS_MASK 0x000000C0 454#define CHANSIZE_SHIFT 8 455#define CHANSIZE_MASK 0x00000100 456#define BURSTLENGTH_SHIFT 9 457#define BURSTLENGTH_MASK 0x00000200 458#define CHANSIZE_OVERRIDE (1 << 11) 459#define MC_VM_AGP_TOP 0x2028 460#define MC_VM_AGP_BOT 0x202C 461#define MC_VM_AGP_BASE 0x2030 462#define MC_VM_FB_LOCATION 0x2024 463#define MC_VM_MB_L1_TLB0_CNTL 0x2234 464#define MC_VM_MB_L1_TLB1_CNTL 0x2238 465#define MC_VM_MB_L1_TLB2_CNTL 0x223C 466#define MC_VM_MB_L1_TLB3_CNTL 0x2240 467#define ENABLE_L1_TLB (1 << 0) 468#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 469#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 470#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 471#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 472#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 473#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 474#define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15) 475#define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18) 476#define MC_VM_MD_L1_TLB0_CNTL 0x2654 477#define MC_VM_MD_L1_TLB1_CNTL 0x2658 478#define MC_VM_MD_L1_TLB2_CNTL 0x265C 479#define MC_VM_MD_L1_TLB3_CNTL 0x2698 480#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 481#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 482#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 483 484#define PA_CL_ENHANCE 0x8A14 485#define CLIP_VTX_REORDER_ENA (1 << 0) 486#define NUM_CLIP_SEQ(x) ((x) << 1) 487#define PA_SC_AA_CONFIG 0x28C04 488#define PA_SC_CLIPRECT_RULE 0x2820C 489#define PA_SC_EDGERULE 0x28230 490#define PA_SC_FIFO_SIZE 0x8BCC 491#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 492#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 493#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 494#define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0) 495#define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16) 496#define PA_SC_LINE_STIPPLE 0x28A0C 497#define PA_SC_LINE_STIPPLE_STATE 0x8B10 498#define PA_SC_MODE_CNTL 0x28A4C 499#define PA_SC_MULTI_CHIP_CNTL 0x8B20 500#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 501 502#define SCRATCH_REG0 0x8500 503#define SCRATCH_REG1 0x8504 504#define SCRATCH_REG2 0x8508 505#define SCRATCH_REG3 0x850C 506#define SCRATCH_REG4 0x8510 507#define SCRATCH_REG5 0x8514 508#define SCRATCH_REG6 0x8518 509#define SCRATCH_REG7 0x851C 510#define SCRATCH_UMSK 0x8540 511#define SCRATCH_ADDR 0x8544 512 513#define SMX_SAR_CTL0 0xA008 514#define SMX_DC_CTL0 0xA020 515#define USE_HASH_FUNCTION (1 << 0) 516#define CACHE_DEPTH(x) ((x) << 1) 517#define FLUSH_ALL_ON_EVENT (1 << 10) 518#define STALL_ON_EVENT (1 << 11) 519#define SMX_EVENT_CTL 0xA02C 520#define ES_FLUSH_CTL(x) ((x) << 0) 521#define GS_FLUSH_CTL(x) ((x) << 3) 522#define ACK_FLUSH_CTL(x) ((x) << 6) 523#define SYNC_FLUSH_CTL (1 << 8) 524 525#define SPI_CONFIG_CNTL 0x9100 526#define GPR_WRITE_PRIORITY(x) ((x) << 0) 527#define DISABLE_INTERP_1 (1 << 5) 528#define SPI_CONFIG_CNTL_1 0x913C 529#define VTX_DONE_DELAY(x) ((x) << 0) 530#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 531#define SPI_INPUT_Z 0x286D8 532#define SPI_PS_IN_CONTROL_0 0x286CC 533#define NUM_INTERP(x) ((x)<<0) 534#define POSITION_ENA (1<<8) 535#define POSITION_CENTROID (1<<9) 536#define POSITION_ADDR(x) ((x)<<10) 537#define PARAM_GEN(x) ((x)<<15) 538#define PARAM_GEN_ADDR(x) ((x)<<19) 539#define BARYC_SAMPLE_CNTL(x) ((x)<<26) 540#define PERSP_GRADIENT_ENA (1<<28) 541#define LINEAR_GRADIENT_ENA (1<<29) 542#define POSITION_SAMPLE (1<<30) 543#define BARYC_AT_SAMPLE_ENA (1<<31) 544 545#define SQ_CONFIG 0x8C00 546#define VC_ENABLE (1 << 0) 547#define EXPORT_SRC_C (1 << 1) 548#define DX9_CONSTS (1 << 2) 549#define ALU_INST_PREFER_VECTOR (1 << 3) 550#define DX10_CLAMP (1 << 4) 551#define CLAUSE_SEQ_PRIO(x) ((x) << 8) 552#define PS_PRIO(x) ((x) << 24) 553#define VS_PRIO(x) ((x) << 26) 554#define GS_PRIO(x) ((x) << 28) 555#define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0 556#define SIMDA_RING0(x) ((x)<<0) 557#define SIMDA_RING1(x) ((x)<<8) 558#define SIMDB_RING0(x) ((x)<<16) 559#define SIMDB_RING1(x) ((x)<<24) 560#define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4 561#define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8 562#define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC 563#define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0 564#define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4 565#define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8 566#define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC 567#define ES_PRIO(x) ((u32)(x) << 30) 568#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 569#define NUM_PS_GPRS(x) ((x) << 0) 570#define NUM_VS_GPRS(x) ((x) << 16) 571#define DYN_GPR_ENABLE (1 << 27) 572#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 573#define SQ_GPR_RESOURCE_MGMT_2 0x8C08 574#define NUM_GS_GPRS(x) ((x) << 0) 575#define NUM_ES_GPRS(x) ((x) << 16) 576#define SQ_MS_FIFO_SIZES 0x8CF0 577#define CACHE_FIFO_SIZE(x) ((x) << 0) 578#define FETCH_FIFO_HIWATER(x) ((x) << 8) 579#define DONE_FIFO_HIWATER(x) ((x) << 16) 580#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 581#define SQ_STACK_RESOURCE_MGMT_1 0x8C10 582#define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 583#define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 584#define SQ_STACK_RESOURCE_MGMT_2 0x8C14 585#define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 586#define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 587#define SQ_THREAD_RESOURCE_MGMT 0x8C0C 588#define NUM_PS_THREADS(x) ((x) << 0) 589#define NUM_VS_THREADS(x) ((x) << 8) 590#define NUM_GS_THREADS(x) ((x) << 16) 591#define NUM_ES_THREADS(x) ((x) << 24) 592 593#define SX_DEBUG_1 0x9058 594#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 595#define SX_EXPORT_BUFFER_SIZES 0x900C 596#define COLOR_BUFFER_SIZE(x) ((x) << 0) 597#define POSITION_BUFFER_SIZE(x) ((x) << 8) 598#define SMX_BUFFER_SIZE(x) ((x) << 16) 599#define SX_MISC 0x28350 600 601#define TA_CNTL_AUX 0x9508 602#define DISABLE_CUBE_WRAP (1 << 0) 603#define DISABLE_CUBE_ANISO (1 << 1) 604#define SYNC_GRADIENT (1 << 24) 605#define SYNC_WALKER (1 << 25) 606#define SYNC_ALIGNER (1 << 26) 607#define BILINEAR_PRECISION_6_BIT (0 << 31) 608#define BILINEAR_PRECISION_8_BIT (1 << 31) 609 610#define TCP_CNTL 0x9610 611#define TCP_CHAN_STEER 0x9614 612 613#define VC_ENHANCE 0x9714 614 615#define VGT_CACHE_INVALIDATION 0x88C4 616#define CACHE_INVALIDATION(x) ((x)<<0) 617#define VC_ONLY 0 618#define TC_ONLY 1 619#define VC_AND_TC 2 620#define AUTO_INVLD_EN(x) ((x) << 6) 621#define NO_AUTO 0 622#define ES_AUTO 1 623#define GS_AUTO 2 624#define ES_AND_GS_AUTO 3 625#define VGT_ES_PER_GS 0x88CC 626#define VGT_GS_PER_ES 0x88C8 627#define VGT_GS_PER_VS 0x88E8 628#define VGT_GS_VERTEX_REUSE 0x88D4 629#define VGT_NUM_INSTANCES 0x8974 630#define VGT_OUT_DEALLOC_CNTL 0x28C5C 631#define DEALLOC_DIST_MASK 0x0000007F 632#define VGT_STRMOUT_EN 0x28AB0 633#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 634#define VTX_REUSE_DEPTH_MASK 0x000000FF 635 636#define VM_CONTEXT0_CNTL 0x1410 637#define ENABLE_CONTEXT (1 << 0) 638#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 639#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 640#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 641#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 642#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 643#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 644#define VM_L2_CNTL 0x1400 645#define ENABLE_L2_CACHE (1 << 0) 646#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 647#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 648#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 649#define VM_L2_CNTL2 0x1404 650#define INVALIDATE_ALL_L1_TLBS (1 << 0) 651#define INVALIDATE_L2_CACHE (1 << 1) 652#define VM_L2_CNTL3 0x1408 653#define BANK_SELECT(x) ((x) << 0) 654#define CACHE_UPDATE_MODE(x) ((x) << 6) 655#define VM_L2_STATUS 0x140C 656#define L2_BUSY (1 << 0) 657 658#define WAIT_UNTIL 0x8040 659 660/* async DMA */ 661#define DMA_RB_RPTR 0xd008 662#define DMA_RB_WPTR 0xd00c 663 664/* async DMA packets */ 665#define DMA_PACKET(cmd, t, s, n) ((((u32)(cmd) & 0xF) << 28) | \ 666 (((t) & 0x1) << 23) | \ 667 (((s) & 0x1) << 22) | \ 668 (((n) & 0xFFFF) << 0)) 669/* async DMA Packet types */ 670#define DMA_PACKET_WRITE 0x2 671#define DMA_PACKET_COPY 0x3 672#define DMA_PACKET_INDIRECT_BUFFER 0x4 673#define DMA_PACKET_SEMAPHORE 0x5 674#define DMA_PACKET_FENCE 0x6 675#define DMA_PACKET_TRAP 0x7 676#define DMA_PACKET_CONSTANT_FILL 0xd 677#define DMA_PACKET_NOP 0xf 678 679 680#define SRBM_STATUS 0x0E50 681 682/* DCE 3.2 HDMI */ 683#define HDMI_CONTROL 0x7400 684# define HDMI_KEEPOUT_MODE (1 << 0) 685# define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */ 686# define HDMI_ERROR_ACK (1 << 8) 687# define HDMI_ERROR_MASK (1 << 9) 688#define HDMI_STATUS 0x7404 689# define HDMI_ACTIVE_AVMUTE (1 << 0) 690# define HDMI_AUDIO_PACKET_ERROR (1 << 16) 691# define HDMI_VBI_PACKET_ERROR (1 << 20) 692#define HDMI_AUDIO_PACKET_CONTROL 0x7408 693# define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 694# define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 695#define HDMI_ACR_PACKET_CONTROL 0x740c 696# define HDMI_ACR_SEND (1 << 0) 697# define HDMI_ACR_CONT (1 << 1) 698# define HDMI_ACR_SELECT(x) (((x) & 3) << 4) 699# define HDMI_ACR_HW 0 700# define HDMI_ACR_32 1 701# define HDMI_ACR_44 2 702# define HDMI_ACR_48 3 703# define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 704# define HDMI_ACR_AUTO_SEND (1 << 12) 705#define HDMI_VBI_PACKET_CONTROL 0x7410 706# define HDMI_NULL_SEND (1 << 0) 707# define HDMI_GC_SEND (1 << 4) 708# define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 709#define HDMI_INFOFRAME_CONTROL0 0x7414 710# define HDMI_AVI_INFO_SEND (1 << 0) 711# define HDMI_AVI_INFO_CONT (1 << 1) 712# define HDMI_AUDIO_INFO_SEND (1 << 4) 713# define HDMI_AUDIO_INFO_CONT (1 << 5) 714# define HDMI_MPEG_INFO_SEND (1 << 8) 715# define HDMI_MPEG_INFO_CONT (1 << 9) 716#define HDMI_INFOFRAME_CONTROL1 0x7418 717# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 718# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 719# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 720#define HDMI_GENERIC_PACKET_CONTROL 0x741c 721# define HDMI_GENERIC0_SEND (1 << 0) 722# define HDMI_GENERIC0_CONT (1 << 1) 723# define HDMI_GENERIC1_SEND (1 << 4) 724# define HDMI_GENERIC1_CONT (1 << 5) 725# define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 726# define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 727#define HDMI_GC 0x7428 728# define HDMI_GC_AVMUTE (1 << 0) 729#define AFMT_AUDIO_PACKET_CONTROL2 0x742c 730# define AFMT_AUDIO_LAYOUT_OVRD (1 << 0) 731# define AFMT_AUDIO_LAYOUT_SELECT (1 << 1) 732# define AFMT_60958_CS_SOURCE (1 << 4) 733# define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8) 734# define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16) 735#define AFMT_AVI_INFO0 0x7454 736# define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 737# define AFMT_AVI_INFO_S(x) (((x) & 3) << 8) 738# define AFMT_AVI_INFO_B(x) (((x) & 3) << 10) 739# define AFMT_AVI_INFO_A(x) (((x) & 1) << 12) 740# define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13) 741# define AFMT_AVI_INFO_Y_RGB 0 742# define AFMT_AVI_INFO_Y_YCBCR422 1 743# define AFMT_AVI_INFO_Y_YCBCR444 2 744# define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 745# define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16) 746# define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20) 747# define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22) 748# define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 749# define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24) 750# define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26) 751# define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28) 752# define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31) 753# define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 754#define AFMT_AVI_INFO1 0x7458 755# define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 756# define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 757# define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 758#define AFMT_AVI_INFO2 0x745c 759# define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 760# define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 761#define AFMT_AVI_INFO3 0x7460 762# define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 763# define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24) 764#define AFMT_MPEG_INFO0 0x7464 765# define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 766# define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 767# define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 768# define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 769#define AFMT_MPEG_INFO1 0x7468 770# define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 771# define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8) 772# define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12) 773#define AFMT_GENERIC0_HDR 0x746c 774#define AFMT_GENERIC0_0 0x7470 775#define AFMT_GENERIC0_1 0x7474 776#define AFMT_GENERIC0_2 0x7478 777#define AFMT_GENERIC0_3 0x747c 778#define AFMT_GENERIC0_4 0x7480 779#define AFMT_GENERIC0_5 0x7484 780#define AFMT_GENERIC0_6 0x7488 781#define AFMT_GENERIC1_HDR 0x748c 782#define AFMT_GENERIC1_0 0x7490 783#define AFMT_GENERIC1_1 0x7494 784#define AFMT_GENERIC1_2 0x7498 785#define AFMT_GENERIC1_3 0x749c 786#define AFMT_GENERIC1_4 0x74a0 787#define AFMT_GENERIC1_5 0x74a4 788#define AFMT_GENERIC1_6 0x74a8 789#define HDMI_ACR_32_0 0x74ac 790# define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 791#define HDMI_ACR_32_1 0x74b0 792# define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0) 793#define HDMI_ACR_44_0 0x74b4 794# define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 795#define HDMI_ACR_44_1 0x74b8 796# define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) 797#define HDMI_ACR_48_0 0x74bc 798# define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 799#define HDMI_ACR_48_1 0x74c0 800# define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0) 801#define HDMI_ACR_STATUS_0 0x74c4 802#define HDMI_ACR_STATUS_1 0x74c8 803#define AFMT_AUDIO_INFO0 0x74cc 804# define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 805# define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8) 806# define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16) 807#define AFMT_AUDIO_INFO1 0x74d0 808# define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 809# define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 810# define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 811# define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 812#define AFMT_60958_0 0x74d4 813# define AFMT_60958_CS_A(x) (((x) & 1) << 0) 814# define AFMT_60958_CS_B(x) (((x) & 1) << 1) 815# define AFMT_60958_CS_C(x) (((x) & 1) << 2) 816# define AFMT_60958_CS_D(x) (((x) & 3) << 3) 817# define AFMT_60958_CS_MODE(x) (((x) & 3) << 6) 818# define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 819# define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 820# define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 821# define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 822# define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 823#define AFMT_60958_1 0x74d8 824# define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 825# define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 826# define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16) 827# define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18) 828# define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 829#define AFMT_AUDIO_CRC_CONTROL 0x74dc 830# define AFMT_AUDIO_CRC_EN (1 << 0) 831#define AFMT_RAMP_CONTROL0 0x74e0 832# define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 833# define AFMT_RAMP_DATA_SIGN (1 << 31) 834#define AFMT_RAMP_CONTROL1 0x74e4 835# define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 836# define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24) 837#define AFMT_RAMP_CONTROL2 0x74e8 838# define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 839#define AFMT_RAMP_CONTROL3 0x74ec 840# define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 841#define AFMT_60958_2 0x74f0 842# define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 843# define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 844# define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 845# define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 846# define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 847# define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 848#define AFMT_STATUS 0x7600 849# define AFMT_AUDIO_ENABLE (1 << 4) 850# define AFMT_AZ_FORMAT_WTRIG (1 << 28) 851# define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 852# define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 853#define AFMT_AUDIO_PACKET_CONTROL 0x7604 854# define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 855# define AFMT_AUDIO_TEST_EN (1 << 12) 856# define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 857# define AFMT_60958_CS_UPDATE (1 << 26) 858# define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 859# define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 860# define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 861# define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 862#define AFMT_VBI_PACKET_CONTROL 0x7608 863# define AFMT_GENERIC0_UPDATE (1 << 2) 864#define AFMT_INFOFRAME_CONTROL0 0x760c 865# define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hdmi regs */ 866# define AFMT_AUDIO_INFO_UPDATE (1 << 7) 867# define AFMT_MPEG_INFO_UPDATE (1 << 10) 868#define AFMT_GENERIC0_7 0x7610 869/* second instance starts at 0x7800 */ 870#define HDMI_OFFSET0 (0x7400 - 0x7400) 871#define HDMI_OFFSET1 (0x7800 - 0x7400) 872 873/* DCE3.2 ELD audio interface */ 874#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */ 875#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */ 876#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */ 877#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */ 878#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */ 879#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */ 880#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */ 881#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */ 882#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */ 883#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */ 884#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */ 885#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */ 886#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */ 887#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */ 888# define MAX_CHANNELS(x) (((x) & 0x7) << 0) 889/* max channels minus one. 7 = 8 channels */ 890# define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 891# define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 892# define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 893/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 894 * bit0 = 32 kHz 895 * bit1 = 44.1 kHz 896 * bit2 = 48 kHz 897 * bit3 = 88.2 kHz 898 * bit4 = 96 kHz 899 * bit5 = 176.4 kHz 900 * bit6 = 192 kHz 901 */ 902 903#define AZ_HOT_PLUG_CONTROL 0x7300 904# define AZ_FORCE_CODEC_WAKE (1 << 0) 905# define PIN0_JACK_DETECTION_ENABLE (1 << 4) 906# define PIN1_JACK_DETECTION_ENABLE (1 << 5) 907# define PIN2_JACK_DETECTION_ENABLE (1 << 6) 908# define PIN3_JACK_DETECTION_ENABLE (1 << 7) 909# define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8) 910# define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9) 911# define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10) 912# define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11) 913# define CODEC_HOT_PLUG_ENABLE (1 << 12) 914# define PIN0_AUDIO_ENABLED (1 << 24) 915# define PIN1_AUDIO_ENABLED (1 << 25) 916# define PIN2_AUDIO_ENABLED (1 << 26) 917# define PIN3_AUDIO_ENABLED (1 << 27) 918# define AUDIO_ENABLED (1 << 31) 919 920 921#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 922#define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 923#define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 924#define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 925#define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c 926#define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c 927 928/* PCIE indirect regs */ 929#define PCIE_P_CNTL 0x40 930# define P_PLL_PWRDN_IN_L1L23 (1 << 3) 931# define P_PLL_BUF_PDNB (1 << 4) 932# define P_PLL_PDNB (1 << 9) 933# define P_ALLOW_PRX_FRONTEND_SHUTOFF (1 << 12) 934/* PCIE PORT regs */ 935#define PCIE_LC_CNTL 0xa0 936# define LC_L0S_INACTIVITY(x) ((x) << 8) 937# define LC_L0S_INACTIVITY_MASK (0xf << 8) 938# define LC_L0S_INACTIVITY_SHIFT 8 939# define LC_L1_INACTIVITY(x) ((x) << 12) 940# define LC_L1_INACTIVITY_MASK (0xf << 12) 941# define LC_L1_INACTIVITY_SHIFT 12 942# define LC_PMI_TO_L1_DIS (1 << 16) 943# define LC_ASPM_TO_L1_DIS (1 << 24) 944#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 945#define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 946# define LC_LINK_WIDTH_SHIFT 0 947# define LC_LINK_WIDTH_MASK 0x7 948# define LC_LINK_WIDTH_X0 0 949# define LC_LINK_WIDTH_X1 1 950# define LC_LINK_WIDTH_X2 2 951# define LC_LINK_WIDTH_X4 3 952# define LC_LINK_WIDTH_X8 4 953# define LC_LINK_WIDTH_X16 6 954# define LC_LINK_WIDTH_RD_SHIFT 4 955# define LC_LINK_WIDTH_RD_MASK 0x70 956# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 957# define LC_RECONFIG_NOW (1 << 8) 958# define LC_RENEGOTIATION_SUPPORT (1 << 9) 959# define LC_RENEGOTIATE_EN (1 << 10) 960# define LC_SHORT_RECONFIG_EN (1 << 11) 961# define LC_UPCONFIGURE_SUPPORT (1 << 12) 962# define LC_UPCONFIGURE_DIS (1 << 13) 963#define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 964# define LC_GEN2_EN_STRAP (1 << 0) 965# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 966# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 967# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 968# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 969# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 970# define LC_CURRENT_DATA_RATE (1 << 11) 971# define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) 972# define LC_HW_VOLTAGE_IF_CONTROL_MASK (3 << 12) 973# define LC_HW_VOLTAGE_IF_CONTROL_SHIFT 12 974# define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 975# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 976# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 977# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 978#define MM_CFGREGS_CNTL 0x544c 979# define MM_WR_TO_CFG_EN (1 << 3) 980#define LINK_CNTL2 0x88 /* F0 */ 981# define TARGET_LINK_SPEED_MASK (0xf << 0) 982# define SELECTABLE_DEEMPHASIS (1 << 6) 983 984/* 985 * PM4 986 */ 987#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 988 (((reg) >> 2) & 0xFFFF) | \ 989 ((n) & 0x3FFF) << 16) 990#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 991 (((op) & 0xFF) << 8) | \ 992 ((n) & 0x3FFF) << 16) 993 994/* UVD */ 995#define UVD_SEMA_ADDR_LOW 0xef00 996#define UVD_SEMA_ADDR_HIGH 0xef04 997#define UVD_SEMA_CMD 0xef08 998#define UVD_GPCOM_VCPU_CMD 0xef0c 999#define UVD_GPCOM_VCPU_DATA0 0xef10 1000#define UVD_GPCOM_VCPU_DATA1 0xef14 1001 1002#define UVD_LMI_EXT40_ADDR 0xf498 1003#define UVD_VCPU_CHIP_ID 0xf4d4 1004#define UVD_VCPU_CACHE_OFFSET0 0xf4d8 1005#define UVD_VCPU_CACHE_SIZE0 0xf4dc 1006#define UVD_VCPU_CACHE_OFFSET1 0xf4e0 1007#define UVD_VCPU_CACHE_SIZE1 0xf4e4 1008#define UVD_VCPU_CACHE_OFFSET2 0xf4e8 1009#define UVD_VCPU_CACHE_SIZE2 0xf4ec 1010#define UVD_LMI_ADDR_EXT 0xf594 1011 1012#define UVD_RBC_RB_RPTR 0xf690 1013#define UVD_RBC_RB_WPTR 0xf694 1014 1015#define UVD_CONTEXT_ID 0xf6f4 1016 1017#endif 1018