/macosx-10.9.5/llvmCore-3425.0.33/examples/OCaml-Kaleidoscope/Chapter7/ |
H A D | toy.ml | 33 (* Promote allocas to registers. *)
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/macosx-10.9.5/cups-372.4/cups/conf/ |
H A D | cupsd.conf.in | 69 <Limit Pause-Printer Resume-Printer Enable-Printer Disable-Printer Pause-Printer-After-Current-Job Hold-New-Jobs Release-Held-New-Jobs Deactivate-Printer Activate-Printer Restart-Printer Shutdown-Printer Startup-Printer Promote-Job Schedule-Job-After Cancel-Jobs CUPS-Accept-Jobs CUPS-Reject-Jobs> 114 <Limit Pause-Printer Resume-Printer Enable-Printer Disable-Printer Pause-Printer-After-Current-Job Hold-New-Jobs Release-Held-New-Jobs Deactivate-Printer Activate-Printer Restart-Printer Shutdown-Printer Startup-Printer Promote-Job Schedule-Job-After Cancel-Jobs CUPS-Accept-Jobs CUPS-Reject-Jobs> 160 <Limit Pause-Printer Resume-Printer Enable-Printer Disable-Printer Pause-Printer-After-Current-Job Hold-New-Jobs Release-Held-New-Jobs Deactivate-Printer Activate-Printer Restart-Printer Shutdown-Printer Startup-Printer Promote-Job Schedule-Job-After Cancel-Jobs CUPS-Accept-Jobs CUPS-Reject-Jobs>
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 114 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 115 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 116 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 303 setOperationAction(ISD::CTLZ , MVT::i8, Promote); 304 setOperationAction(ISD::CTLZ , MVT::i16, Promote); 333 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); 334 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); 335 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); 336 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); 351 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); 2367 SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N); local 2384 SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N); local 2418 SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N); local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 453 // Promote the value if needed. 1133 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); 1134 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); 1135 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); 1136 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); 1138 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); 1139 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); 1140 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); 1141 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); 1143 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Target/ |
H A D | TargetLowering.h | 87 Promote, // This operation should be executed in a larger type. enumerator in enum:llvm::TargetLowering::LegalizeAction 282 /// type (return 'Promote'), or we need to expand it into multiple registers 505 assert(Action != Promote && "Can't promote condition code!"); 520 assert(getOperationAction(Op, VT) == Promote && 538 getOperationAction(Op, NVT) == Promote); 1982 && "Promote may not follow Expand or Promote"); 2033 // Promote the integer element types until a legal vector type is found
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.cpp | 92 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 93 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 94 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 731 // Promote the value if needed.
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 472 // Promote the value if needed.
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 236 setOperationAction(ISD::VAARG, MVT::i1, Promote); 238 setOperationAction(ISD::VAARG, MVT::i8, Promote); 240 setOperationAction(ISD::VAARG, MVT::i16, Promote); 242 setOperationAction(ISD::VAARG, MVT::i32, Promote); 285 // We cannot do this with Promote because i64 is not a legal type. 325 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); 329 setOperationAction(ISD::AND , VT, Promote); 331 setOperationAction(ISD::OR , VT, Promote); 333 setOperationAction(ISD::XOR , VT, Promote); [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 129 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 130 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 944 // Promote the value if needed.
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 178 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 179 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 238 case TargetLowering::Promote: 241 // "Promote" the operation by bitcasting 247 // "Promote" the operation by extending the operand.
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H A D | LegalizeDAG.cpp | 733 case TargetLowering::Promote: { 754 // Promote to a byte-sized store with upper bits zero if not 891 case TargetLowering::Promote: { 929 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 930 // Promote to a byte-sized load if not loading an integral number of 1161 if (Action != TargetLowering::Promote) 1339 case TargetLowering::Promote: 3674 // Promote each of the values to the new type. 3695 // Promote each of the values to the new type.
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 161 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 162 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 163 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 2544 // Promote i8 and i16 2957 // Promote the value if needed.
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 420 // Promote the value if needed. 704 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 96 setOperationAction(ISD::LOAD, VT, Promote); 99 setOperationAction(ISD::STORE, VT, Promote); 132 // Promote all bit-wise operations. 134 setOperationAction(ISD::AND, VT, Promote); 136 setOperationAction(ISD::OR, VT, Promote); 138 setOperationAction(ISD::XOR, VT, Promote); 581 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 1362 // Promote the value if needed.
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