Searched refs:NewOpc (Results 1 - 16 of 16) sorted by relevance

/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DThumb2InstrInfo.cpp439 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
440 MI.setDesc(TII.get(NewOpc));
473 unsigned NewOpc = Opcode;
483 NewOpc = immediateOffsetOpcode(Opcode);
495 NewOpc = negativeOffsetOpcode(Opcode);
500 NewOpc = positiveOffsetOpcode(Opcode);
521 if (NewOpc != Opcode)
522 MI.setDesc(TII.get(NewOpc));
555 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
H A DARMLoadStoreOptimizer.cpp776 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); local
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
875 unsigned NewOpc = 0; local
893 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub);
912 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub);
930 BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
939 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
941 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
946 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), M
1072 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument
1135 unsigned NewOpc = (isLd) local
1158 unsigned NewOpc = (isLd) local
1406 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); local
1560 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument
1728 unsigned NewOpc = 0; local
[all...]
H A DARMConstantIslandPass.cpp1700 unsigned NewOpc = 0; local
1707 NewOpc = ARM::tLEApcrel;
1714 NewOpc = ARM::tLDRpci;
1721 if (!NewOpc)
1734 U.MI->setDesc(TII->get(NewOpc));
1754 unsigned NewOpc = 0; local
1760 NewOpc = ARM::tB;
1765 NewOpc = ARM::tBcc;
1771 if (NewOpc) {
1776 Br.MI->setDesc(TII->get(NewOpc));
[all...]
H A DARMExpandPseudoInsts.cpp944 unsigned NewOpc = ARM::VLDMDIA; local
946 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
975 unsigned NewOpc = ARM::VSTMDIA; local
977 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1006 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q : local
1009 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
H A DARMISelLowering.cpp2380 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) local
2382 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
4937 unsigned NewOpc = 0; local
4942 NewOpc = ARMISD::VMULLs;
4947 NewOpc = ARMISD::VMULLu;
4952 NewOpc = ARMISD::VMULLs;
4955 NewOpc = ARMISD::VMULLu;
4959 NewOpc = ARMISD::VMULLu;
4964 if (!NewOpc) {
4983 return DAG.getNode(NewOpc, D
6652 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? local
6676 unsigned NewOpc; local
6999 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); local
8235 unsigned NewOpc = 0; local
8354 unsigned NewOpc = 0; local
[all...]
H A DThumb1RegisterInfo.cpp505 unsigned NewOpc = convertToNonSPOpcode(Opcode); variable
506 if (NewOpc != Opcode && FrameReg != ARM::SP)
507 MI.setDesc(TII.get(NewOpc));
H A DARMISelDAGToDAG.cpp3012 unsigned NewOpc = ARM::LDREXD; local
3014 NewOpc = ARM::t2LDREXD;
3028 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
3098 unsigned NewOpc = ARM::STREXD; local
3100 NewOpc = ARM::t2STREXD;
3102 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/
H A DX86MCInstLower.cpp223 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) { argument
224 OutMI.setOpcode(NewOpc);
228 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) { argument
229 OutMI.setOpcode(NewOpc);
H A DX86InstrInfo.cpp3304 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3355 unsigned NewOpc; local
3357 NewOpc = GetCondBranchFromCond(NewCC);
3359 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3362 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3369 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3831 unsigned NewOpc = 0; local
3835 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
3836 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
3837 case X86::TEST32rr: NewOpc
3892 unsigned NewOpc = 0; local
4146 unsigned NewOpc; local
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/
H A DSPUISelDAGToDAG.cpp608 unsigned NewOpc = 0; local
622 NewOpc = SPU::AIr32;
627 NewOpc = SPU::Ar32;
860 NewOpc = SPU::Ar32;
866 NewOpc = SPU::AIr32;
882 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
884 return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
H A DSPUISelLowering.cpp743 unsigned NewOpc = ISD::ANY_EXTEND; local
746 NewOpc = ISD::FP_EXTEND;
748 result = DAG.getNode(NewOpc, dl, OutVT, result);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMipsLongBranch.cpp220 unsigned NewOpc = TII->GetOppositeBranchOpc(Br->getOpcode()); local
221 const MCInstrDesc &NewDesc = TII->get(NewOpc);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp6777 unsigned NewOpc; local
6780 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6781 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6782 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6786 TmpInst.setOpcode(NewOpc);
7251 unsigned NewOpc; local
7254 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7255 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7256 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7257 case ARM::t2UXTB: NewOpc
7366 unsigned NewOpc; local
7405 unsigned NewOpc; local
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/
H A DMachineLICM.cpp1255 unsigned NewOpc = local
1260 if (NewOpc == 0) return 0;
1261 const MCInstrDesc &MID = TII->get(NewOpc);
H A DTwoAddressInstructionPass.cpp1106 unsigned NewOpc = local
1111 if (NewOpc != 0) {
1112 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp353 unsigned NewOpc = N->getOpcode(); local
363 NewOpc = ISD::FP_TO_SINT;
365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));

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