Lines Matching refs:NewOpc
2380 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2382 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
4937 unsigned NewOpc = 0;
4942 NewOpc = ARMISD::VMULLs;
4947 NewOpc = ARMISD::VMULLu;
4952 NewOpc = ARMISD::VMULLs;
4955 NewOpc = ARMISD::VMULLu;
4959 NewOpc = ARMISD::VMULLu;
4964 if (!NewOpc) {
4983 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4998 DAG.getNode(NewOpc, DL, VT,
5000 DAG.getNode(NewOpc, DL, VT,
6652 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
6662 BuildMI(*BB, MI, dl, TII->get(NewOpc))
6676 unsigned NewOpc;
6679 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
6680 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
6681 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
6683 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
6999 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7000 if (NewOpc) {
7003 MCID = &TII->get(NewOpc);
7018 assert(!NewOpc && "Optional cc_out operand required");
7037 assert(!NewOpc && "Optional cc_out operand required");
8235 unsigned NewOpc = 0;
8241 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
8243 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
8245 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
8247 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
8249 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
8251 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
8253 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
8255 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
8257 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
8259 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
8261 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
8263 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
8265 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
8267 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
8274 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
8275 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
8276 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
8319 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
8354 unsigned NewOpc = 0;
8358 NewOpc = ARMISD::VLD2DUP;
8361 NewOpc = ARMISD::VLD3DUP;
8364 NewOpc = ARMISD::VLD4DUP;
8393 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,