1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86InstrBuilder.h" 17#include "X86MachineFunctionInfo.h" 18#include "X86Subtarget.h" 19#include "X86TargetMachine.h" 20#include "llvm/DerivedTypes.h" 21#include "llvm/LLVMContext.h" 22#include "llvm/ADT/STLExtras.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineDominators.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/LiveVariables.h" 29#include "llvm/MC/MCAsmInfo.h" 30#include "llvm/MC/MCInst.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetOptions.h" 36#include <limits> 37 38#define GET_INSTRINFO_CTOR 39#include "X86GenInstrInfo.inc" 40 41using namespace llvm; 42 43static cl::opt<bool> 44NoFusing("disable-spill-fusing", 45 cl::desc("Disable fusing of spill code into instructions")); 46static cl::opt<bool> 47PrintFailedFusing("print-failed-fuse-candidates", 48 cl::desc("Print instructions that the allocator wants to" 49 " fuse, but the X86 backend currently can't"), 50 cl::Hidden); 51static cl::opt<bool> 52ReMatPICStubLoad("remat-pic-stub-load", 53 cl::desc("Re-materialize load from stub in PIC mode"), 54 cl::init(false), cl::Hidden); 55 56enum { 57 // Select which memory operand is being unfolded. 58 // (stored in bits 0 - 3) 59 TB_INDEX_0 = 0, 60 TB_INDEX_1 = 1, 61 TB_INDEX_2 = 2, 62 TB_INDEX_3 = 3, 63 TB_INDEX_MASK = 0xf, 64 65 // Do not insert the reverse map (MemOp -> RegOp) into the table. 66 // This may be needed because there is a many -> one mapping. 67 TB_NO_REVERSE = 1 << 4, 68 69 // Do not insert the forward map (RegOp -> MemOp) into the table. 70 // This is needed for Native Client, which prohibits branch 71 // instructions from using a memory operand. 72 TB_NO_FORWARD = 1 << 5, 73 74 TB_FOLDED_LOAD = 1 << 6, 75 TB_FOLDED_STORE = 1 << 7, 76 77 // Minimum alignment required for load/store. 78 // Used for RegOp->MemOp conversion. 79 // (stored in bits 8 - 15) 80 TB_ALIGN_SHIFT = 8, 81 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, 82 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT, 83 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, 84 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT 85}; 86 87struct X86OpTblEntry { 88 uint16_t RegOp; 89 uint16_t MemOp; 90 uint16_t Flags; 91}; 92 93X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 94 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit() 95 ? X86::ADJCALLSTACKDOWN64 96 : X86::ADJCALLSTACKDOWN32), 97 (tm.getSubtarget<X86Subtarget>().is64Bit() 98 ? X86::ADJCALLSTACKUP64 99 : X86::ADJCALLSTACKUP32)), 100 TM(tm), RI(tm, *this) { 101 102 static const X86OpTblEntry OpTbl2Addr[] = { 103 { X86::ADC32ri, X86::ADC32mi, 0 }, 104 { X86::ADC32ri8, X86::ADC32mi8, 0 }, 105 { X86::ADC32rr, X86::ADC32mr, 0 }, 106 { X86::ADC64ri32, X86::ADC64mi32, 0 }, 107 { X86::ADC64ri8, X86::ADC64mi8, 0 }, 108 { X86::ADC64rr, X86::ADC64mr, 0 }, 109 { X86::ADD16ri, X86::ADD16mi, 0 }, 110 { X86::ADD16ri8, X86::ADD16mi8, 0 }, 111 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE }, 112 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE }, 113 { X86::ADD16rr, X86::ADD16mr, 0 }, 114 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE }, 115 { X86::ADD32ri, X86::ADD32mi, 0 }, 116 { X86::ADD32ri8, X86::ADD32mi8, 0 }, 117 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE }, 118 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }, 119 { X86::ADD32rr, X86::ADD32mr, 0 }, 120 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE }, 121 { X86::ADD64ri32, X86::ADD64mi32, 0 }, 122 { X86::ADD64ri8, X86::ADD64mi8, 0 }, 123 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE }, 124 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE }, 125 { X86::ADD64rr, X86::ADD64mr, 0 }, 126 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE }, 127 { X86::ADD8ri, X86::ADD8mi, 0 }, 128 { X86::ADD8rr, X86::ADD8mr, 0 }, 129 { X86::AND16ri, X86::AND16mi, 0 }, 130 { X86::AND16ri8, X86::AND16mi8, 0 }, 131 { X86::AND16rr, X86::AND16mr, 0 }, 132 { X86::AND32ri, X86::AND32mi, 0 }, 133 { X86::AND32ri8, X86::AND32mi8, 0 }, 134 { X86::AND32rr, X86::AND32mr, 0 }, 135 { X86::AND64ri32, X86::AND64mi32, 0 }, 136 { X86::AND64ri8, X86::AND64mi8, 0 }, 137 { X86::AND64rr, X86::AND64mr, 0 }, 138 { X86::AND8ri, X86::AND8mi, 0 }, 139 { X86::AND8rr, X86::AND8mr, 0 }, 140 { X86::DEC16r, X86::DEC16m, 0 }, 141 { X86::DEC32r, X86::DEC32m, 0 }, 142 { X86::DEC64_16r, X86::DEC64_16m, 0 }, 143 { X86::DEC64_32r, X86::DEC64_32m, 0 }, 144 { X86::DEC64r, X86::DEC64m, 0 }, 145 { X86::DEC8r, X86::DEC8m, 0 }, 146 { X86::INC16r, X86::INC16m, 0 }, 147 { X86::INC32r, X86::INC32m, 0 }, 148 { X86::INC64_16r, X86::INC64_16m, 0 }, 149 { X86::INC64_32r, X86::INC64_32m, 0 }, 150 { X86::INC64r, X86::INC64m, 0 }, 151 { X86::INC8r, X86::INC8m, 0 }, 152 { X86::NEG16r, X86::NEG16m, 0 }, 153 { X86::NEG32r, X86::NEG32m, 0 }, 154 { X86::NEG64r, X86::NEG64m, 0 }, 155 { X86::NEG8r, X86::NEG8m, 0 }, 156 { X86::NOT16r, X86::NOT16m, 0 }, 157 { X86::NOT32r, X86::NOT32m, 0 }, 158 { X86::NOT64r, X86::NOT64m, 0 }, 159 { X86::NOT8r, X86::NOT8m, 0 }, 160 { X86::OR16ri, X86::OR16mi, 0 }, 161 { X86::OR16ri8, X86::OR16mi8, 0 }, 162 { X86::OR16rr, X86::OR16mr, 0 }, 163 { X86::OR32ri, X86::OR32mi, 0 }, 164 { X86::OR32ri8, X86::OR32mi8, 0 }, 165 { X86::OR32rr, X86::OR32mr, 0 }, 166 { X86::OR64ri32, X86::OR64mi32, 0 }, 167 { X86::OR64ri8, X86::OR64mi8, 0 }, 168 { X86::OR64rr, X86::OR64mr, 0 }, 169 { X86::OR8ri, X86::OR8mi, 0 }, 170 { X86::OR8rr, X86::OR8mr, 0 }, 171 { X86::ROL16r1, X86::ROL16m1, 0 }, 172 { X86::ROL16rCL, X86::ROL16mCL, 0 }, 173 { X86::ROL16ri, X86::ROL16mi, 0 }, 174 { X86::ROL32r1, X86::ROL32m1, 0 }, 175 { X86::ROL32rCL, X86::ROL32mCL, 0 }, 176 { X86::ROL32ri, X86::ROL32mi, 0 }, 177 { X86::ROL64r1, X86::ROL64m1, 0 }, 178 { X86::ROL64rCL, X86::ROL64mCL, 0 }, 179 { X86::ROL64ri, X86::ROL64mi, 0 }, 180 { X86::ROL8r1, X86::ROL8m1, 0 }, 181 { X86::ROL8rCL, X86::ROL8mCL, 0 }, 182 { X86::ROL8ri, X86::ROL8mi, 0 }, 183 { X86::ROR16r1, X86::ROR16m1, 0 }, 184 { X86::ROR16rCL, X86::ROR16mCL, 0 }, 185 { X86::ROR16ri, X86::ROR16mi, 0 }, 186 { X86::ROR32r1, X86::ROR32m1, 0 }, 187 { X86::ROR32rCL, X86::ROR32mCL, 0 }, 188 { X86::ROR32ri, X86::ROR32mi, 0 }, 189 { X86::ROR64r1, X86::ROR64m1, 0 }, 190 { X86::ROR64rCL, X86::ROR64mCL, 0 }, 191 { X86::ROR64ri, X86::ROR64mi, 0 }, 192 { X86::ROR8r1, X86::ROR8m1, 0 }, 193 { X86::ROR8rCL, X86::ROR8mCL, 0 }, 194 { X86::ROR8ri, X86::ROR8mi, 0 }, 195 { X86::SAR16r1, X86::SAR16m1, 0 }, 196 { X86::SAR16rCL, X86::SAR16mCL, 0 }, 197 { X86::SAR16ri, X86::SAR16mi, 0 }, 198 { X86::SAR32r1, X86::SAR32m1, 0 }, 199 { X86::SAR32rCL, X86::SAR32mCL, 0 }, 200 { X86::SAR32ri, X86::SAR32mi, 0 }, 201 { X86::SAR64r1, X86::SAR64m1, 0 }, 202 { X86::SAR64rCL, X86::SAR64mCL, 0 }, 203 { X86::SAR64ri, X86::SAR64mi, 0 }, 204 { X86::SAR8r1, X86::SAR8m1, 0 }, 205 { X86::SAR8rCL, X86::SAR8mCL, 0 }, 206 { X86::SAR8ri, X86::SAR8mi, 0 }, 207 { X86::SBB32ri, X86::SBB32mi, 0 }, 208 { X86::SBB32ri8, X86::SBB32mi8, 0 }, 209 { X86::SBB32rr, X86::SBB32mr, 0 }, 210 { X86::SBB64ri32, X86::SBB64mi32, 0 }, 211 { X86::SBB64ri8, X86::SBB64mi8, 0 }, 212 { X86::SBB64rr, X86::SBB64mr, 0 }, 213 { X86::SHL16rCL, X86::SHL16mCL, 0 }, 214 { X86::SHL16ri, X86::SHL16mi, 0 }, 215 { X86::SHL32rCL, X86::SHL32mCL, 0 }, 216 { X86::SHL32ri, X86::SHL32mi, 0 }, 217 { X86::SHL64rCL, X86::SHL64mCL, 0 }, 218 { X86::SHL64ri, X86::SHL64mi, 0 }, 219 { X86::SHL8rCL, X86::SHL8mCL, 0 }, 220 { X86::SHL8ri, X86::SHL8mi, 0 }, 221 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 }, 222 { X86::SHLD16rri8, X86::SHLD16mri8, 0 }, 223 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 }, 224 { X86::SHLD32rri8, X86::SHLD32mri8, 0 }, 225 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 }, 226 { X86::SHLD64rri8, X86::SHLD64mri8, 0 }, 227 { X86::SHR16r1, X86::SHR16m1, 0 }, 228 { X86::SHR16rCL, X86::SHR16mCL, 0 }, 229 { X86::SHR16ri, X86::SHR16mi, 0 }, 230 { X86::SHR32r1, X86::SHR32m1, 0 }, 231 { X86::SHR32rCL, X86::SHR32mCL, 0 }, 232 { X86::SHR32ri, X86::SHR32mi, 0 }, 233 { X86::SHR64r1, X86::SHR64m1, 0 }, 234 { X86::SHR64rCL, X86::SHR64mCL, 0 }, 235 { X86::SHR64ri, X86::SHR64mi, 0 }, 236 { X86::SHR8r1, X86::SHR8m1, 0 }, 237 { X86::SHR8rCL, X86::SHR8mCL, 0 }, 238 { X86::SHR8ri, X86::SHR8mi, 0 }, 239 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 }, 240 { X86::SHRD16rri8, X86::SHRD16mri8, 0 }, 241 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 }, 242 { X86::SHRD32rri8, X86::SHRD32mri8, 0 }, 243 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 }, 244 { X86::SHRD64rri8, X86::SHRD64mri8, 0 }, 245 { X86::SUB16ri, X86::SUB16mi, 0 }, 246 { X86::SUB16ri8, X86::SUB16mi8, 0 }, 247 { X86::SUB16rr, X86::SUB16mr, 0 }, 248 { X86::SUB32ri, X86::SUB32mi, 0 }, 249 { X86::SUB32ri8, X86::SUB32mi8, 0 }, 250 { X86::SUB32rr, X86::SUB32mr, 0 }, 251 { X86::SUB64ri32, X86::SUB64mi32, 0 }, 252 { X86::SUB64ri8, X86::SUB64mi8, 0 }, 253 { X86::SUB64rr, X86::SUB64mr, 0 }, 254 { X86::SUB8ri, X86::SUB8mi, 0 }, 255 { X86::SUB8rr, X86::SUB8mr, 0 }, 256 { X86::XOR16ri, X86::XOR16mi, 0 }, 257 { X86::XOR16ri8, X86::XOR16mi8, 0 }, 258 { X86::XOR16rr, X86::XOR16mr, 0 }, 259 { X86::XOR32ri, X86::XOR32mi, 0 }, 260 { X86::XOR32ri8, X86::XOR32mi8, 0 }, 261 { X86::XOR32rr, X86::XOR32mr, 0 }, 262 { X86::XOR64ri32, X86::XOR64mi32, 0 }, 263 { X86::XOR64ri8, X86::XOR64mi8, 0 }, 264 { X86::XOR64rr, X86::XOR64mr, 0 }, 265 { X86::XOR8ri, X86::XOR8mi, 0 }, 266 { X86::XOR8rr, X86::XOR8mr, 0 } 267 }; 268 269 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 270 unsigned RegOp = OpTbl2Addr[i].RegOp; 271 unsigned MemOp = OpTbl2Addr[i].MemOp; 272 unsigned Flags = OpTbl2Addr[i].Flags; 273 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable, 274 RegOp, MemOp, 275 // Index 0, folded load and store, no alignment requirement. 276 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE); 277 } 278 279 static const X86OpTblEntry OpTbl0[] = { 280 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD }, 281 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD }, 282 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD }, 283 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD }, 284 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD }, 285 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD }, 286 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD }, 287 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD }, 288 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD }, 289 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD }, 290 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD }, 291 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD }, 292 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD }, 293 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD }, 294 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD }, 295 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD }, 296 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD }, 297 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD }, 298 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD }, 299 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD }, 300 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 301 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 302 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 303 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD }, 304 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD }, 305 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD }, 306 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD }, 307 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD }, 308 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD }, 309 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD }, 310 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD }, 311 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD }, 312 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD }, 313 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE }, 314 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE }, 315 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE }, 316 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE }, 317 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE }, 318 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE }, 319 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE }, 320 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE }, 321 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE }, 322 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 323 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 324 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 325 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE }, 326 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE }, 327 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE }, 328 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE }, 329 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE }, 330 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE }, 331 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD }, 332 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD }, 333 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD }, 334 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD }, 335 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE }, 336 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE }, 337 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE }, 338 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE }, 339 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE }, 340 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE }, 341 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE }, 342 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE }, 343 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE }, 344 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE }, 345 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE }, 346 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE }, 347 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE }, 348 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE }, 349 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE }, 350 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE }, 351 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD }, 352 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD }, 353 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD }, 354 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD }, 355 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD }, 356 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }, 357 // AVX 128-bit versions of foldable instructions 358 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 359 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 360 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE }, 361 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 362 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 363 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 364 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 }, 365 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE }, 366 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE }, 367 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE }, 368 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE }, 369 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE }, 370 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE }, 371 // AVX 256-bit foldable instructions 372 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 }, 373 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 374 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 375 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 }, 376 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE }, 377 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE } 378 }; 379 380 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 381 unsigned RegOp = OpTbl0[i].RegOp; 382 unsigned MemOp = OpTbl0[i].MemOp; 383 unsigned Flags = OpTbl0[i].Flags; 384 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable, 385 RegOp, MemOp, TB_INDEX_0 | Flags); 386 } 387 388 static const X86OpTblEntry OpTbl1[] = { 389 { X86::CMP16rr, X86::CMP16rm, 0 }, 390 { X86::CMP32rr, X86::CMP32rm, 0 }, 391 { X86::CMP64rr, X86::CMP64rm, 0 }, 392 { X86::CMP8rr, X86::CMP8rm, 0 }, 393 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 394 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 395 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 396 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 397 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 398 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 399 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 400 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 401 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 402 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 403 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE }, 404 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE }, 405 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 406 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 407 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 408 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 409 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 410 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 411 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 412 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 413 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 }, 414 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 }, 415 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 }, 416 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 }, 417 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 }, 418 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 }, 419 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 420 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 421 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 422 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 423 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 424 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 425 { X86::MOV16rr, X86::MOV16rm, 0 }, 426 { X86::MOV32rr, X86::MOV32rm, 0 }, 427 { X86::MOV64rr, X86::MOV64rm, 0 }, 428 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 429 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 430 { X86::MOV8rr, X86::MOV8rm, 0 }, 431 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 }, 432 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 }, 433 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 434 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 435 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 436 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 }, 437 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 }, 438 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 }, 439 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 440 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 441 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 442 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 443 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 444 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 445 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 }, 446 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 447 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 448 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 449 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 }, 450 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 451 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 452 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 453 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 454 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, 455 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 }, 456 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, 457 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 }, 458 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 }, 459 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 }, 460 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 }, 461 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 }, 462 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 }, 463 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 }, 464 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 }, 465 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 }, 466 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 }, 467 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 468 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 469 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 }, 470 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 }, 471 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 }, 472 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 }, 473 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 474 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 475 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 476 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 477 { X86::TEST16rr, X86::TEST16rm, 0 }, 478 { X86::TEST32rr, X86::TEST32rm, 0 }, 479 { X86::TEST64rr, X86::TEST64rm, 0 }, 480 { X86::TEST8rr, X86::TEST8rm, 0 }, 481 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 482 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 483 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, 484 // AVX 128-bit versions of foldable instructions 485 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 }, 486 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 }, 487 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 }, 488 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 }, 489 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 }, 490 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 }, 491 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 }, 492 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 }, 493 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 }, 494 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 }, 495 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 }, 496 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 }, 497 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 }, 498 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 }, 499 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 }, 500 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 }, 501 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE }, 502 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE }, 503 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 }, 504 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 }, 505 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 }, 506 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 }, 507 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 }, 508 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 }, 509 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 }, 510 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 }, 511 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 }, 512 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 }, 513 { X86::VMOVUPDrr, X86::VMOVUPDrm, TB_ALIGN_16 }, 514 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 }, 515 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 }, 516 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 }, 517 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 }, 518 { X86::VPABSBrr128, X86::VPABSBrm128, TB_ALIGN_16 }, 519 { X86::VPABSDrr128, X86::VPABSDrm128, TB_ALIGN_16 }, 520 { X86::VPABSWrr128, X86::VPABSWrm128, TB_ALIGN_16 }, 521 { X86::VPERMILPDri, X86::VPERMILPDmi, TB_ALIGN_16 }, 522 { X86::VPERMILPSri, X86::VPERMILPSmi, TB_ALIGN_16 }, 523 { X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 }, 524 { X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 }, 525 { X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 }, 526 { X86::VRCPPSr, X86::VRCPPSm, TB_ALIGN_16 }, 527 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, TB_ALIGN_16 }, 528 { X86::VRSQRTPSr, X86::VRSQRTPSm, TB_ALIGN_16 }, 529 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, TB_ALIGN_16 }, 530 { X86::VSQRTPDr, X86::VSQRTPDm, TB_ALIGN_16 }, 531 { X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, TB_ALIGN_16 }, 532 { X86::VSQRTPSr, X86::VSQRTPSm, TB_ALIGN_16 }, 533 { X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, TB_ALIGN_16 }, 534 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 }, 535 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 }, 536 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE }, 537 538 // AVX 256-bit foldable instructions 539 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 }, 540 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 }, 541 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 }, 542 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 }, 543 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 }, 544 { X86::VPERMILPDYri, X86::VPERMILPDYmi, TB_ALIGN_32 }, 545 { X86::VPERMILPSYri, X86::VPERMILPSYmi, TB_ALIGN_32 }, 546 547 // AVX2 foldable instructions 548 { X86::VPABSBrr256, X86::VPABSBrm256, TB_ALIGN_32 }, 549 { X86::VPABSDrr256, X86::VPABSDrm256, TB_ALIGN_32 }, 550 { X86::VPABSWrr256, X86::VPABSWrm256, TB_ALIGN_32 }, 551 { X86::VPSHUFDYri, X86::VPSHUFDYmi, TB_ALIGN_32 }, 552 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, TB_ALIGN_32 }, 553 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, TB_ALIGN_32 }, 554 { X86::VRCPPSYr, X86::VRCPPSYm, TB_ALIGN_32 }, 555 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, TB_ALIGN_32 }, 556 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, TB_ALIGN_32 }, 557 { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, TB_ALIGN_32 }, 558 { X86::VSQRTPDYr, X86::VSQRTPDYm, TB_ALIGN_32 }, 559 { X86::VSQRTPDYr_Int, X86::VSQRTPDYm_Int, TB_ALIGN_32 }, 560 { X86::VSQRTPSYr, X86::VSQRTPSYm, TB_ALIGN_32 }, 561 { X86::VSQRTPSYr_Int, X86::VSQRTPSYm_Int, TB_ALIGN_32 }, 562 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE }, 563 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE }, 564 565 // BMI/BMI2 foldable instructions 566 { X86::RORX32ri, X86::RORX32mi, 0 }, 567 { X86::RORX64ri, X86::RORX64mi, 0 }, 568 { X86::SARX32rr, X86::SARX32rm, 0 }, 569 { X86::SARX64rr, X86::SARX64rm, 0 }, 570 { X86::SHRX32rr, X86::SHRX32rm, 0 }, 571 { X86::SHRX64rr, X86::SHRX64rm, 0 }, 572 { X86::SHLX32rr, X86::SHLX32rm, 0 }, 573 { X86::SHLX64rr, X86::SHLX64rm, 0 }, 574 }; 575 576 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 577 unsigned RegOp = OpTbl1[i].RegOp; 578 unsigned MemOp = OpTbl1[i].MemOp; 579 unsigned Flags = OpTbl1[i].Flags; 580 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable, 581 RegOp, MemOp, 582 // Index 1, folded load 583 Flags | TB_INDEX_1 | TB_FOLDED_LOAD); 584 } 585 586 static const X86OpTblEntry OpTbl2[] = { 587 { X86::ADC32rr, X86::ADC32rm, 0 }, 588 { X86::ADC64rr, X86::ADC64rm, 0 }, 589 { X86::ADD16rr, X86::ADD16rm, 0 }, 590 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE }, 591 { X86::ADD32rr, X86::ADD32rm, 0 }, 592 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE }, 593 { X86::ADD64rr, X86::ADD64rm, 0 }, 594 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE }, 595 { X86::ADD8rr, X86::ADD8rm, 0 }, 596 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 }, 597 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 }, 598 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 599 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 600 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 }, 601 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 }, 602 { X86::AND16rr, X86::AND16rm, 0 }, 603 { X86::AND32rr, X86::AND32rm, 0 }, 604 { X86::AND64rr, X86::AND64rm, 0 }, 605 { X86::AND8rr, X86::AND8rm, 0 }, 606 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 }, 607 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 }, 608 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 }, 609 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 }, 610 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 }, 611 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 }, 612 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 }, 613 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 }, 614 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 615 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 616 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 617 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 618 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 619 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 620 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 621 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 622 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 623 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 624 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 625 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 626 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 627 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 628 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 629 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 630 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 631 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 632 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 633 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 634 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 635 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 636 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 637 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 638 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 639 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 640 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 641 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 642 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 643 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 644 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 645 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 646 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 647 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 648 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 649 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 650 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 651 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 652 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 653 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 654 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 655 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 656 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 657 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 658 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 659 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 660 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 661 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 662 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 }, 663 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 }, 664 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 665 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 666 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 }, 667 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 }, 668 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 669 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 670 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 }, 671 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 }, 672 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 }, 673 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 }, 674 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 }, 675 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 }, 676 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 }, 677 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 }, 678 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 }, 679 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 }, 680 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 }, 681 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 }, 682 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 683 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 684 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 685 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 686 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 687 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 688 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 689 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 690 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 691 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 692 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 693 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 }, 694 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 }, 695 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 }, 696 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 }, 697 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 698 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 }, 699 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 700 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 }, 701 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 }, 702 { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 }, 703 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 }, 704 { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 }, 705 { X86::MINSDrr, X86::MINSDrm, 0 }, 706 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 }, 707 { X86::MINSSrr, X86::MINSSrm, 0 }, 708 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 }, 709 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 }, 710 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 }, 711 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 }, 712 { X86::MULSDrr, X86::MULSDrm, 0 }, 713 { X86::MULSSrr, X86::MULSSrm, 0 }, 714 { X86::OR16rr, X86::OR16rm, 0 }, 715 { X86::OR32rr, X86::OR32rm, 0 }, 716 { X86::OR64rr, X86::OR64rm, 0 }, 717 { X86::OR8rr, X86::OR8rm, 0 }, 718 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 }, 719 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 }, 720 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 }, 721 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 }, 722 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 }, 723 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 }, 724 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 }, 725 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 }, 726 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 }, 727 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 }, 728 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 }, 729 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 }, 730 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 }, 731 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 }, 732 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 }, 733 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 }, 734 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 }, 735 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 }, 736 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 }, 737 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 }, 738 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 }, 739 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 }, 740 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 }, 741 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 }, 742 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 }, 743 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 }, 744 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 }, 745 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 }, 746 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 }, 747 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 }, 748 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 }, 749 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 }, 750 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 }, 751 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 }, 752 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 }, 753 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 }, 754 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 }, 755 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 }, 756 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 }, 757 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 }, 758 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 }, 759 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 }, 760 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 }, 761 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 }, 762 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 }, 763 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 }, 764 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 }, 765 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 }, 766 { X86::PORrr, X86::PORrm, TB_ALIGN_16 }, 767 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 }, 768 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 }, 769 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 }, 770 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 }, 771 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 }, 772 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 }, 773 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 }, 774 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 }, 775 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 }, 776 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 }, 777 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 }, 778 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 }, 779 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 }, 780 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 }, 781 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 }, 782 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 }, 783 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 }, 784 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 }, 785 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 }, 786 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 }, 787 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 }, 788 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 }, 789 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 }, 790 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 }, 791 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 }, 792 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 }, 793 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 }, 794 { X86::SBB32rr, X86::SBB32rm, 0 }, 795 { X86::SBB64rr, X86::SBB64rm, 0 }, 796 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 }, 797 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 }, 798 { X86::SUB16rr, X86::SUB16rm, 0 }, 799 { X86::SUB32rr, X86::SUB32rm, 0 }, 800 { X86::SUB64rr, X86::SUB64rm, 0 }, 801 { X86::SUB8rr, X86::SUB8rm, 0 }, 802 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 }, 803 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 }, 804 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 805 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 806 // FIXME: TEST*rr -> swapped operand of TEST*mr. 807 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 }, 808 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 }, 809 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 }, 810 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 }, 811 { X86::XOR16rr, X86::XOR16rm, 0 }, 812 { X86::XOR32rr, X86::XOR32rm, 0 }, 813 { X86::XOR64rr, X86::XOR64rm, 0 }, 814 { X86::XOR8rr, X86::XOR8rm, 0 }, 815 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 }, 816 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 }, 817 // AVX 128-bit versions of foldable instructions 818 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 }, 819 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 }, 820 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 }, 821 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 }, 822 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 }, 823 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 }, 824 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 }, 825 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 }, 826 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 }, 827 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 }, 828 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 }, 829 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 }, 830 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, TB_ALIGN_16 }, 831 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, TB_ALIGN_16 }, 832 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 }, 833 { X86::VSQRTSDr, X86::VSQRTSDm, 0 }, 834 { X86::VSQRTSSr, X86::VSQRTSSm, 0 }, 835 { X86::VADDPDrr, X86::VADDPDrm, TB_ALIGN_16 }, 836 { X86::VADDPSrr, X86::VADDPSrm, TB_ALIGN_16 }, 837 { X86::VADDSDrr, X86::VADDSDrm, 0 }, 838 { X86::VADDSSrr, X86::VADDSSrm, 0 }, 839 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, TB_ALIGN_16 }, 840 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, TB_ALIGN_16 }, 841 { X86::VANDNPDrr, X86::VANDNPDrm, TB_ALIGN_16 }, 842 { X86::VANDNPSrr, X86::VANDNPSrm, TB_ALIGN_16 }, 843 { X86::VANDPDrr, X86::VANDPDrm, TB_ALIGN_16 }, 844 { X86::VANDPSrr, X86::VANDPSrm, TB_ALIGN_16 }, 845 { X86::VBLENDPDrri, X86::VBLENDPDrmi, TB_ALIGN_16 }, 846 { X86::VBLENDPSrri, X86::VBLENDPSrmi, TB_ALIGN_16 }, 847 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, TB_ALIGN_16 }, 848 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, TB_ALIGN_16 }, 849 { X86::VCMPPDrri, X86::VCMPPDrmi, TB_ALIGN_16 }, 850 { X86::VCMPPSrri, X86::VCMPPSrmi, TB_ALIGN_16 }, 851 { X86::VCMPSDrr, X86::VCMPSDrm, 0 }, 852 { X86::VCMPSSrr, X86::VCMPSSrm, 0 }, 853 { X86::VDIVPDrr, X86::VDIVPDrm, TB_ALIGN_16 }, 854 { X86::VDIVPSrr, X86::VDIVPSrm, TB_ALIGN_16 }, 855 { X86::VDIVSDrr, X86::VDIVSDrm, 0 }, 856 { X86::VDIVSSrr, X86::VDIVSSrm, 0 }, 857 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 }, 858 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 }, 859 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 }, 860 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 }, 861 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 }, 862 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 }, 863 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 }, 864 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 }, 865 { X86::VHADDPDrr, X86::VHADDPDrm, TB_ALIGN_16 }, 866 { X86::VHADDPSrr, X86::VHADDPSrm, TB_ALIGN_16 }, 867 { X86::VHSUBPDrr, X86::VHSUBPDrm, TB_ALIGN_16 }, 868 { X86::VHSUBPSrr, X86::VHSUBPSrm, TB_ALIGN_16 }, 869 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 }, 870 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 }, 871 { X86::VMAXPDrr, X86::VMAXPDrm, TB_ALIGN_16 }, 872 { X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, TB_ALIGN_16 }, 873 { X86::VMAXPSrr, X86::VMAXPSrm, TB_ALIGN_16 }, 874 { X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, TB_ALIGN_16 }, 875 { X86::VMAXSDrr, X86::VMAXSDrm, 0 }, 876 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 }, 877 { X86::VMAXSSrr, X86::VMAXSSrm, 0 }, 878 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 }, 879 { X86::VMINPDrr, X86::VMINPDrm, TB_ALIGN_16 }, 880 { X86::VMINPDrr_Int, X86::VMINPDrm_Int, TB_ALIGN_16 }, 881 { X86::VMINPSrr, X86::VMINPSrm, TB_ALIGN_16 }, 882 { X86::VMINPSrr_Int, X86::VMINPSrm_Int, TB_ALIGN_16 }, 883 { X86::VMINSDrr, X86::VMINSDrm, 0 }, 884 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 }, 885 { X86::VMINSSrr, X86::VMINSSrm, 0 }, 886 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 }, 887 { X86::VMPSADBWrri, X86::VMPSADBWrmi, TB_ALIGN_16 }, 888 { X86::VMULPDrr, X86::VMULPDrm, TB_ALIGN_16 }, 889 { X86::VMULPSrr, X86::VMULPSrm, TB_ALIGN_16 }, 890 { X86::VMULSDrr, X86::VMULSDrm, 0 }, 891 { X86::VMULSSrr, X86::VMULSSrm, 0 }, 892 { X86::VORPDrr, X86::VORPDrm, TB_ALIGN_16 }, 893 { X86::VORPSrr, X86::VORPSrm, TB_ALIGN_16 }, 894 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, TB_ALIGN_16 }, 895 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, TB_ALIGN_16 }, 896 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, TB_ALIGN_16 }, 897 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, TB_ALIGN_16 }, 898 { X86::VPADDBrr, X86::VPADDBrm, TB_ALIGN_16 }, 899 { X86::VPADDDrr, X86::VPADDDrm, TB_ALIGN_16 }, 900 { X86::VPADDQrr, X86::VPADDQrm, TB_ALIGN_16 }, 901 { X86::VPADDSBrr, X86::VPADDSBrm, TB_ALIGN_16 }, 902 { X86::VPADDSWrr, X86::VPADDSWrm, TB_ALIGN_16 }, 903 { X86::VPADDUSBrr, X86::VPADDUSBrm, TB_ALIGN_16 }, 904 { X86::VPADDUSWrr, X86::VPADDUSWrm, TB_ALIGN_16 }, 905 { X86::VPADDWrr, X86::VPADDWrm, TB_ALIGN_16 }, 906 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, TB_ALIGN_16 }, 907 { X86::VPANDNrr, X86::VPANDNrm, TB_ALIGN_16 }, 908 { X86::VPANDrr, X86::VPANDrm, TB_ALIGN_16 }, 909 { X86::VPAVGBrr, X86::VPAVGBrm, TB_ALIGN_16 }, 910 { X86::VPAVGWrr, X86::VPAVGWrm, TB_ALIGN_16 }, 911 { X86::VPBLENDWrri, X86::VPBLENDWrmi, TB_ALIGN_16 }, 912 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, TB_ALIGN_16 }, 913 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, TB_ALIGN_16 }, 914 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, TB_ALIGN_16 }, 915 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, TB_ALIGN_16 }, 916 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, TB_ALIGN_16 }, 917 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, TB_ALIGN_16 }, 918 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, TB_ALIGN_16 }, 919 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, TB_ALIGN_16 }, 920 { X86::VPHADDDrr, X86::VPHADDDrm, TB_ALIGN_16 }, 921 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, TB_ALIGN_16 }, 922 { X86::VPHADDWrr, X86::VPHADDWrm, TB_ALIGN_16 }, 923 { X86::VPHSUBDrr, X86::VPHSUBDrm, TB_ALIGN_16 }, 924 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, TB_ALIGN_16 }, 925 { X86::VPHSUBWrr, X86::VPHSUBWrm, TB_ALIGN_16 }, 926 { X86::VPERMILPDrr, X86::VPERMILPDrm, TB_ALIGN_16 }, 927 { X86::VPERMILPSrr, X86::VPERMILPSrm, TB_ALIGN_16 }, 928 { X86::VPINSRWrri, X86::VPINSRWrmi, TB_ALIGN_16 }, 929 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, TB_ALIGN_16 }, 930 { X86::VPMADDWDrr, X86::VPMADDWDrm, TB_ALIGN_16 }, 931 { X86::VPMAXSWrr, X86::VPMAXSWrm, TB_ALIGN_16 }, 932 { X86::VPMAXUBrr, X86::VPMAXUBrm, TB_ALIGN_16 }, 933 { X86::VPMINSWrr, X86::VPMINSWrm, TB_ALIGN_16 }, 934 { X86::VPMINUBrr, X86::VPMINUBrm, TB_ALIGN_16 }, 935 { X86::VPMULDQrr, X86::VPMULDQrm, TB_ALIGN_16 }, 936 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, TB_ALIGN_16 }, 937 { X86::VPMULHUWrr, X86::VPMULHUWrm, TB_ALIGN_16 }, 938 { X86::VPMULHWrr, X86::VPMULHWrm, TB_ALIGN_16 }, 939 { X86::VPMULLDrr, X86::VPMULLDrm, TB_ALIGN_16 }, 940 { X86::VPMULLWrr, X86::VPMULLWrm, TB_ALIGN_16 }, 941 { X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 }, 942 { X86::VPORrr, X86::VPORrm, TB_ALIGN_16 }, 943 { X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 }, 944 { X86::VPSHUFBrr, X86::VPSHUFBrm, TB_ALIGN_16 }, 945 { X86::VPSIGNBrr, X86::VPSIGNBrm, TB_ALIGN_16 }, 946 { X86::VPSIGNWrr, X86::VPSIGNWrm, TB_ALIGN_16 }, 947 { X86::VPSIGNDrr, X86::VPSIGNDrm, TB_ALIGN_16 }, 948 { X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 }, 949 { X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 }, 950 { X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 }, 951 { X86::VPSRADrr, X86::VPSRADrm, TB_ALIGN_16 }, 952 { X86::VPSRAWrr, X86::VPSRAWrm, TB_ALIGN_16 }, 953 { X86::VPSRLDrr, X86::VPSRLDrm, TB_ALIGN_16 }, 954 { X86::VPSRLQrr, X86::VPSRLQrm, TB_ALIGN_16 }, 955 { X86::VPSRLWrr, X86::VPSRLWrm, TB_ALIGN_16 }, 956 { X86::VPSUBBrr, X86::VPSUBBrm, TB_ALIGN_16 }, 957 { X86::VPSUBDrr, X86::VPSUBDrm, TB_ALIGN_16 }, 958 { X86::VPSUBSBrr, X86::VPSUBSBrm, TB_ALIGN_16 }, 959 { X86::VPSUBSWrr, X86::VPSUBSWrm, TB_ALIGN_16 }, 960 { X86::VPSUBWrr, X86::VPSUBWrm, TB_ALIGN_16 }, 961 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, TB_ALIGN_16 }, 962 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, TB_ALIGN_16 }, 963 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, TB_ALIGN_16 }, 964 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, TB_ALIGN_16 }, 965 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, TB_ALIGN_16 }, 966 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, TB_ALIGN_16 }, 967 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, TB_ALIGN_16 }, 968 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, TB_ALIGN_16 }, 969 { X86::VPXORrr, X86::VPXORrm, TB_ALIGN_16 }, 970 { X86::VSHUFPDrri, X86::VSHUFPDrmi, TB_ALIGN_16 }, 971 { X86::VSHUFPSrri, X86::VSHUFPSrmi, TB_ALIGN_16 }, 972 { X86::VSUBPDrr, X86::VSUBPDrm, TB_ALIGN_16 }, 973 { X86::VSUBPSrr, X86::VSUBPSrm, TB_ALIGN_16 }, 974 { X86::VSUBSDrr, X86::VSUBSDrm, 0 }, 975 { X86::VSUBSSrr, X86::VSUBSSrm, 0 }, 976 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, TB_ALIGN_16 }, 977 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, TB_ALIGN_16 }, 978 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, TB_ALIGN_16 }, 979 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, TB_ALIGN_16 }, 980 { X86::VXORPDrr, X86::VXORPDrm, TB_ALIGN_16 }, 981 { X86::VXORPSrr, X86::VXORPSrm, TB_ALIGN_16 }, 982 // AVX 256-bit foldable instructions 983 { X86::VADDPDYrr, X86::VADDPDYrm, TB_ALIGN_32 }, 984 { X86::VADDPSYrr, X86::VADDPSYrm, TB_ALIGN_32 }, 985 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, TB_ALIGN_32 }, 986 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, TB_ALIGN_32 }, 987 { X86::VANDNPDYrr, X86::VANDNPDYrm, TB_ALIGN_32 }, 988 { X86::VANDNPSYrr, X86::VANDNPSYrm, TB_ALIGN_32 }, 989 { X86::VANDPDYrr, X86::VANDPDYrm, TB_ALIGN_32 }, 990 { X86::VANDPSYrr, X86::VANDPSYrm, TB_ALIGN_32 }, 991 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, TB_ALIGN_32 }, 992 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, TB_ALIGN_32 }, 993 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, TB_ALIGN_32 }, 994 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, TB_ALIGN_32 }, 995 { X86::VCMPPDYrri, X86::VCMPPDYrmi, TB_ALIGN_32 }, 996 { X86::VCMPPSYrri, X86::VCMPPSYrmi, TB_ALIGN_32 }, 997 { X86::VDIVPDYrr, X86::VDIVPDYrm, TB_ALIGN_32 }, 998 { X86::VDIVPSYrr, X86::VDIVPSYrm, TB_ALIGN_32 }, 999 { X86::VHADDPDYrr, X86::VHADDPDYrm, TB_ALIGN_32 }, 1000 { X86::VHADDPSYrr, X86::VHADDPSYrm, TB_ALIGN_32 }, 1001 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, TB_ALIGN_32 }, 1002 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, TB_ALIGN_32 }, 1003 { X86::VINSERTF128rr, X86::VINSERTF128rm, TB_ALIGN_32 }, 1004 { X86::VMAXPDYrr, X86::VMAXPDYrm, TB_ALIGN_32 }, 1005 { X86::VMAXPDYrr_Int, X86::VMAXPDYrm_Int, TB_ALIGN_32 }, 1006 { X86::VMAXPSYrr, X86::VMAXPSYrm, TB_ALIGN_32 }, 1007 { X86::VMAXPSYrr_Int, X86::VMAXPSYrm_Int, TB_ALIGN_32 }, 1008 { X86::VMINPDYrr, X86::VMINPDYrm, TB_ALIGN_32 }, 1009 { X86::VMINPDYrr_Int, X86::VMINPDYrm_Int, TB_ALIGN_32 }, 1010 { X86::VMINPSYrr, X86::VMINPSYrm, TB_ALIGN_32 }, 1011 { X86::VMINPSYrr_Int, X86::VMINPSYrm_Int, TB_ALIGN_32 }, 1012 { X86::VMULPDYrr, X86::VMULPDYrm, TB_ALIGN_32 }, 1013 { X86::VMULPSYrr, X86::VMULPSYrm, TB_ALIGN_32 }, 1014 { X86::VORPDYrr, X86::VORPDYrm, TB_ALIGN_32 }, 1015 { X86::VORPSYrr, X86::VORPSYrm, TB_ALIGN_32 }, 1016 { X86::VPERM2F128rr, X86::VPERM2F128rm, TB_ALIGN_32 }, 1017 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, TB_ALIGN_32 }, 1018 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, TB_ALIGN_32 }, 1019 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, TB_ALIGN_32 }, 1020 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, TB_ALIGN_32 }, 1021 { X86::VSUBPDYrr, X86::VSUBPDYrm, TB_ALIGN_32 }, 1022 { X86::VSUBPSYrr, X86::VSUBPSYrm, TB_ALIGN_32 }, 1023 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, TB_ALIGN_32 }, 1024 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, TB_ALIGN_32 }, 1025 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, TB_ALIGN_32 }, 1026 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, TB_ALIGN_32 }, 1027 { X86::VXORPDYrr, X86::VXORPDYrm, TB_ALIGN_32 }, 1028 { X86::VXORPSYrr, X86::VXORPSYrm, TB_ALIGN_32 }, 1029 // AVX2 foldable instructions 1030 { X86::VINSERTI128rr, X86::VINSERTI128rm, TB_ALIGN_16 }, 1031 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, TB_ALIGN_32 }, 1032 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, TB_ALIGN_32 }, 1033 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, TB_ALIGN_32 }, 1034 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, TB_ALIGN_32 }, 1035 { X86::VPADDBYrr, X86::VPADDBYrm, TB_ALIGN_32 }, 1036 { X86::VPADDDYrr, X86::VPADDDYrm, TB_ALIGN_32 }, 1037 { X86::VPADDQYrr, X86::VPADDQYrm, TB_ALIGN_32 }, 1038 { X86::VPADDSBYrr, X86::VPADDSBYrm, TB_ALIGN_32 }, 1039 { X86::VPADDSWYrr, X86::VPADDSWYrm, TB_ALIGN_32 }, 1040 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, TB_ALIGN_32 }, 1041 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, TB_ALIGN_32 }, 1042 { X86::VPADDWYrr, X86::VPADDWYrm, TB_ALIGN_32 }, 1043 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, TB_ALIGN_32 }, 1044 { X86::VPANDNYrr, X86::VPANDNYrm, TB_ALIGN_32 }, 1045 { X86::VPANDYrr, X86::VPANDYrm, TB_ALIGN_32 }, 1046 { X86::VPAVGBYrr, X86::VPAVGBYrm, TB_ALIGN_32 }, 1047 { X86::VPAVGWYrr, X86::VPAVGWYrm, TB_ALIGN_32 }, 1048 { X86::VPBLENDDrri, X86::VPBLENDDrmi, TB_ALIGN_32 }, 1049 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, TB_ALIGN_32 }, 1050 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, TB_ALIGN_32 }, 1051 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, TB_ALIGN_32 }, 1052 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, TB_ALIGN_32 }, 1053 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, TB_ALIGN_32 }, 1054 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, TB_ALIGN_32 }, 1055 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, TB_ALIGN_32 }, 1056 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, TB_ALIGN_32 }, 1057 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, TB_ALIGN_32 }, 1058 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, TB_ALIGN_32 }, 1059 { X86::VPERM2I128rr, X86::VPERM2I128rm, TB_ALIGN_32 }, 1060 { X86::VPERMDYrr, X86::VPERMDYrm, TB_ALIGN_32 }, 1061 { X86::VPERMPDYri, X86::VPERMPDYmi, TB_ALIGN_32 }, 1062 { X86::VPERMPSYrr, X86::VPERMPSYrm, TB_ALIGN_32 }, 1063 { X86::VPERMQYri, X86::VPERMQYmi, TB_ALIGN_32 }, 1064 { X86::VPHADDDYrr, X86::VPHADDDYrm, TB_ALIGN_32 }, 1065 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, TB_ALIGN_32 }, 1066 { X86::VPHADDWYrr, X86::VPHADDWYrm, TB_ALIGN_32 }, 1067 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, TB_ALIGN_32 }, 1068 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, TB_ALIGN_32 }, 1069 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, TB_ALIGN_32 }, 1070 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, TB_ALIGN_32 }, 1071 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, TB_ALIGN_32 }, 1072 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, TB_ALIGN_32 }, 1073 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, TB_ALIGN_32 }, 1074 { X86::VPMINSWYrr, X86::VPMINSWYrm, TB_ALIGN_32 }, 1075 { X86::VPMINUBYrr, X86::VPMINUBYrm, TB_ALIGN_32 }, 1076 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, TB_ALIGN_32 }, 1077 { X86::VPMULDQYrr, X86::VPMULDQYrm, TB_ALIGN_32 }, 1078 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, TB_ALIGN_32 }, 1079 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, TB_ALIGN_32 }, 1080 { X86::VPMULHWYrr, X86::VPMULHWYrm, TB_ALIGN_32 }, 1081 { X86::VPMULLDYrr, X86::VPMULLDYrm, TB_ALIGN_32 }, 1082 { X86::VPMULLWYrr, X86::VPMULLWYrm, TB_ALIGN_32 }, 1083 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, TB_ALIGN_32 }, 1084 { X86::VPORYrr, X86::VPORYrm, TB_ALIGN_32 }, 1085 { X86::VPSADBWYrr, X86::VPSADBWYrm, TB_ALIGN_32 }, 1086 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, TB_ALIGN_32 }, 1087 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, TB_ALIGN_32 }, 1088 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, TB_ALIGN_32 }, 1089 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, TB_ALIGN_32 }, 1090 { X86::VPSLLDYrr, X86::VPSLLDYrm, TB_ALIGN_16 }, 1091 { X86::VPSLLQYrr, X86::VPSLLQYrm, TB_ALIGN_16 }, 1092 { X86::VPSLLWYrr, X86::VPSLLWYrm, TB_ALIGN_16 }, 1093 { X86::VPSLLVDrr, X86::VPSLLVDrm, TB_ALIGN_16 }, 1094 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, TB_ALIGN_32 }, 1095 { X86::VPSLLVQrr, X86::VPSLLVQrm, TB_ALIGN_16 }, 1096 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, TB_ALIGN_32 }, 1097 { X86::VPSRADYrr, X86::VPSRADYrm, TB_ALIGN_16 }, 1098 { X86::VPSRAWYrr, X86::VPSRAWYrm, TB_ALIGN_16 }, 1099 { X86::VPSRAVDrr, X86::VPSRAVDrm, TB_ALIGN_16 }, 1100 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, TB_ALIGN_32 }, 1101 { X86::VPSRLDYrr, X86::VPSRLDYrm, TB_ALIGN_16 }, 1102 { X86::VPSRLQYrr, X86::VPSRLQYrm, TB_ALIGN_16 }, 1103 { X86::VPSRLWYrr, X86::VPSRLWYrm, TB_ALIGN_16 }, 1104 { X86::VPSRLVDrr, X86::VPSRLVDrm, TB_ALIGN_16 }, 1105 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, TB_ALIGN_32 }, 1106 { X86::VPSRLVQrr, X86::VPSRLVQrm, TB_ALIGN_16 }, 1107 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, TB_ALIGN_32 }, 1108 { X86::VPSUBBYrr, X86::VPSUBBYrm, TB_ALIGN_32 }, 1109 { X86::VPSUBDYrr, X86::VPSUBDYrm, TB_ALIGN_32 }, 1110 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, TB_ALIGN_32 }, 1111 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, TB_ALIGN_32 }, 1112 { X86::VPSUBWYrr, X86::VPSUBWYrm, TB_ALIGN_32 }, 1113 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, TB_ALIGN_32 }, 1114 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, TB_ALIGN_32 }, 1115 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, TB_ALIGN_16 }, 1116 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, TB_ALIGN_32 }, 1117 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, TB_ALIGN_32 }, 1118 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, TB_ALIGN_32 }, 1119 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, TB_ALIGN_32 }, 1120 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, TB_ALIGN_32 }, 1121 { X86::VPXORYrr, X86::VPXORYrm, TB_ALIGN_32 }, 1122 // FIXME: add AVX 256-bit foldable instructions 1123 1124 // FMA4 foldable patterns 1125 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_16 }, 1126 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_16 }, 1127 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_16 }, 1128 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_16 }, 1129 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_32 }, 1130 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_32 }, 1131 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_16 }, 1132 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_16 }, 1133 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_32 }, 1134 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_32 }, 1135 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_16 }, 1136 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_16 }, 1137 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_16 }, 1138 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_16 }, 1139 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_32 }, 1140 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_32 }, 1141 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_16 }, 1142 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_16 }, 1143 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_32 }, 1144 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_32 }, 1145 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_16 }, 1146 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_16 }, 1147 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_32 }, 1148 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_32 }, 1149 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_16 }, 1150 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_16 }, 1151 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_32 }, 1152 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_32 }, 1153 1154 // BMI/BMI2 foldable instructions 1155 { X86::MULX32rr, X86::MULX32rm, 0 }, 1156 { X86::MULX64rr, X86::MULX64rm, 0 }, 1157 }; 1158 1159 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 1160 unsigned RegOp = OpTbl2[i].RegOp; 1161 unsigned MemOp = OpTbl2[i].MemOp; 1162 unsigned Flags = OpTbl2[i].Flags; 1163 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable, 1164 RegOp, MemOp, 1165 // Index 2, folded load 1166 Flags | TB_INDEX_2 | TB_FOLDED_LOAD); 1167 } 1168 1169 static const X86OpTblEntry OpTbl3[] = { 1170 // FMA foldable instructions 1171 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, 0 }, 1172 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, 0 }, 1173 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, 0 }, 1174 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, 0 }, 1175 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, 0 }, 1176 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, 0 }, 1177 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, 0 }, 1178 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, 0 }, 1179 1180 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_16 }, 1181 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_16 }, 1182 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_16 }, 1183 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_16 }, 1184 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_16 }, 1185 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_16 }, 1186 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_32 }, 1187 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_32 }, 1188 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_32 }, 1189 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_32 }, 1190 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_32 }, 1191 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_32 }, 1192 1193 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, 0 }, 1194 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, 0 }, 1195 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, 0 }, 1196 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, 0 }, 1197 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, 0 }, 1198 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, 0 }, 1199 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, 0 }, 1200 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, 0 }, 1201 1202 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_16 }, 1203 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_16 }, 1204 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_16 }, 1205 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_16 }, 1206 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_16 }, 1207 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_16 }, 1208 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_32 }, 1209 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_32 }, 1210 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_32 }, 1211 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_32 }, 1212 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_32 }, 1213 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_32 }, 1214 1215 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, 0 }, 1216 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, 0 }, 1217 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, 0 }, 1218 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, 0 }, 1219 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, 0 }, 1220 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, 0 }, 1221 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, 0 }, 1222 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, 0 }, 1223 1224 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_16 }, 1225 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_16 }, 1226 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_16 }, 1227 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_16 }, 1228 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_16 }, 1229 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_16 }, 1230 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_32 }, 1231 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_32 }, 1232 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_32 }, 1233 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_32 }, 1234 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_32 }, 1235 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_32 }, 1236 1237 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, 0 }, 1238 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, 0 }, 1239 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, 0 }, 1240 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, 0 }, 1241 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, 0 }, 1242 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, 0 }, 1243 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, 0 }, 1244 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, 0 }, 1245 1246 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_16 }, 1247 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_16 }, 1248 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_16 }, 1249 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_16 }, 1250 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_16 }, 1251 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_16 }, 1252 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_32 }, 1253 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_32 }, 1254 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_32 }, 1255 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_32 }, 1256 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_32 }, 1257 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_32 }, 1258 1259 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_16 }, 1260 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_16 }, 1261 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_16 }, 1262 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_16 }, 1263 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_16 }, 1264 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_16 }, 1265 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_32 }, 1266 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_32 }, 1267 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_32 }, 1268 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_32 }, 1269 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_32 }, 1270 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_32 }, 1271 1272 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_16 }, 1273 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_16 }, 1274 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_16 }, 1275 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_16 }, 1276 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_16 }, 1277 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_16 }, 1278 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_32 }, 1279 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_32 }, 1280 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_32 }, 1281 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_32 }, 1282 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_32 }, 1283 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_32 }, 1284 1285 // FMA4 foldable patterns 1286 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_16 }, 1287 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_16 }, 1288 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_16 }, 1289 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_16 }, 1290 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_32 }, 1291 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_32 }, 1292 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_16 }, 1293 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_16 }, 1294 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_32 }, 1295 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_32 }, 1296 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_16 }, 1297 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_16 }, 1298 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_16 }, 1299 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_16 }, 1300 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_32 }, 1301 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_32 }, 1302 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_16 }, 1303 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_16 }, 1304 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_32 }, 1305 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_32 }, 1306 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_16 }, 1307 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_16 }, 1308 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_32 }, 1309 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_32 }, 1310 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_16 }, 1311 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_16 }, 1312 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_32 }, 1313 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_32 }, 1314 }; 1315 1316 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) { 1317 unsigned RegOp = OpTbl3[i].RegOp; 1318 unsigned MemOp = OpTbl3[i].MemOp; 1319 unsigned Flags = OpTbl3[i].Flags; 1320 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable, 1321 RegOp, MemOp, 1322 // Index 3, folded load 1323 Flags | TB_INDEX_3 | TB_FOLDED_LOAD); 1324 } 1325 1326} 1327 1328void 1329X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable, 1330 MemOp2RegOpTableType &M2RTable, 1331 unsigned RegOp, unsigned MemOp, unsigned Flags) { 1332 if ((Flags & TB_NO_FORWARD) == 0) { 1333 assert(!R2MTable.count(RegOp) && "Duplicate entry!"); 1334 R2MTable[RegOp] = std::make_pair(MemOp, Flags); 1335 } 1336 if ((Flags & TB_NO_REVERSE) == 0) { 1337 assert(!M2RTable.count(MemOp) && 1338 "Duplicated entries in unfolding maps?"); 1339 M2RTable[MemOp] = std::make_pair(RegOp, Flags); 1340 } 1341} 1342 1343bool 1344X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 1345 unsigned &SrcReg, unsigned &DstReg, 1346 unsigned &SubIdx) const { 1347 switch (MI.getOpcode()) { 1348 default: break; 1349 case X86::MOVSX16rr8: 1350 case X86::MOVZX16rr8: 1351 case X86::MOVSX32rr8: 1352 case X86::MOVZX32rr8: 1353 case X86::MOVSX64rr8: 1354 case X86::MOVZX64rr8: 1355 if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 1356 // It's not always legal to reference the low 8-bit of the larger 1357 // register in 32-bit mode. 1358 return false; 1359 case X86::MOVSX32rr16: 1360 case X86::MOVZX32rr16: 1361 case X86::MOVSX64rr16: 1362 case X86::MOVZX64rr16: 1363 case X86::MOVSX64rr32: 1364 case X86::MOVZX64rr32: { 1365 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 1366 // Be conservative. 1367 return false; 1368 SrcReg = MI.getOperand(1).getReg(); 1369 DstReg = MI.getOperand(0).getReg(); 1370 switch (MI.getOpcode()) { 1371 default: llvm_unreachable("Unreachable!"); 1372 case X86::MOVSX16rr8: 1373 case X86::MOVZX16rr8: 1374 case X86::MOVSX32rr8: 1375 case X86::MOVZX32rr8: 1376 case X86::MOVSX64rr8: 1377 case X86::MOVZX64rr8: 1378 SubIdx = X86::sub_8bit; 1379 break; 1380 case X86::MOVSX32rr16: 1381 case X86::MOVZX32rr16: 1382 case X86::MOVSX64rr16: 1383 case X86::MOVZX64rr16: 1384 SubIdx = X86::sub_16bit; 1385 break; 1386 case X86::MOVSX64rr32: 1387 case X86::MOVZX64rr32: 1388 SubIdx = X86::sub_32bit; 1389 break; 1390 } 1391 return true; 1392 } 1393 } 1394 return false; 1395} 1396 1397/// isFrameOperand - Return true and the FrameIndex if the specified 1398/// operand and follow operands form a reference to the stack frame. 1399bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 1400 int &FrameIndex) const { 1401 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() && 1402 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() && 1403 MI->getOperand(Op+1).getImm() == 1 && 1404 MI->getOperand(Op+2).getReg() == 0 && 1405 MI->getOperand(Op+3).getImm() == 0) { 1406 FrameIndex = MI->getOperand(Op).getIndex(); 1407 return true; 1408 } 1409 return false; 1410} 1411 1412static bool isFrameLoadOpcode(int Opcode) { 1413 switch (Opcode) { 1414 default: 1415 return false; 1416 case X86::MOV8rm: 1417 case X86::MOV16rm: 1418 case X86::MOV32rm: 1419 case X86::MOV64rm: 1420 case X86::LD_Fp64m: 1421 case X86::MOVSSrm: 1422 case X86::MOVSDrm: 1423 case X86::MOVAPSrm: 1424 case X86::MOVAPDrm: 1425 case X86::MOVDQArm: 1426 case X86::VMOVSSrm: 1427 case X86::VMOVSDrm: 1428 case X86::VMOVAPSrm: 1429 case X86::VMOVAPDrm: 1430 case X86::VMOVDQArm: 1431 case X86::VMOVAPSYrm: 1432 case X86::VMOVAPDYrm: 1433 case X86::VMOVDQAYrm: 1434 case X86::MMX_MOVD64rm: 1435 case X86::MMX_MOVQ64rm: 1436 return true; 1437 } 1438} 1439 1440static bool isFrameStoreOpcode(int Opcode) { 1441 switch (Opcode) { 1442 default: break; 1443 case X86::MOV8mr: 1444 case X86::MOV16mr: 1445 case X86::MOV32mr: 1446 case X86::MOV64mr: 1447 case X86::ST_FpP64m: 1448 case X86::MOVSSmr: 1449 case X86::MOVSDmr: 1450 case X86::MOVAPSmr: 1451 case X86::MOVAPDmr: 1452 case X86::MOVDQAmr: 1453 case X86::VMOVSSmr: 1454 case X86::VMOVSDmr: 1455 case X86::VMOVAPSmr: 1456 case X86::VMOVAPDmr: 1457 case X86::VMOVDQAmr: 1458 case X86::VMOVAPSYmr: 1459 case X86::VMOVAPDYmr: 1460 case X86::VMOVDQAYmr: 1461 case X86::MMX_MOVD64mr: 1462 case X86::MMX_MOVQ64mr: 1463 case X86::MMX_MOVNTQmr: 1464 return true; 1465 } 1466 return false; 1467} 1468 1469unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 1470 int &FrameIndex) const { 1471 if (isFrameLoadOpcode(MI->getOpcode())) 1472 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) 1473 return MI->getOperand(0).getReg(); 1474 return 0; 1475} 1476 1477unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 1478 int &FrameIndex) const { 1479 if (isFrameLoadOpcode(MI->getOpcode())) { 1480 unsigned Reg; 1481 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 1482 return Reg; 1483 // Check for post-frame index elimination operations 1484 const MachineMemOperand *Dummy; 1485 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 1486 } 1487 return 0; 1488} 1489 1490unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 1491 int &FrameIndex) const { 1492 if (isFrameStoreOpcode(MI->getOpcode())) 1493 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 && 1494 isFrameOperand(MI, 0, FrameIndex)) 1495 return MI->getOperand(X86::AddrNumOperands).getReg(); 1496 return 0; 1497} 1498 1499unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 1500 int &FrameIndex) const { 1501 if (isFrameStoreOpcode(MI->getOpcode())) { 1502 unsigned Reg; 1503 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 1504 return Reg; 1505 // Check for post-frame index elimination operations 1506 const MachineMemOperand *Dummy; 1507 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 1508 } 1509 return 0; 1510} 1511 1512/// regIsPICBase - Return true if register is PIC base (i.e.g defined by 1513/// X86::MOVPC32r. 1514static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 1515 // Don't waste compile time scanning use-def chains of physregs. 1516 if (!TargetRegisterInfo::isVirtualRegister(BaseReg)) 1517 return false; 1518 bool isPICBase = false; 1519 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 1520 E = MRI.def_end(); I != E; ++I) { 1521 MachineInstr *DefMI = I.getOperand().getParent(); 1522 if (DefMI->getOpcode() != X86::MOVPC32r) 1523 return false; 1524 assert(!isPICBase && "More than one PIC base?"); 1525 isPICBase = true; 1526 } 1527 return isPICBase; 1528} 1529 1530bool 1531X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 1532 AliasAnalysis *AA) const { 1533 switch (MI->getOpcode()) { 1534 default: break; 1535 case X86::MOV8rm: 1536 case X86::MOV16rm: 1537 case X86::MOV32rm: 1538 case X86::MOV64rm: 1539 case X86::LD_Fp64m: 1540 case X86::MOVSSrm: 1541 case X86::MOVSDrm: 1542 case X86::MOVAPSrm: 1543 case X86::MOVUPSrm: 1544 case X86::MOVAPDrm: 1545 case X86::MOVDQArm: 1546 case X86::VMOVSSrm: 1547 case X86::VMOVSDrm: 1548 case X86::VMOVAPSrm: 1549 case X86::VMOVUPSrm: 1550 case X86::VMOVAPDrm: 1551 case X86::VMOVDQArm: 1552 case X86::VMOVAPSYrm: 1553 case X86::VMOVUPSYrm: 1554 case X86::VMOVAPDYrm: 1555 case X86::VMOVDQAYrm: 1556 case X86::MMX_MOVD64rm: 1557 case X86::MMX_MOVQ64rm: 1558 case X86::FsVMOVAPSrm: 1559 case X86::FsVMOVAPDrm: 1560 case X86::FsMOVAPSrm: 1561 case X86::FsMOVAPDrm: { 1562 // Loads from constant pools are trivially rematerializable. 1563 if (MI->getOperand(1).isReg() && 1564 MI->getOperand(2).isImm() && 1565 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 1566 MI->isInvariantLoad(AA)) { 1567 unsigned BaseReg = MI->getOperand(1).getReg(); 1568 if (BaseReg == 0 || BaseReg == X86::RIP) 1569 return true; 1570 // Allow re-materialization of PIC load. 1571 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 1572 return false; 1573 const MachineFunction &MF = *MI->getParent()->getParent(); 1574 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1575 return regIsPICBase(BaseReg, MRI); 1576 } 1577 return false; 1578 } 1579 1580 case X86::LEA32r: 1581 case X86::LEA64r: { 1582 if (MI->getOperand(2).isImm() && 1583 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 1584 !MI->getOperand(4).isReg()) { 1585 // lea fi#, lea GV, etc. are all rematerializable. 1586 if (!MI->getOperand(1).isReg()) 1587 return true; 1588 unsigned BaseReg = MI->getOperand(1).getReg(); 1589 if (BaseReg == 0) 1590 return true; 1591 // Allow re-materialization of lea PICBase + x. 1592 const MachineFunction &MF = *MI->getParent()->getParent(); 1593 const MachineRegisterInfo &MRI = MF.getRegInfo(); 1594 return regIsPICBase(BaseReg, MRI); 1595 } 1596 return false; 1597 } 1598 } 1599 1600 // All other instructions marked M_REMATERIALIZABLE are always trivially 1601 // rematerializable. 1602 return true; 1603} 1604 1605/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 1606/// would clobber the EFLAGS condition register. Note the result may be 1607/// conservative. If it cannot definitely determine the safety after visiting 1608/// a few instructions in each direction it assumes it's not safe. 1609static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 1610 MachineBasicBlock::iterator I) { 1611 MachineBasicBlock::iterator E = MBB.end(); 1612 1613 // For compile time consideration, if we are not able to determine the 1614 // safety after visiting 4 instructions in each direction, we will assume 1615 // it's not safe. 1616 MachineBasicBlock::iterator Iter = I; 1617 for (unsigned i = 0; Iter != E && i < 4; ++i) { 1618 bool SeenDef = false; 1619 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1620 MachineOperand &MO = Iter->getOperand(j); 1621 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1622 SeenDef = true; 1623 if (!MO.isReg()) 1624 continue; 1625 if (MO.getReg() == X86::EFLAGS) { 1626 if (MO.isUse()) 1627 return false; 1628 SeenDef = true; 1629 } 1630 } 1631 1632 if (SeenDef) 1633 // This instruction defines EFLAGS, no need to look any further. 1634 return true; 1635 ++Iter; 1636 // Skip over DBG_VALUE. 1637 while (Iter != E && Iter->isDebugValue()) 1638 ++Iter; 1639 } 1640 1641 // It is safe to clobber EFLAGS at the end of a block of no successor has it 1642 // live in. 1643 if (Iter == E) { 1644 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(), 1645 SE = MBB.succ_end(); SI != SE; ++SI) 1646 if ((*SI)->isLiveIn(X86::EFLAGS)) 1647 return false; 1648 return true; 1649 } 1650 1651 MachineBasicBlock::iterator B = MBB.begin(); 1652 Iter = I; 1653 for (unsigned i = 0; i < 4; ++i) { 1654 // If we make it to the beginning of the block, it's safe to clobber 1655 // EFLAGS iff EFLAGS is not live-in. 1656 if (Iter == B) 1657 return !MBB.isLiveIn(X86::EFLAGS); 1658 1659 --Iter; 1660 // Skip over DBG_VALUE. 1661 while (Iter != B && Iter->isDebugValue()) 1662 --Iter; 1663 1664 bool SawKill = false; 1665 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1666 MachineOperand &MO = Iter->getOperand(j); 1667 // A register mask may clobber EFLAGS, but we should still look for a 1668 // live EFLAGS def. 1669 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS)) 1670 SawKill = true; 1671 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1672 if (MO.isDef()) return MO.isDead(); 1673 if (MO.isKill()) SawKill = true; 1674 } 1675 } 1676 1677 if (SawKill) 1678 // This instruction kills EFLAGS and doesn't redefine it, so 1679 // there's no need to look further. 1680 return true; 1681 } 1682 1683 // Conservative answer. 1684 return false; 1685} 1686 1687void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1688 MachineBasicBlock::iterator I, 1689 unsigned DestReg, unsigned SubIdx, 1690 const MachineInstr *Orig, 1691 const TargetRegisterInfo &TRI) const { 1692 DebugLoc DL = Orig->getDebugLoc(); 1693 1694 // MOV32r0 etc. are implemented with xor which clobbers condition code. 1695 // Re-materialize them as movri instructions to avoid side effects. 1696 bool Clone = true; 1697 unsigned Opc = Orig->getOpcode(); 1698 switch (Opc) { 1699 default: break; 1700 case X86::MOV8r0: 1701 case X86::MOV16r0: 1702 case X86::MOV32r0: 1703 case X86::MOV64r0: { 1704 if (!isSafeToClobberEFLAGS(MBB, I)) { 1705 switch (Opc) { 1706 default: llvm_unreachable("Unreachable!"); 1707 case X86::MOV8r0: Opc = X86::MOV8ri; break; 1708 case X86::MOV16r0: Opc = X86::MOV16ri; break; 1709 case X86::MOV32r0: Opc = X86::MOV32ri; break; 1710 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break; 1711 } 1712 Clone = false; 1713 } 1714 break; 1715 } 1716 } 1717 1718 if (Clone) { 1719 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1720 MBB.insert(I, MI); 1721 } else { 1722 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0); 1723 } 1724 1725 MachineInstr *NewMI = prior(I); 1726 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1727} 1728 1729/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1730/// is not marked dead. 1731static bool hasLiveCondCodeDef(MachineInstr *MI) { 1732 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1733 MachineOperand &MO = MI->getOperand(i); 1734 if (MO.isReg() && MO.isDef() && 1735 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1736 return true; 1737 } 1738 } 1739 return false; 1740} 1741 1742/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1743/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1744/// to a 32-bit superregister and then truncating back down to a 16-bit 1745/// subregister. 1746MachineInstr * 1747X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1748 MachineFunction::iterator &MFI, 1749 MachineBasicBlock::iterator &MBBI, 1750 LiveVariables *LV) const { 1751 MachineInstr *MI = MBBI; 1752 unsigned Dest = MI->getOperand(0).getReg(); 1753 unsigned Src = MI->getOperand(1).getReg(); 1754 bool isDead = MI->getOperand(0).isDead(); 1755 bool isKill = MI->getOperand(1).isKill(); 1756 1757 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1758 ? X86::LEA64_32r : X86::LEA32r; 1759 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1760 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1761 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1762 1763 // Build and insert into an implicit UNDEF value. This is OK because 1764 // well be shifting and then extracting the lower 16-bits. 1765 // This has the potential to cause partial register stall. e.g. 1766 // movw (%rbp,%rcx,2), %dx 1767 // leal -65(%rdx), %esi 1768 // But testing has shown this *does* help performance in 64-bit mode (at 1769 // least on modern x86 machines). 1770 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1771 MachineInstr *InsMI = 1772 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1773 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1774 .addReg(Src, getKillRegState(isKill)); 1775 1776 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1777 get(Opc), leaOutReg); 1778 switch (MIOpc) { 1779 default: llvm_unreachable("Unreachable!"); 1780 case X86::SHL16ri: { 1781 unsigned ShAmt = MI->getOperand(2).getImm(); 1782 MIB.addReg(0).addImm(1 << ShAmt) 1783 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 1784 break; 1785 } 1786 case X86::INC16r: 1787 case X86::INC64_16r: 1788 addRegOffset(MIB, leaInReg, true, 1); 1789 break; 1790 case X86::DEC16r: 1791 case X86::DEC64_16r: 1792 addRegOffset(MIB, leaInReg, true, -1); 1793 break; 1794 case X86::ADD16ri: 1795 case X86::ADD16ri8: 1796 case X86::ADD16ri_DB: 1797 case X86::ADD16ri8_DB: 1798 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1799 break; 1800 case X86::ADD16rr: 1801 case X86::ADD16rr_DB: { 1802 unsigned Src2 = MI->getOperand(2).getReg(); 1803 bool isKill2 = MI->getOperand(2).isKill(); 1804 unsigned leaInReg2 = 0; 1805 MachineInstr *InsMI2 = 0; 1806 if (Src == Src2) { 1807 // ADD16rr %reg1028<kill>, %reg1028 1808 // just a single insert_subreg. 1809 addRegReg(MIB, leaInReg, true, leaInReg, false); 1810 } else { 1811 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1812 // Build and insert into an implicit UNDEF value. This is OK because 1813 // well be shifting and then extracting the lower 16-bits. 1814 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); 1815 InsMI2 = 1816 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1817 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 1818 .addReg(Src2, getKillRegState(isKill2)); 1819 addRegReg(MIB, leaInReg, true, leaInReg2, true); 1820 } 1821 if (LV && isKill2 && InsMI2) 1822 LV->replaceKillInstruction(Src2, MI, InsMI2); 1823 break; 1824 } 1825 } 1826 1827 MachineInstr *NewMI = MIB; 1828 MachineInstr *ExtMI = 1829 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1830 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1831 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 1832 1833 if (LV) { 1834 // Update live variables 1835 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1836 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1837 if (isKill) 1838 LV->replaceKillInstruction(Src, MI, InsMI); 1839 if (isDead) 1840 LV->replaceKillInstruction(Dest, MI, ExtMI); 1841 } 1842 1843 return ExtMI; 1844} 1845 1846/// convertToThreeAddress - This method must be implemented by targets that 1847/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1848/// may be able to convert a two-address instruction into a true 1849/// three-address instruction on demand. This allows the X86 target (for 1850/// example) to convert ADD and SHL instructions into LEA instructions if they 1851/// would require register copies due to two-addressness. 1852/// 1853/// This method returns a null pointer if the transformation cannot be 1854/// performed, otherwise it returns the new instruction. 1855/// 1856MachineInstr * 1857X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1858 MachineBasicBlock::iterator &MBBI, 1859 LiveVariables *LV) const { 1860 MachineInstr *MI = MBBI; 1861 MachineFunction &MF = *MI->getParent()->getParent(); 1862 // All instructions input are two-addr instructions. Get the known operands. 1863 const MachineOperand &Dest = MI->getOperand(0); 1864 const MachineOperand &Src = MI->getOperand(1); 1865 1866 MachineInstr *NewMI = NULL; 1867 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1868 // we have better subtarget support, enable the 16-bit LEA generation here. 1869 // 16-bit LEA is also slow on Core2. 1870 bool DisableLEA16 = true; 1871 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1872 1873 unsigned MIOpc = MI->getOpcode(); 1874 switch (MIOpc) { 1875 case X86::SHUFPSrri: { 1876 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1877 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1878 1879 unsigned B = MI->getOperand(1).getReg(); 1880 unsigned C = MI->getOperand(2).getReg(); 1881 if (B != C) return 0; 1882 unsigned M = MI->getOperand(3).getImm(); 1883 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1884 .addOperand(Dest).addOperand(Src).addImm(M); 1885 break; 1886 } 1887 case X86::SHUFPDrri: { 1888 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!"); 1889 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1890 1891 unsigned B = MI->getOperand(1).getReg(); 1892 unsigned C = MI->getOperand(2).getReg(); 1893 if (B != C) return 0; 1894 unsigned M = MI->getOperand(3).getImm(); 1895 1896 // Convert to PSHUFD mask. 1897 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44; 1898 1899 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1900 .addOperand(Dest).addOperand(Src).addImm(M); 1901 break; 1902 } 1903 case X86::SHL64ri: { 1904 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1905 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1906 // the flags produced by a shift yet, so this is safe. 1907 unsigned ShAmt = MI->getOperand(2).getImm(); 1908 if (ShAmt == 0 || ShAmt >= 4) return 0; 1909 1910 // LEA can't handle RSP. 1911 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 1912 !MF.getRegInfo().constrainRegClass(Src.getReg(), 1913 &X86::GR64_NOSPRegClass)) 1914 return 0; 1915 1916 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1917 .addOperand(Dest) 1918 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 1919 break; 1920 } 1921 case X86::SHL32ri: { 1922 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1923 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1924 // the flags produced by a shift yet, so this is safe. 1925 unsigned ShAmt = MI->getOperand(2).getImm(); 1926 if (ShAmt == 0 || ShAmt >= 4) return 0; 1927 1928 // LEA can't handle ESP. 1929 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 1930 !MF.getRegInfo().constrainRegClass(Src.getReg(), 1931 &X86::GR32_NOSPRegClass)) 1932 return 0; 1933 1934 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1935 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1936 .addOperand(Dest) 1937 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 1938 break; 1939 } 1940 case X86::SHL16ri: { 1941 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1942 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1943 // the flags produced by a shift yet, so this is safe. 1944 unsigned ShAmt = MI->getOperand(2).getImm(); 1945 if (ShAmt == 0 || ShAmt >= 4) return 0; 1946 1947 if (DisableLEA16) 1948 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1949 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1950 .addOperand(Dest) 1951 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0); 1952 break; 1953 } 1954 default: { 1955 // The following opcodes also sets the condition code register(s). Only 1956 // convert them to equivalent lea if the condition code register def's 1957 // are dead! 1958 if (hasLiveCondCodeDef(MI)) 1959 return 0; 1960 1961 switch (MIOpc) { 1962 default: return 0; 1963 case X86::INC64r: 1964 case X86::INC32r: 1965 case X86::INC64_32r: { 1966 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1967 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 1968 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1969 const TargetRegisterClass *RC = MIOpc == X86::INC64r ? 1970 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass : 1971 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass; 1972 1973 // LEA can't handle RSP. 1974 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 1975 !MF.getRegInfo().constrainRegClass(Src.getReg(), RC)) 1976 return 0; 1977 1978 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1979 .addOperand(Dest).addOperand(Src), 1); 1980 break; 1981 } 1982 case X86::INC16r: 1983 case X86::INC64_16r: 1984 if (DisableLEA16) 1985 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1986 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1987 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1988 .addOperand(Dest).addOperand(Src), 1); 1989 break; 1990 case X86::DEC64r: 1991 case X86::DEC32r: 1992 case X86::DEC64_32r: { 1993 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1994 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 1995 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1996 const TargetRegisterClass *RC = MIOpc == X86::DEC64r ? 1997 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass : 1998 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass; 1999 // LEA can't handle RSP. 2000 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) && 2001 !MF.getRegInfo().constrainRegClass(Src.getReg(), RC)) 2002 return 0; 2003 2004 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2005 .addOperand(Dest).addOperand(Src), -1); 2006 break; 2007 } 2008 case X86::DEC16r: 2009 case X86::DEC64_16r: 2010 if (DisableLEA16) 2011 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2012 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 2013 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2014 .addOperand(Dest).addOperand(Src), -1); 2015 break; 2016 case X86::ADD64rr: 2017 case X86::ADD64rr_DB: 2018 case X86::ADD32rr: 2019 case X86::ADD32rr_DB: { 2020 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2021 unsigned Opc; 2022 const TargetRegisterClass *RC; 2023 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) { 2024 Opc = X86::LEA64r; 2025 RC = &X86::GR64_NOSPRegClass; 2026 } else { 2027 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2028 RC = &X86::GR32_NOSPRegClass; 2029 } 2030 2031 2032 unsigned Src2 = MI->getOperand(2).getReg(); 2033 bool isKill2 = MI->getOperand(2).isKill(); 2034 2035 // LEA can't handle RSP. 2036 if (TargetRegisterInfo::isVirtualRegister(Src2) && 2037 !MF.getRegInfo().constrainRegClass(Src2, RC)) 2038 return 0; 2039 2040 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2041 .addOperand(Dest), 2042 Src.getReg(), Src.isKill(), Src2, isKill2); 2043 2044 // Preserve undefness of the operands. 2045 bool isUndef = MI->getOperand(1).isUndef(); 2046 bool isUndef2 = MI->getOperand(2).isUndef(); 2047 NewMI->getOperand(1).setIsUndef(isUndef); 2048 NewMI->getOperand(3).setIsUndef(isUndef2); 2049 2050 if (LV && isKill2) 2051 LV->replaceKillInstruction(Src2, MI, NewMI); 2052 break; 2053 } 2054 case X86::ADD16rr: 2055 case X86::ADD16rr_DB: { 2056 if (DisableLEA16) 2057 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2058 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2059 unsigned Src2 = MI->getOperand(2).getReg(); 2060 bool isKill2 = MI->getOperand(2).isKill(); 2061 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2062 .addOperand(Dest), 2063 Src.getReg(), Src.isKill(), Src2, isKill2); 2064 2065 // Preserve undefness of the operands. 2066 bool isUndef = MI->getOperand(1).isUndef(); 2067 bool isUndef2 = MI->getOperand(2).isUndef(); 2068 NewMI->getOperand(1).setIsUndef(isUndef); 2069 NewMI->getOperand(3).setIsUndef(isUndef2); 2070 2071 if (LV && isKill2) 2072 LV->replaceKillInstruction(Src2, MI, NewMI); 2073 break; 2074 } 2075 case X86::ADD64ri32: 2076 case X86::ADD64ri8: 2077 case X86::ADD64ri32_DB: 2078 case X86::ADD64ri8_DB: 2079 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2080 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 2081 .addOperand(Dest).addOperand(Src), 2082 MI->getOperand(2).getImm()); 2083 break; 2084 case X86::ADD32ri: 2085 case X86::ADD32ri8: 2086 case X86::ADD32ri_DB: 2087 case X86::ADD32ri8_DB: { 2088 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2089 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 2090 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 2091 .addOperand(Dest).addOperand(Src), 2092 MI->getOperand(2).getImm()); 2093 break; 2094 } 2095 case X86::ADD16ri: 2096 case X86::ADD16ri8: 2097 case X86::ADD16ri_DB: 2098 case X86::ADD16ri8_DB: 2099 if (DisableLEA16) 2100 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 2101 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 2102 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 2103 .addOperand(Dest).addOperand(Src), 2104 MI->getOperand(2).getImm()); 2105 break; 2106 } 2107 } 2108 } 2109 2110 if (!NewMI) return 0; 2111 2112 if (LV) { // Update live variables 2113 if (Src.isKill()) 2114 LV->replaceKillInstruction(Src.getReg(), MI, NewMI); 2115 if (Dest.isDead()) 2116 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI); 2117 } 2118 2119 MFI->insert(MBBI, NewMI); // Insert the new inst 2120 return NewMI; 2121} 2122 2123/// commuteInstruction - We have a few instructions that must be hacked on to 2124/// commute them. 2125/// 2126MachineInstr * 2127X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 2128 switch (MI->getOpcode()) { 2129 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 2130 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 2131 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 2132 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 2133 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 2134 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 2135 unsigned Opc; 2136 unsigned Size; 2137 switch (MI->getOpcode()) { 2138 default: llvm_unreachable("Unreachable!"); 2139 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 2140 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 2141 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 2142 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 2143 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 2144 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 2145 } 2146 unsigned Amt = MI->getOperand(3).getImm(); 2147 if (NewMI) { 2148 MachineFunction &MF = *MI->getParent()->getParent(); 2149 MI = MF.CloneMachineInstr(MI); 2150 NewMI = false; 2151 } 2152 MI->setDesc(get(Opc)); 2153 MI->getOperand(3).setImm(Size-Amt); 2154 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 2155 } 2156 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr: 2157 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr: 2158 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr: 2159 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr: 2160 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr: 2161 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr: 2162 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr: 2163 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr: 2164 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr: 2165 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr: 2166 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr: 2167 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr: 2168 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr: 2169 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr: 2170 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr: 2171 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: { 2172 unsigned Opc; 2173 switch (MI->getOpcode()) { 2174 default: llvm_unreachable("Unreachable!"); 2175 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 2176 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 2177 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 2178 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 2179 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 2180 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 2181 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 2182 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 2183 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 2184 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 2185 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 2186 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 2187 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 2188 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 2189 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 2190 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 2191 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 2192 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 2193 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 2194 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 2195 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 2196 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 2197 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 2198 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 2199 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 2200 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 2201 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 2202 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 2203 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 2204 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 2205 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 2206 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 2207 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 2208 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 2209 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 2210 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 2211 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 2212 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 2213 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 2214 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 2215 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 2216 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 2217 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 2218 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 2219 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 2220 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 2221 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 2222 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 2223 } 2224 if (NewMI) { 2225 MachineFunction &MF = *MI->getParent()->getParent(); 2226 MI = MF.CloneMachineInstr(MI); 2227 NewMI = false; 2228 } 2229 MI->setDesc(get(Opc)); 2230 // Fallthrough intended. 2231 } 2232 default: 2233 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 2234 } 2235} 2236 2237static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { 2238 switch (BrOpc) { 2239 default: return X86::COND_INVALID; 2240 case X86::JE_4: return X86::COND_E; 2241 case X86::JNE_4: return X86::COND_NE; 2242 case X86::JL_4: return X86::COND_L; 2243 case X86::JLE_4: return X86::COND_LE; 2244 case X86::JG_4: return X86::COND_G; 2245 case X86::JGE_4: return X86::COND_GE; 2246 case X86::JB_4: return X86::COND_B; 2247 case X86::JBE_4: return X86::COND_BE; 2248 case X86::JA_4: return X86::COND_A; 2249 case X86::JAE_4: return X86::COND_AE; 2250 case X86::JS_4: return X86::COND_S; 2251 case X86::JNS_4: return X86::COND_NS; 2252 case X86::JP_4: return X86::COND_P; 2253 case X86::JNP_4: return X86::COND_NP; 2254 case X86::JO_4: return X86::COND_O; 2255 case X86::JNO_4: return X86::COND_NO; 2256 } 2257} 2258 2259/// getCondFromSETOpc - return condition code of a SET opcode. 2260static X86::CondCode getCondFromSETOpc(unsigned Opc) { 2261 switch (Opc) { 2262 default: return X86::COND_INVALID; 2263 case X86::SETAr: case X86::SETAm: return X86::COND_A; 2264 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE; 2265 case X86::SETBr: case X86::SETBm: return X86::COND_B; 2266 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE; 2267 case X86::SETEr: case X86::SETEm: return X86::COND_E; 2268 case X86::SETGr: case X86::SETGm: return X86::COND_G; 2269 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE; 2270 case X86::SETLr: case X86::SETLm: return X86::COND_L; 2271 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE; 2272 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE; 2273 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO; 2274 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP; 2275 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS; 2276 case X86::SETOr: case X86::SETOm: return X86::COND_O; 2277 case X86::SETPr: case X86::SETPm: return X86::COND_P; 2278 case X86::SETSr: case X86::SETSm: return X86::COND_S; 2279 } 2280} 2281 2282/// getCondFromCmovOpc - return condition code of a CMov opcode. 2283X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) { 2284 switch (Opc) { 2285 default: return X86::COND_INVALID; 2286 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm: 2287 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr: 2288 return X86::COND_A; 2289 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm: 2290 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr: 2291 return X86::COND_AE; 2292 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm: 2293 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr: 2294 return X86::COND_B; 2295 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm: 2296 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr: 2297 return X86::COND_BE; 2298 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm: 2299 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr: 2300 return X86::COND_E; 2301 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm: 2302 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr: 2303 return X86::COND_G; 2304 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm: 2305 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr: 2306 return X86::COND_GE; 2307 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm: 2308 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr: 2309 return X86::COND_L; 2310 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm: 2311 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr: 2312 return X86::COND_LE; 2313 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm: 2314 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr: 2315 return X86::COND_NE; 2316 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm: 2317 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr: 2318 return X86::COND_NO; 2319 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm: 2320 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr: 2321 return X86::COND_NP; 2322 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm: 2323 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr: 2324 return X86::COND_NS; 2325 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm: 2326 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr: 2327 return X86::COND_O; 2328 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm: 2329 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr: 2330 return X86::COND_P; 2331 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm: 2332 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr: 2333 return X86::COND_S; 2334 } 2335} 2336 2337unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 2338 switch (CC) { 2339 default: llvm_unreachable("Illegal condition code!"); 2340 case X86::COND_E: return X86::JE_4; 2341 case X86::COND_NE: return X86::JNE_4; 2342 case X86::COND_L: return X86::JL_4; 2343 case X86::COND_LE: return X86::JLE_4; 2344 case X86::COND_G: return X86::JG_4; 2345 case X86::COND_GE: return X86::JGE_4; 2346 case X86::COND_B: return X86::JB_4; 2347 case X86::COND_BE: return X86::JBE_4; 2348 case X86::COND_A: return X86::JA_4; 2349 case X86::COND_AE: return X86::JAE_4; 2350 case X86::COND_S: return X86::JS_4; 2351 case X86::COND_NS: return X86::JNS_4; 2352 case X86::COND_P: return X86::JP_4; 2353 case X86::COND_NP: return X86::JNP_4; 2354 case X86::COND_O: return X86::JO_4; 2355 case X86::COND_NO: return X86::JNO_4; 2356 } 2357} 2358 2359/// GetOppositeBranchCondition - Return the inverse of the specified condition, 2360/// e.g. turning COND_E to COND_NE. 2361X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 2362 switch (CC) { 2363 default: llvm_unreachable("Illegal condition code!"); 2364 case X86::COND_E: return X86::COND_NE; 2365 case X86::COND_NE: return X86::COND_E; 2366 case X86::COND_L: return X86::COND_GE; 2367 case X86::COND_LE: return X86::COND_G; 2368 case X86::COND_G: return X86::COND_LE; 2369 case X86::COND_GE: return X86::COND_L; 2370 case X86::COND_B: return X86::COND_AE; 2371 case X86::COND_BE: return X86::COND_A; 2372 case X86::COND_A: return X86::COND_BE; 2373 case X86::COND_AE: return X86::COND_B; 2374 case X86::COND_S: return X86::COND_NS; 2375 case X86::COND_NS: return X86::COND_S; 2376 case X86::COND_P: return X86::COND_NP; 2377 case X86::COND_NP: return X86::COND_P; 2378 case X86::COND_O: return X86::COND_NO; 2379 case X86::COND_NO: return X86::COND_O; 2380 } 2381} 2382 2383/// getSwappedCondition - assume the flags are set by MI(a,b), return 2384/// the condition code if we modify the instructions such that flags are 2385/// set by MI(b,a). 2386static X86::CondCode getSwappedCondition(X86::CondCode CC) { 2387 switch (CC) { 2388 default: return X86::COND_INVALID; 2389 case X86::COND_E: return X86::COND_E; 2390 case X86::COND_NE: return X86::COND_NE; 2391 case X86::COND_L: return X86::COND_G; 2392 case X86::COND_LE: return X86::COND_GE; 2393 case X86::COND_G: return X86::COND_L; 2394 case X86::COND_GE: return X86::COND_LE; 2395 case X86::COND_B: return X86::COND_A; 2396 case X86::COND_BE: return X86::COND_AE; 2397 case X86::COND_A: return X86::COND_B; 2398 case X86::COND_AE: return X86::COND_BE; 2399 } 2400} 2401 2402/// getSETFromCond - Return a set opcode for the given condition and 2403/// whether it has memory operand. 2404static unsigned getSETFromCond(X86::CondCode CC, 2405 bool HasMemoryOperand) { 2406 static const uint16_t Opc[16][2] = { 2407 { X86::SETAr, X86::SETAm }, 2408 { X86::SETAEr, X86::SETAEm }, 2409 { X86::SETBr, X86::SETBm }, 2410 { X86::SETBEr, X86::SETBEm }, 2411 { X86::SETEr, X86::SETEm }, 2412 { X86::SETGr, X86::SETGm }, 2413 { X86::SETGEr, X86::SETGEm }, 2414 { X86::SETLr, X86::SETLm }, 2415 { X86::SETLEr, X86::SETLEm }, 2416 { X86::SETNEr, X86::SETNEm }, 2417 { X86::SETNOr, X86::SETNOm }, 2418 { X86::SETNPr, X86::SETNPm }, 2419 { X86::SETNSr, X86::SETNSm }, 2420 { X86::SETOr, X86::SETOm }, 2421 { X86::SETPr, X86::SETPm }, 2422 { X86::SETSr, X86::SETSm } 2423 }; 2424 2425 assert(CC < 16 && "Can only handle standard cond codes"); 2426 return Opc[CC][HasMemoryOperand ? 1 : 0]; 2427} 2428 2429/// getCMovFromCond - Return a cmov opcode for the given condition, 2430/// register size in bytes, and operand type. 2431static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes, 2432 bool HasMemoryOperand) { 2433 static const uint16_t Opc[32][3] = { 2434 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr }, 2435 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr }, 2436 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr }, 2437 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr }, 2438 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr }, 2439 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr }, 2440 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr }, 2441 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr }, 2442 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr }, 2443 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr }, 2444 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr }, 2445 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr }, 2446 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr }, 2447 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr }, 2448 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr }, 2449 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr }, 2450 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm }, 2451 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm }, 2452 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm }, 2453 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm }, 2454 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm }, 2455 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm }, 2456 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm }, 2457 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm }, 2458 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm }, 2459 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm }, 2460 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm }, 2461 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm }, 2462 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm }, 2463 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm }, 2464 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm }, 2465 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm } 2466 }; 2467 2468 assert(CC < 16 && "Can only handle standard cond codes"); 2469 unsigned Idx = HasMemoryOperand ? 16+CC : CC; 2470 switch(RegBytes) { 2471 default: llvm_unreachable("Illegal register size!"); 2472 case 2: return Opc[Idx][0]; 2473 case 4: return Opc[Idx][1]; 2474 case 8: return Opc[Idx][2]; 2475 } 2476} 2477 2478bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 2479 if (!MI->isTerminator()) return false; 2480 2481 // Conditional branch is a special case. 2482 if (MI->isBranch() && !MI->isBarrier()) 2483 return true; 2484 if (!MI->isPredicable()) 2485 return true; 2486 return !isPredicated(MI); 2487} 2488 2489bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 2490 MachineBasicBlock *&TBB, 2491 MachineBasicBlock *&FBB, 2492 SmallVectorImpl<MachineOperand> &Cond, 2493 bool AllowModify) const { 2494 // Start from the bottom of the block and work up, examining the 2495 // terminator instructions. 2496 MachineBasicBlock::iterator I = MBB.end(); 2497 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 2498 while (I != MBB.begin()) { 2499 --I; 2500 if (I->isDebugValue()) 2501 continue; 2502 2503 // Working from the bottom, when we see a non-terminator instruction, we're 2504 // done. 2505 if (!isUnpredicatedTerminator(I)) 2506 break; 2507 2508 // A terminator that isn't a branch can't easily be handled by this 2509 // analysis. 2510 if (!I->isBranch()) 2511 return true; 2512 2513 // Handle unconditional branches. 2514 if (I->getOpcode() == X86::JMP_4) { 2515 UnCondBrIter = I; 2516 2517 if (!AllowModify) { 2518 TBB = I->getOperand(0).getMBB(); 2519 continue; 2520 } 2521 2522 // If the block has any instructions after a JMP, delete them. 2523 while (llvm::next(I) != MBB.end()) 2524 llvm::next(I)->eraseFromParent(); 2525 2526 Cond.clear(); 2527 FBB = 0; 2528 2529 // Delete the JMP if it's equivalent to a fall-through. 2530 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 2531 TBB = 0; 2532 I->eraseFromParent(); 2533 I = MBB.end(); 2534 UnCondBrIter = MBB.end(); 2535 continue; 2536 } 2537 2538 // TBB is used to indicate the unconditional destination. 2539 TBB = I->getOperand(0).getMBB(); 2540 continue; 2541 } 2542 2543 // Handle conditional branches. 2544 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); 2545 if (BranchCode == X86::COND_INVALID) 2546 return true; // Can't handle indirect branch. 2547 2548 // Working from the bottom, handle the first conditional branch. 2549 if (Cond.empty()) { 2550 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 2551 if (AllowModify && UnCondBrIter != MBB.end() && 2552 MBB.isLayoutSuccessor(TargetBB)) { 2553 // If we can modify the code and it ends in something like: 2554 // 2555 // jCC L1 2556 // jmp L2 2557 // L1: 2558 // ... 2559 // L2: 2560 // 2561 // Then we can change this to: 2562 // 2563 // jnCC L2 2564 // L1: 2565 // ... 2566 // L2: 2567 // 2568 // Which is a bit more efficient. 2569 // We conditionally jump to the fall-through block. 2570 BranchCode = GetOppositeBranchCondition(BranchCode); 2571 unsigned JNCC = GetCondBranchFromCond(BranchCode); 2572 MachineBasicBlock::iterator OldInst = I; 2573 2574 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 2575 .addMBB(UnCondBrIter->getOperand(0).getMBB()); 2576 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4)) 2577 .addMBB(TargetBB); 2578 2579 OldInst->eraseFromParent(); 2580 UnCondBrIter->eraseFromParent(); 2581 2582 // Restart the analysis. 2583 UnCondBrIter = MBB.end(); 2584 I = MBB.end(); 2585 continue; 2586 } 2587 2588 FBB = TBB; 2589 TBB = I->getOperand(0).getMBB(); 2590 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 2591 continue; 2592 } 2593 2594 // Handle subsequent conditional branches. Only handle the case where all 2595 // conditional branches branch to the same destination and their condition 2596 // opcodes fit one of the special multi-branch idioms. 2597 assert(Cond.size() == 1); 2598 assert(TBB); 2599 2600 // Only handle the case where all conditional branches branch to the same 2601 // destination. 2602 if (TBB != I->getOperand(0).getMBB()) 2603 return true; 2604 2605 // If the conditions are the same, we can leave them alone. 2606 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 2607 if (OldBranchCode == BranchCode) 2608 continue; 2609 2610 // If they differ, see if they fit one of the known patterns. Theoretically, 2611 // we could handle more patterns here, but we shouldn't expect to see them 2612 // if instruction selection has done a reasonable job. 2613 if ((OldBranchCode == X86::COND_NP && 2614 BranchCode == X86::COND_E) || 2615 (OldBranchCode == X86::COND_E && 2616 BranchCode == X86::COND_NP)) 2617 BranchCode = X86::COND_NP_OR_E; 2618 else if ((OldBranchCode == X86::COND_P && 2619 BranchCode == X86::COND_NE) || 2620 (OldBranchCode == X86::COND_NE && 2621 BranchCode == X86::COND_P)) 2622 BranchCode = X86::COND_NE_OR_P; 2623 else 2624 return true; 2625 2626 // Update the MachineOperand. 2627 Cond[0].setImm(BranchCode); 2628 } 2629 2630 return false; 2631} 2632 2633unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 2634 MachineBasicBlock::iterator I = MBB.end(); 2635 unsigned Count = 0; 2636 2637 while (I != MBB.begin()) { 2638 --I; 2639 if (I->isDebugValue()) 2640 continue; 2641 if (I->getOpcode() != X86::JMP_4 && 2642 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 2643 break; 2644 // Remove the branch. 2645 I->eraseFromParent(); 2646 I = MBB.end(); 2647 ++Count; 2648 } 2649 2650 return Count; 2651} 2652 2653unsigned 2654X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 2655 MachineBasicBlock *FBB, 2656 const SmallVectorImpl<MachineOperand> &Cond, 2657 DebugLoc DL) const { 2658 // Shouldn't be a fall through. 2659 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 2660 assert((Cond.size() == 1 || Cond.size() == 0) && 2661 "X86 branch conditions have one component!"); 2662 2663 if (Cond.empty()) { 2664 // Unconditional branch? 2665 assert(!FBB && "Unconditional branch with multiple successors!"); 2666 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB); 2667 return 1; 2668 } 2669 2670 // Conditional branch. 2671 unsigned Count = 0; 2672 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 2673 switch (CC) { 2674 case X86::COND_NP_OR_E: 2675 // Synthesize NP_OR_E with two branches. 2676 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB); 2677 ++Count; 2678 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB); 2679 ++Count; 2680 break; 2681 case X86::COND_NE_OR_P: 2682 // Synthesize NE_OR_P with two branches. 2683 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB); 2684 ++Count; 2685 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB); 2686 ++Count; 2687 break; 2688 default: { 2689 unsigned Opc = GetCondBranchFromCond(CC); 2690 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 2691 ++Count; 2692 } 2693 } 2694 if (FBB) { 2695 // Two-way Conditional branch. Insert the second branch. 2696 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB); 2697 ++Count; 2698 } 2699 return Count; 2700} 2701 2702bool X86InstrInfo:: 2703canInsertSelect(const MachineBasicBlock &MBB, 2704 const SmallVectorImpl<MachineOperand> &Cond, 2705 unsigned TrueReg, unsigned FalseReg, 2706 int &CondCycles, int &TrueCycles, int &FalseCycles) const { 2707 // Not all subtargets have cmov instructions. 2708 if (!TM.getSubtarget<X86Subtarget>().hasCMov()) 2709 return false; 2710 if (Cond.size() != 1) 2711 return false; 2712 // We cannot do the composite conditions, at least not in SSA form. 2713 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S) 2714 return false; 2715 2716 // Check register classes. 2717 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2718 const TargetRegisterClass *RC = 2719 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); 2720 if (!RC) 2721 return false; 2722 2723 // We have cmov instructions for 16, 32, and 64 bit general purpose registers. 2724 if (X86::GR16RegClass.hasSubClassEq(RC) || 2725 X86::GR32RegClass.hasSubClassEq(RC) || 2726 X86::GR64RegClass.hasSubClassEq(RC)) { 2727 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy 2728 // Bridge. Probably Ivy Bridge as well. 2729 CondCycles = 2; 2730 TrueCycles = 2; 2731 FalseCycles = 2; 2732 return true; 2733 } 2734 2735 // Can't do vectors. 2736 return false; 2737} 2738 2739void X86InstrInfo::insertSelect(MachineBasicBlock &MBB, 2740 MachineBasicBlock::iterator I, DebugLoc DL, 2741 unsigned DstReg, 2742 const SmallVectorImpl<MachineOperand> &Cond, 2743 unsigned TrueReg, unsigned FalseReg) const { 2744 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 2745 assert(Cond.size() == 1 && "Invalid Cond array"); 2746 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(), 2747 MRI.getRegClass(DstReg)->getSize(), 2748 false/*HasMemoryOperand*/); 2749 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); 2750} 2751 2752/// isHReg - Test if the given register is a physical h register. 2753static bool isHReg(unsigned Reg) { 2754 return X86::GR8_ABCD_HRegClass.contains(Reg); 2755} 2756 2757// Try and copy between VR128/VR64 and GR64 registers. 2758static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg, 2759 bool HasAVX) { 2760 // SrcReg(VR128) -> DestReg(GR64) 2761 // SrcReg(VR64) -> DestReg(GR64) 2762 // SrcReg(GR64) -> DestReg(VR128) 2763 // SrcReg(GR64) -> DestReg(VR64) 2764 2765 if (X86::GR64RegClass.contains(DestReg)) { 2766 if (X86::VR128RegClass.contains(SrcReg)) 2767 // Copy from a VR128 register to a GR64 register. 2768 return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr; 2769 if (X86::VR64RegClass.contains(SrcReg)) 2770 // Copy from a VR64 register to a GR64 register. 2771 return X86::MOVSDto64rr; 2772 } else if (X86::GR64RegClass.contains(SrcReg)) { 2773 // Copy from a GR64 register to a VR128 register. 2774 if (X86::VR128RegClass.contains(DestReg)) 2775 return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr; 2776 // Copy from a GR64 register to a VR64 register. 2777 if (X86::VR64RegClass.contains(DestReg)) 2778 return X86::MOV64toSDrr; 2779 } 2780 2781 // SrcReg(FR32) -> DestReg(GR32) 2782 // SrcReg(GR32) -> DestReg(FR32) 2783 2784 if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg)) 2785 // Copy from a FR32 register to a GR32 register. 2786 return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr; 2787 2788 if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg)) 2789 // Copy from a GR32 register to a FR32 register. 2790 return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr; 2791 2792 return 0; 2793} 2794 2795void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 2796 MachineBasicBlock::iterator MI, DebugLoc DL, 2797 unsigned DestReg, unsigned SrcReg, 2798 bool KillSrc) const { 2799 // First deal with the normal symmetric copies. 2800 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 2801 unsigned Opc; 2802 if (X86::GR64RegClass.contains(DestReg, SrcReg)) 2803 Opc = X86::MOV64rr; 2804 else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 2805 Opc = X86::MOV32rr; 2806 else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 2807 Opc = X86::MOV16rr; 2808 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 2809 // Copying to or from a physical H register on x86-64 requires a NOREX 2810 // move. Otherwise use a normal move. 2811 if ((isHReg(DestReg) || isHReg(SrcReg)) && 2812 TM.getSubtarget<X86Subtarget>().is64Bit()) { 2813 Opc = X86::MOV8rr_NOREX; 2814 // Both operands must be encodable without an REX prefix. 2815 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) && 2816 "8-bit H register can not be copied outside GR8_NOREX"); 2817 } else 2818 Opc = X86::MOV8rr; 2819 } else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 2820 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr; 2821 else if (X86::VR256RegClass.contains(DestReg, SrcReg)) 2822 Opc = X86::VMOVAPSYrr; 2823 else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 2824 Opc = X86::MMX_MOVQ64rr; 2825 else 2826 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX); 2827 2828 if (Opc) { 2829 BuildMI(MBB, MI, DL, get(Opc), DestReg) 2830 .addReg(SrcReg, getKillRegState(KillSrc)); 2831 return; 2832 } 2833 2834 // Moving EFLAGS to / from another register requires a push and a pop. 2835 if (SrcReg == X86::EFLAGS) { 2836 if (X86::GR64RegClass.contains(DestReg)) { 2837 BuildMI(MBB, MI, DL, get(X86::PUSHF64)); 2838 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 2839 return; 2840 } 2841 if (X86::GR32RegClass.contains(DestReg)) { 2842 BuildMI(MBB, MI, DL, get(X86::PUSHF32)); 2843 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 2844 return; 2845 } 2846 } 2847 if (DestReg == X86::EFLAGS) { 2848 if (X86::GR64RegClass.contains(SrcReg)) { 2849 BuildMI(MBB, MI, DL, get(X86::PUSH64r)) 2850 .addReg(SrcReg, getKillRegState(KillSrc)); 2851 BuildMI(MBB, MI, DL, get(X86::POPF64)); 2852 return; 2853 } 2854 if (X86::GR32RegClass.contains(SrcReg)) { 2855 BuildMI(MBB, MI, DL, get(X86::PUSH32r)) 2856 .addReg(SrcReg, getKillRegState(KillSrc)); 2857 BuildMI(MBB, MI, DL, get(X86::POPF32)); 2858 return; 2859 } 2860 } 2861 2862 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 2863 << " to " << RI.getName(DestReg) << '\n'); 2864 llvm_unreachable("Cannot emit physreg copy instruction"); 2865} 2866 2867static unsigned getLoadStoreRegOpcode(unsigned Reg, 2868 const TargetRegisterClass *RC, 2869 bool isStackAligned, 2870 const TargetMachine &TM, 2871 bool load) { 2872 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 2873 switch (RC->getSize()) { 2874 default: 2875 llvm_unreachable("Unknown spill size"); 2876 case 1: 2877 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); 2878 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2879 // Copying to or from a physical H register on x86-64 requires a NOREX 2880 // move. Otherwise use a normal move. 2881 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) 2882 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 2883 return load ? X86::MOV8rm : X86::MOV8mr; 2884 case 2: 2885 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); 2886 return load ? X86::MOV16rm : X86::MOV16mr; 2887 case 4: 2888 if (X86::GR32RegClass.hasSubClassEq(RC)) 2889 return load ? X86::MOV32rm : X86::MOV32mr; 2890 if (X86::FR32RegClass.hasSubClassEq(RC)) 2891 return load ? 2892 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) : 2893 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr); 2894 if (X86::RFP32RegClass.hasSubClassEq(RC)) 2895 return load ? X86::LD_Fp32m : X86::ST_Fp32m; 2896 llvm_unreachable("Unknown 4-byte regclass"); 2897 case 8: 2898 if (X86::GR64RegClass.hasSubClassEq(RC)) 2899 return load ? X86::MOV64rm : X86::MOV64mr; 2900 if (X86::FR64RegClass.hasSubClassEq(RC)) 2901 return load ? 2902 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) : 2903 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr); 2904 if (X86::VR64RegClass.hasSubClassEq(RC)) 2905 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 2906 if (X86::RFP64RegClass.hasSubClassEq(RC)) 2907 return load ? X86::LD_Fp64m : X86::ST_Fp64m; 2908 llvm_unreachable("Unknown 8-byte regclass"); 2909 case 10: 2910 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); 2911 return load ? X86::LD_Fp80m : X86::ST_FpP80m; 2912 case 16: { 2913 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass"); 2914 // If stack is realigned we can use aligned stores. 2915 if (isStackAligned) 2916 return load ? 2917 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) : 2918 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr); 2919 else 2920 return load ? 2921 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) : 2922 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr); 2923 } 2924 case 32: 2925 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"); 2926 // If stack is realigned we can use aligned stores. 2927 if (isStackAligned) 2928 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr; 2929 else 2930 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr; 2931 } 2932} 2933 2934static unsigned getStoreRegOpcode(unsigned SrcReg, 2935 const TargetRegisterClass *RC, 2936 bool isStackAligned, 2937 TargetMachine &TM) { 2938 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false); 2939} 2940 2941 2942static unsigned getLoadRegOpcode(unsigned DestReg, 2943 const TargetRegisterClass *RC, 2944 bool isStackAligned, 2945 const TargetMachine &TM) { 2946 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true); 2947} 2948 2949void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 2950 MachineBasicBlock::iterator MI, 2951 unsigned SrcReg, bool isKill, int FrameIdx, 2952 const TargetRegisterClass *RC, 2953 const TargetRegisterInfo *TRI) const { 2954 const MachineFunction &MF = *MBB.getParent(); 2955 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() && 2956 "Stack slot too small for store"); 2957 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 2958 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) || 2959 RI.canRealignStack(MF); 2960 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2961 DebugLoc DL = MBB.findDebugLoc(MI); 2962 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 2963 .addReg(SrcReg, getKillRegState(isKill)); 2964} 2965 2966void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 2967 bool isKill, 2968 SmallVectorImpl<MachineOperand> &Addr, 2969 const TargetRegisterClass *RC, 2970 MachineInstr::mmo_iterator MMOBegin, 2971 MachineInstr::mmo_iterator MMOEnd, 2972 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2973 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 2974 bool isAligned = MMOBegin != MMOEnd && 2975 (*MMOBegin)->getAlignment() >= Alignment; 2976 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2977 DebugLoc DL; 2978 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 2979 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2980 MIB.addOperand(Addr[i]); 2981 MIB.addReg(SrcReg, getKillRegState(isKill)); 2982 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2983 NewMIs.push_back(MIB); 2984} 2985 2986 2987void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 2988 MachineBasicBlock::iterator MI, 2989 unsigned DestReg, int FrameIdx, 2990 const TargetRegisterClass *RC, 2991 const TargetRegisterInfo *TRI) const { 2992 const MachineFunction &MF = *MBB.getParent(); 2993 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 2994 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) || 2995 RI.canRealignStack(MF); 2996 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2997 DebugLoc DL = MBB.findDebugLoc(MI); 2998 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 2999} 3000 3001void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 3002 SmallVectorImpl<MachineOperand> &Addr, 3003 const TargetRegisterClass *RC, 3004 MachineInstr::mmo_iterator MMOBegin, 3005 MachineInstr::mmo_iterator MMOEnd, 3006 SmallVectorImpl<MachineInstr*> &NewMIs) const { 3007 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 3008 bool isAligned = MMOBegin != MMOEnd && 3009 (*MMOBegin)->getAlignment() >= Alignment; 3010 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 3011 DebugLoc DL; 3012 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 3013 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 3014 MIB.addOperand(Addr[i]); 3015 (*MIB).setMemRefs(MMOBegin, MMOEnd); 3016 NewMIs.push_back(MIB); 3017} 3018 3019bool X86InstrInfo:: 3020analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, 3021 int &CmpMask, int &CmpValue) const { 3022 switch (MI->getOpcode()) { 3023 default: break; 3024 case X86::CMP64ri32: 3025 case X86::CMP64ri8: 3026 case X86::CMP32ri: 3027 case X86::CMP32ri8: 3028 case X86::CMP16ri: 3029 case X86::CMP16ri8: 3030 case X86::CMP8ri: 3031 SrcReg = MI->getOperand(0).getReg(); 3032 SrcReg2 = 0; 3033 CmpMask = ~0; 3034 CmpValue = MI->getOperand(1).getImm(); 3035 return true; 3036 // A SUB can be used to perform comparison. 3037 case X86::SUB64rm: 3038 case X86::SUB32rm: 3039 case X86::SUB16rm: 3040 case X86::SUB8rm: 3041 SrcReg = MI->getOperand(1).getReg(); 3042 SrcReg2 = 0; 3043 CmpMask = ~0; 3044 CmpValue = 0; 3045 return true; 3046 case X86::SUB64rr: 3047 case X86::SUB32rr: 3048 case X86::SUB16rr: 3049 case X86::SUB8rr: 3050 SrcReg = MI->getOperand(1).getReg(); 3051 SrcReg2 = MI->getOperand(2).getReg(); 3052 CmpMask = ~0; 3053 CmpValue = 0; 3054 return true; 3055 case X86::SUB64ri32: 3056 case X86::SUB64ri8: 3057 case X86::SUB32ri: 3058 case X86::SUB32ri8: 3059 case X86::SUB16ri: 3060 case X86::SUB16ri8: 3061 case X86::SUB8ri: 3062 SrcReg = MI->getOperand(1).getReg(); 3063 SrcReg2 = 0; 3064 CmpMask = ~0; 3065 CmpValue = MI->getOperand(2).getImm(); 3066 return true; 3067 case X86::CMP64rr: 3068 case X86::CMP32rr: 3069 case X86::CMP16rr: 3070 case X86::CMP8rr: 3071 SrcReg = MI->getOperand(0).getReg(); 3072 SrcReg2 = MI->getOperand(1).getReg(); 3073 CmpMask = ~0; 3074 CmpValue = 0; 3075 return true; 3076 case X86::TEST8rr: 3077 case X86::TEST16rr: 3078 case X86::TEST32rr: 3079 case X86::TEST64rr: 3080 SrcReg = MI->getOperand(0).getReg(); 3081 if (MI->getOperand(1).getReg() != SrcReg) return false; 3082 // Compare against zero. 3083 SrcReg2 = 0; 3084 CmpMask = ~0; 3085 CmpValue = 0; 3086 return true; 3087 } 3088 return false; 3089} 3090 3091/// isRedundantFlagInstr - check whether the first instruction, whose only 3092/// purpose is to update flags, can be made redundant. 3093/// CMPrr can be made redundant by SUBrr if the operands are the same. 3094/// This function can be extended later on. 3095/// SrcReg, SrcRegs: register operands for FlagI. 3096/// ImmValue: immediate for FlagI if it takes an immediate. 3097inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg, 3098 unsigned SrcReg2, int ImmValue, 3099 MachineInstr *OI) { 3100 if (((FlagI->getOpcode() == X86::CMP64rr && 3101 OI->getOpcode() == X86::SUB64rr) || 3102 (FlagI->getOpcode() == X86::CMP32rr && 3103 OI->getOpcode() == X86::SUB32rr)|| 3104 (FlagI->getOpcode() == X86::CMP16rr && 3105 OI->getOpcode() == X86::SUB16rr)|| 3106 (FlagI->getOpcode() == X86::CMP8rr && 3107 OI->getOpcode() == X86::SUB8rr)) && 3108 ((OI->getOperand(1).getReg() == SrcReg && 3109 OI->getOperand(2).getReg() == SrcReg2) || 3110 (OI->getOperand(1).getReg() == SrcReg2 && 3111 OI->getOperand(2).getReg() == SrcReg))) 3112 return true; 3113 3114 if (((FlagI->getOpcode() == X86::CMP64ri32 && 3115 OI->getOpcode() == X86::SUB64ri32) || 3116 (FlagI->getOpcode() == X86::CMP64ri8 && 3117 OI->getOpcode() == X86::SUB64ri8) || 3118 (FlagI->getOpcode() == X86::CMP32ri && 3119 OI->getOpcode() == X86::SUB32ri) || 3120 (FlagI->getOpcode() == X86::CMP32ri8 && 3121 OI->getOpcode() == X86::SUB32ri8) || 3122 (FlagI->getOpcode() == X86::CMP16ri && 3123 OI->getOpcode() == X86::SUB16ri) || 3124 (FlagI->getOpcode() == X86::CMP16ri8 && 3125 OI->getOpcode() == X86::SUB16ri8) || 3126 (FlagI->getOpcode() == X86::CMP8ri && 3127 OI->getOpcode() == X86::SUB8ri)) && 3128 OI->getOperand(1).getReg() == SrcReg && 3129 OI->getOperand(2).getImm() == ImmValue) 3130 return true; 3131 return false; 3132} 3133 3134/// isDefConvertible - check whether the definition can be converted 3135/// to remove a comparison against zero. 3136inline static bool isDefConvertible(MachineInstr *MI) { 3137 switch (MI->getOpcode()) { 3138 default: return false; 3139 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri: 3140 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8: 3141 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr: 3142 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm: 3143 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm: 3144 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r: 3145 case X86::DEC64m: case X86::DEC32m: case X86::DEC16m: case X86::DEC8m: 3146 case X86::DEC64_32r: case X86::DEC64_16r: 3147 case X86::DEC64_32m: case X86::DEC64_16m: 3148 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri: 3149 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8: 3150 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr: 3151 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm: 3152 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm: 3153 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r: 3154 case X86::INC64m: case X86::INC32m: case X86::INC16m: case X86::INC8m: 3155 case X86::INC64_32r: case X86::INC64_16r: 3156 case X86::INC64_32m: case X86::INC64_16m: 3157 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri: 3158 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8: 3159 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr: 3160 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm: 3161 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm: 3162 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri: 3163 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8: 3164 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr: 3165 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm: 3166 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm: 3167 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri: 3168 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8: 3169 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr: 3170 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm: 3171 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm: 3172 return true; 3173 } 3174} 3175 3176/// optimizeCompareInstr - Check if there exists an earlier instruction that 3177/// operates on the same source operands and sets flags in the same way as 3178/// Compare; remove Compare if possible. 3179bool X86InstrInfo:: 3180optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, 3181 int CmpMask, int CmpValue, 3182 const MachineRegisterInfo *MRI) const { 3183 // Check whether we can replace SUB with CMP. 3184 unsigned NewOpcode = 0; 3185 switch (CmpInstr->getOpcode()) { 3186 default: break; 3187 case X86::SUB64ri32: 3188 case X86::SUB64ri8: 3189 case X86::SUB32ri: 3190 case X86::SUB32ri8: 3191 case X86::SUB16ri: 3192 case X86::SUB16ri8: 3193 case X86::SUB8ri: 3194 case X86::SUB64rm: 3195 case X86::SUB32rm: 3196 case X86::SUB16rm: 3197 case X86::SUB8rm: 3198 case X86::SUB64rr: 3199 case X86::SUB32rr: 3200 case X86::SUB16rr: 3201 case X86::SUB8rr: { 3202 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg())) 3203 return false; 3204 // There is no use of the destination register, we can replace SUB with CMP. 3205 switch (CmpInstr->getOpcode()) { 3206 default: llvm_unreachable("Unreachable!"); 3207 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 3208 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 3209 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 3210 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 3211 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 3212 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 3213 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 3214 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 3215 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; 3216 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break; 3217 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break; 3218 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break; 3219 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break; 3220 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break; 3221 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break; 3222 } 3223 CmpInstr->setDesc(get(NewOpcode)); 3224 CmpInstr->RemoveOperand(0); 3225 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri. 3226 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || 3227 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm) 3228 return false; 3229 } 3230 } 3231 3232 // Get the unique definition of SrcReg. 3233 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); 3234 if (!MI) return false; 3235 3236 // CmpInstr is the first instruction of the BB. 3237 MachineBasicBlock::iterator I = CmpInstr, Def = MI; 3238 3239 // If we are comparing against zero, check whether we can use MI to update 3240 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize. 3241 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0); 3242 if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() || 3243 !isDefConvertible(MI))) 3244 return false; 3245 3246 // We are searching for an earlier instruction that can make CmpInstr 3247 // redundant and that instruction will be saved in Sub. 3248 MachineInstr *Sub = NULL; 3249 const TargetRegisterInfo *TRI = &getRegisterInfo(); 3250 3251 // We iterate backward, starting from the instruction before CmpInstr and 3252 // stop when reaching the definition of a source register or done with the BB. 3253 // RI points to the instruction before CmpInstr. 3254 // If the definition is in this basic block, RE points to the definition; 3255 // otherwise, RE is the rend of the basic block. 3256 MachineBasicBlock::reverse_iterator 3257 RI = MachineBasicBlock::reverse_iterator(I), 3258 RE = CmpInstr->getParent() == MI->getParent() ? 3259 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ : 3260 CmpInstr->getParent()->rend(); 3261 MachineInstr *Movr0Inst = 0; 3262 for (; RI != RE; ++RI) { 3263 MachineInstr *Instr = &*RI; 3264 // Check whether CmpInstr can be made redundant by the current instruction. 3265 if (!IsCmpZero && 3266 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) { 3267 Sub = Instr; 3268 break; 3269 } 3270 3271 if (Instr->modifiesRegister(X86::EFLAGS, TRI) || 3272 Instr->readsRegister(X86::EFLAGS, TRI)) { 3273 // This instruction modifies or uses EFLAGS. 3274 3275 // MOV32r0 etc. are implemented with xor which clobbers condition code. 3276 // They are safe to move up, if the definition to EFLAGS is dead and 3277 // earlier instructions do not read or write EFLAGS. 3278 if (!Movr0Inst && (Instr->getOpcode() == X86::MOV8r0 || 3279 Instr->getOpcode() == X86::MOV16r0 || 3280 Instr->getOpcode() == X86::MOV32r0 || 3281 Instr->getOpcode() == X86::MOV64r0) && 3282 Instr->registerDefIsDead(X86::EFLAGS, TRI)) { 3283 Movr0Inst = Instr; 3284 continue; 3285 } 3286 3287 // We can't remove CmpInstr. 3288 return false; 3289 } 3290 } 3291 3292 // Return false if no candidates exist. 3293 if (!IsCmpZero && !Sub) 3294 return false; 3295 3296 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && 3297 Sub->getOperand(2).getReg() == SrcReg); 3298 3299 // Scan forward from the instruction after CmpInstr for uses of EFLAGS. 3300 // It is safe to remove CmpInstr if EFLAGS is redefined or killed. 3301 // If we are done with the basic block, we need to check whether EFLAGS is 3302 // live-out. 3303 bool IsSafe = false; 3304 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate; 3305 MachineBasicBlock::iterator E = CmpInstr->getParent()->end(); 3306 for (++I; I != E; ++I) { 3307 const MachineInstr &Instr = *I; 3308 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI); 3309 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI); 3310 // We should check the usage if this instruction uses and updates EFLAGS. 3311 if (!UseEFLAGS && ModifyEFLAGS) { 3312 // It is safe to remove CmpInstr if EFLAGS is updated again. 3313 IsSafe = true; 3314 break; 3315 } 3316 if (!UseEFLAGS && !ModifyEFLAGS) 3317 continue; 3318 3319 // EFLAGS is used by this instruction. 3320 X86::CondCode OldCC; 3321 bool OpcIsSET = false; 3322 if (IsCmpZero || IsSwapped) { 3323 // We decode the condition code from opcode. 3324 if (Instr.isBranch()) 3325 OldCC = getCondFromBranchOpc(Instr.getOpcode()); 3326 else { 3327 OldCC = getCondFromSETOpc(Instr.getOpcode()); 3328 if (OldCC != X86::COND_INVALID) 3329 OpcIsSET = true; 3330 else 3331 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode()); 3332 } 3333 if (OldCC == X86::COND_INVALID) return false; 3334 } 3335 if (IsCmpZero) { 3336 switch (OldCC) { 3337 default: break; 3338 case X86::COND_A: case X86::COND_AE: 3339 case X86::COND_B: case X86::COND_BE: 3340 case X86::COND_G: case X86::COND_GE: 3341 case X86::COND_L: case X86::COND_LE: 3342 case X86::COND_O: case X86::COND_NO: 3343 // CF and OF are used, we can't perform this optimization. 3344 return false; 3345 } 3346 } else if (IsSwapped) { 3347 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs 3348 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. 3349 // We swap the condition code and synthesize the new opcode. 3350 X86::CondCode NewCC = getSwappedCondition(OldCC); 3351 if (NewCC == X86::COND_INVALID) return false; 3352 3353 // Synthesize the new opcode. 3354 bool HasMemoryOperand = Instr.hasOneMemOperand(); 3355 unsigned NewOpc; 3356 if (Instr.isBranch()) 3357 NewOpc = GetCondBranchFromCond(NewCC); 3358 else if(OpcIsSET) 3359 NewOpc = getSETFromCond(NewCC, HasMemoryOperand); 3360 else { 3361 unsigned DstReg = Instr.getOperand(0).getReg(); 3362 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), 3363 HasMemoryOperand); 3364 } 3365 3366 // Push the MachineInstr to OpsToUpdate. 3367 // If it is safe to remove CmpInstr, the condition code of these 3368 // instructions will be modified. 3369 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); 3370 } 3371 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) { 3372 // It is safe to remove CmpInstr if EFLAGS is updated again or killed. 3373 IsSafe = true; 3374 break; 3375 } 3376 } 3377 3378 // If EFLAGS is not killed nor re-defined, we should check whether it is 3379 // live-out. If it is live-out, do not optimize. 3380 if ((IsCmpZero || IsSwapped) && !IsSafe) { 3381 MachineBasicBlock *MBB = CmpInstr->getParent(); 3382 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), 3383 SE = MBB->succ_end(); SI != SE; ++SI) 3384 if ((*SI)->isLiveIn(X86::EFLAGS)) 3385 return false; 3386 } 3387 3388 // The instruction to be updated is either Sub or MI. 3389 Sub = IsCmpZero ? MI : Sub; 3390 // Move Movr0Inst to the place right before Sub. 3391 if (Movr0Inst) { 3392 Sub->getParent()->remove(Movr0Inst); 3393 Sub->getParent()->insert(MachineBasicBlock::iterator(Sub), Movr0Inst); 3394 } 3395 3396 // Make sure Sub instruction defines EFLAGS and mark the def live. 3397 unsigned LastOperand = Sub->getNumOperands() - 1; 3398 assert(Sub->getNumOperands() >= 2 && 3399 Sub->getOperand(LastOperand).isReg() && 3400 Sub->getOperand(LastOperand).getReg() == X86::EFLAGS && 3401 "EFLAGS should be the last operand of SUB, ADD, OR, XOR, AND"); 3402 Sub->getOperand(LastOperand).setIsDef(true); 3403 Sub->getOperand(LastOperand).setIsDead(false); 3404 CmpInstr->eraseFromParent(); 3405 3406 // Modify the condition code of instructions in OpsToUpdate. 3407 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++) 3408 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second)); 3409 return true; 3410} 3411 3412/// optimizeLoadInstr - Try to remove the load by folding it to a register 3413/// operand at the use. We fold the load instructions if load defines a virtual 3414/// register, the virtual register is used once in the same BB, and the 3415/// instructions in-between do not load or store, and have no side effects. 3416MachineInstr* X86InstrInfo:: 3417optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, 3418 unsigned &FoldAsLoadDefReg, 3419 MachineInstr *&DefMI) const { 3420 if (FoldAsLoadDefReg == 0) 3421 return 0; 3422 // To be conservative, if there exists another load, clear the load candidate. 3423 if (MI->mayLoad()) { 3424 FoldAsLoadDefReg = 0; 3425 return 0; 3426 } 3427 3428 // Check whether we can move DefMI here. 3429 DefMI = MRI->getVRegDef(FoldAsLoadDefReg); 3430 assert(DefMI); 3431 bool SawStore = false; 3432 if (!DefMI->isSafeToMove(this, 0, SawStore)) 3433 return 0; 3434 3435 // We try to commute MI if possible. 3436 unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1; 3437 for (unsigned Idx = 0; Idx < IdxEnd; Idx++) { 3438 // Collect information about virtual register operands of MI. 3439 unsigned SrcOperandId = 0; 3440 bool FoundSrcOperand = false; 3441 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { 3442 MachineOperand &MO = MI->getOperand(i); 3443 if (!MO.isReg()) 3444 continue; 3445 unsigned Reg = MO.getReg(); 3446 if (Reg != FoldAsLoadDefReg) 3447 continue; 3448 // Do not fold if we have a subreg use or a def or multiple uses. 3449 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand) 3450 return 0; 3451 3452 SrcOperandId = i; 3453 FoundSrcOperand = true; 3454 } 3455 if (!FoundSrcOperand) return 0; 3456 3457 // Check whether we can fold the def into SrcOperandId. 3458 SmallVector<unsigned, 8> Ops; 3459 Ops.push_back(SrcOperandId); 3460 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI); 3461 if (FoldMI) { 3462 FoldAsLoadDefReg = 0; 3463 return FoldMI; 3464 } 3465 3466 if (Idx == 1) { 3467 // MI was changed but it didn't help, commute it back! 3468 commuteInstruction(MI, false); 3469 return 0; 3470 } 3471 3472 // Check whether we can commute MI and enable folding. 3473 if (MI->isCommutable()) { 3474 MachineInstr *NewMI = commuteInstruction(MI, false); 3475 // Unable to commute. 3476 if (!NewMI) return 0; 3477 if (NewMI != MI) { 3478 // New instruction. It doesn't need to be kept. 3479 NewMI->eraseFromParent(); 3480 return 0; 3481 } 3482 } 3483 } 3484 return 0; 3485} 3486 3487/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr 3488/// instruction with two undef reads of the register being defined. This is 3489/// used for mapping: 3490/// %xmm4 = V_SET0 3491/// to: 3492/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef> 3493/// 3494static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) { 3495 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); 3496 unsigned Reg = MI->getOperand(0).getReg(); 3497 MI->setDesc(Desc); 3498 3499 // MachineInstr::addOperand() will insert explicit operands before any 3500 // implicit operands. 3501 MachineInstrBuilder(MI).addReg(Reg, RegState::Undef) 3502 .addReg(Reg, RegState::Undef); 3503 // But we don't trust that. 3504 assert(MI->getOperand(1).getReg() == Reg && 3505 MI->getOperand(2).getReg() == Reg && "Misplaced operand"); 3506 return true; 3507} 3508 3509bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 3510 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 3511 switch (MI->getOpcode()) { 3512 case X86::V_SET0: 3513 case X86::FsFLD0SS: 3514 case X86::FsFLD0SD: 3515 return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); 3516 case X86::AVX_SET0: 3517 assert(HasAVX && "AVX not supported"); 3518 return Expand2AddrUndef(MI, get(X86::VXORPSYrr)); 3519 case X86::V_SETALLONES: 3520 return Expand2AddrUndef(MI, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); 3521 case X86::AVX2_SETALLONES: 3522 return Expand2AddrUndef(MI, get(X86::VPCMPEQDYrr)); 3523 case X86::TEST8ri_NOREX: 3524 MI->setDesc(get(X86::TEST8ri)); 3525 return true; 3526 } 3527 return false; 3528} 3529 3530MachineInstr* 3531X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 3532 int FrameIx, uint64_t Offset, 3533 const MDNode *MDPtr, 3534 DebugLoc DL) const { 3535 X86AddressMode AM; 3536 AM.BaseType = X86AddressMode::FrameIndexBase; 3537 AM.Base.FrameIndex = FrameIx; 3538 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); 3539 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr); 3540 return &*MIB; 3541} 3542 3543static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 3544 const SmallVectorImpl<MachineOperand> &MOs, 3545 MachineInstr *MI, 3546 const TargetInstrInfo &TII) { 3547 // Create the base instruction with the memory operand as the first part. 3548 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 3549 MI->getDebugLoc(), true); 3550 MachineInstrBuilder MIB(NewMI); 3551 unsigned NumAddrOps = MOs.size(); 3552 for (unsigned i = 0; i != NumAddrOps; ++i) 3553 MIB.addOperand(MOs[i]); 3554 if (NumAddrOps < 4) // FrameIndex only 3555 addOffset(MIB, 0); 3556 3557 // Loop over the rest of the ri operands, converting them over. 3558 unsigned NumOps = MI->getDesc().getNumOperands()-2; 3559 for (unsigned i = 0; i != NumOps; ++i) { 3560 MachineOperand &MO = MI->getOperand(i+2); 3561 MIB.addOperand(MO); 3562 } 3563 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 3564 MachineOperand &MO = MI->getOperand(i); 3565 MIB.addOperand(MO); 3566 } 3567 return MIB; 3568} 3569 3570static MachineInstr *FuseInst(MachineFunction &MF, 3571 unsigned Opcode, unsigned OpNo, 3572 const SmallVectorImpl<MachineOperand> &MOs, 3573 MachineInstr *MI, const TargetInstrInfo &TII) { 3574 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 3575 MI->getDebugLoc(), true); 3576 MachineInstrBuilder MIB(NewMI); 3577 3578 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 3579 MachineOperand &MO = MI->getOperand(i); 3580 if (i == OpNo) { 3581 assert(MO.isReg() && "Expected to fold into reg operand!"); 3582 unsigned NumAddrOps = MOs.size(); 3583 for (unsigned i = 0; i != NumAddrOps; ++i) 3584 MIB.addOperand(MOs[i]); 3585 if (NumAddrOps < 4) // FrameIndex only 3586 addOffset(MIB, 0); 3587 } else { 3588 MIB.addOperand(MO); 3589 } 3590 } 3591 return MIB; 3592} 3593 3594static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 3595 const SmallVectorImpl<MachineOperand> &MOs, 3596 MachineInstr *MI) { 3597 MachineFunction &MF = *MI->getParent()->getParent(); 3598 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 3599 3600 unsigned NumAddrOps = MOs.size(); 3601 for (unsigned i = 0; i != NumAddrOps; ++i) 3602 MIB.addOperand(MOs[i]); 3603 if (NumAddrOps < 4) // FrameIndex only 3604 addOffset(MIB, 0); 3605 return MIB.addImm(0); 3606} 3607 3608MachineInstr* 3609X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3610 MachineInstr *MI, unsigned i, 3611 const SmallVectorImpl<MachineOperand> &MOs, 3612 unsigned Size, unsigned Align) const { 3613 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 3614 bool isTwoAddrFold = false; 3615 unsigned NumOps = MI->getDesc().getNumOperands(); 3616 bool isTwoAddr = NumOps > 1 && 3617 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 3618 3619 // FIXME: AsmPrinter doesn't know how to handle 3620 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 3621 if (MI->getOpcode() == X86::ADD32ri && 3622 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 3623 return NULL; 3624 3625 MachineInstr *NewMI = NULL; 3626 // Folding a memory location into the two-address part of a two-address 3627 // instruction is different than folding it other places. It requires 3628 // replacing the *two* registers with the memory location. 3629 if (isTwoAddr && NumOps >= 2 && i < 2 && 3630 MI->getOperand(0).isReg() && 3631 MI->getOperand(1).isReg() && 3632 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 3633 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 3634 isTwoAddrFold = true; 3635 } else if (i == 0) { // If operand 0 3636 unsigned Opc = 0; 3637 switch (MI->getOpcode()) { 3638 default: break; 3639 case X86::MOV64r0: Opc = X86::MOV64mi32; break; 3640 case X86::MOV32r0: Opc = X86::MOV32mi; break; 3641 case X86::MOV16r0: Opc = X86::MOV16mi; break; 3642 case X86::MOV8r0: Opc = X86::MOV8mi; break; 3643 } 3644 if (Opc) 3645 NewMI = MakeM0Inst(*this, Opc, MOs, MI); 3646 if (NewMI) 3647 return NewMI; 3648 3649 OpcodeTablePtr = &RegOp2MemOpTable0; 3650 } else if (i == 1) { 3651 OpcodeTablePtr = &RegOp2MemOpTable1; 3652 } else if (i == 2) { 3653 OpcodeTablePtr = &RegOp2MemOpTable2; 3654 } else if (i == 3) { 3655 OpcodeTablePtr = &RegOp2MemOpTable3; 3656 } 3657 3658 // If table selected... 3659 if (OpcodeTablePtr) { 3660 // Find the Opcode to fuse 3661 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 3662 OpcodeTablePtr->find(MI->getOpcode()); 3663 if (I != OpcodeTablePtr->end()) { 3664 unsigned Opcode = I->second.first; 3665 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT; 3666 if (Align < MinAlign) 3667 return NULL; 3668 bool NarrowToMOV32rm = false; 3669 if (Size) { 3670 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize(); 3671 if (Size < RCSize) { 3672 // Check if it's safe to fold the load. If the size of the object is 3673 // narrower than the load width, then it's not. 3674 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 3675 return NULL; 3676 // If this is a 64-bit load, but the spill slot is 32, then we can do 3677 // a 32-bit load which is implicitly zero-extended. This likely is due 3678 // to liveintervalanalysis remat'ing a load from stack slot. 3679 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 3680 return NULL; 3681 Opcode = X86::MOV32rm; 3682 NarrowToMOV32rm = true; 3683 } 3684 } 3685 3686 if (isTwoAddrFold) 3687 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 3688 else 3689 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 3690 3691 if (NarrowToMOV32rm) { 3692 // If this is the special case where we use a MOV32rm to load a 32-bit 3693 // value and zero-extend the top bits. Change the destination register 3694 // to a 32-bit one. 3695 unsigned DstReg = NewMI->getOperand(0).getReg(); 3696 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 3697 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 3698 X86::sub_32bit)); 3699 else 3700 NewMI->getOperand(0).setSubReg(X86::sub_32bit); 3701 } 3702 return NewMI; 3703 } 3704 } 3705 3706 // No fusion 3707 if (PrintFailedFusing && !MI->isCopy()) 3708 dbgs() << "We failed to fuse operand " << i << " in " << *MI; 3709 return NULL; 3710} 3711 3712/// hasPartialRegUpdate - Return true for all instructions that only update 3713/// the first 32 or 64-bits of the destination register and leave the rest 3714/// unmodified. This can be used to avoid folding loads if the instructions 3715/// only update part of the destination register, and the non-updated part is 3716/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these 3717/// instructions breaks the partial register dependency and it can improve 3718/// performance. e.g.: 3719/// 3720/// movss (%rdi), %xmm0 3721/// cvtss2sd %xmm0, %xmm0 3722/// 3723/// Instead of 3724/// cvtss2sd (%rdi), %xmm0 3725/// 3726/// FIXME: This should be turned into a TSFlags. 3727/// 3728static bool hasPartialRegUpdate(unsigned Opcode) { 3729 switch (Opcode) { 3730 case X86::CVTSI2SSrr: 3731 case X86::CVTSI2SS64rr: 3732 case X86::CVTSI2SDrr: 3733 case X86::CVTSI2SD64rr: 3734 case X86::CVTSD2SSrr: 3735 case X86::Int_CVTSD2SSrr: 3736 case X86::CVTSS2SDrr: 3737 case X86::Int_CVTSS2SDrr: 3738 case X86::RCPSSr: 3739 case X86::RCPSSr_Int: 3740 case X86::ROUNDSDr: 3741 case X86::ROUNDSDr_Int: 3742 case X86::ROUNDSSr: 3743 case X86::ROUNDSSr_Int: 3744 case X86::RSQRTSSr: 3745 case X86::RSQRTSSr_Int: 3746 case X86::SQRTSSr: 3747 case X86::SQRTSSr_Int: 3748 // AVX encoded versions 3749 case X86::VCVTSD2SSrr: 3750 case X86::Int_VCVTSD2SSrr: 3751 case X86::VCVTSS2SDrr: 3752 case X86::Int_VCVTSS2SDrr: 3753 case X86::VRCPSSr: 3754 case X86::VROUNDSDr: 3755 case X86::VROUNDSDr_Int: 3756 case X86::VROUNDSSr: 3757 case X86::VROUNDSSr_Int: 3758 case X86::VRSQRTSSr: 3759 case X86::VSQRTSSr: 3760 return true; 3761 } 3762 3763 return false; 3764} 3765 3766/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle 3767/// instructions we would like before a partial register update. 3768unsigned X86InstrInfo:: 3769getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 3770 const TargetRegisterInfo *TRI) const { 3771 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode())) 3772 return 0; 3773 3774 // If MI is marked as reading Reg, the partial register update is wanted. 3775 const MachineOperand &MO = MI->getOperand(0); 3776 unsigned Reg = MO.getReg(); 3777 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 3778 if (MO.readsReg() || MI->readsVirtualRegister(Reg)) 3779 return 0; 3780 } else { 3781 if (MI->readsRegister(Reg, TRI)) 3782 return 0; 3783 } 3784 3785 // If any of the preceding 16 instructions are reading Reg, insert a 3786 // dependency breaking instruction. The magic number is based on a few 3787 // Nehalem experiments. 3788 return 16; 3789} 3790 3791void X86InstrInfo:: 3792breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 3793 const TargetRegisterInfo *TRI) const { 3794 unsigned Reg = MI->getOperand(OpNum).getReg(); 3795 if (X86::VR128RegClass.contains(Reg)) { 3796 // These instructions are all floating point domain, so xorps is the best 3797 // choice. 3798 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 3799 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr; 3800 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg) 3801 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); 3802 } else if (X86::VR256RegClass.contains(Reg)) { 3803 // Use vxorps to clear the full ymm register. 3804 // It wants to read and write the xmm sub-register. 3805 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm); 3806 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg) 3807 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef) 3808 .addReg(Reg, RegState::ImplicitDefine); 3809 } else 3810 return; 3811 MI->addRegisterKilled(Reg, TRI, true); 3812} 3813 3814MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3815 MachineInstr *MI, 3816 const SmallVectorImpl<unsigned> &Ops, 3817 int FrameIndex) const { 3818 // Check switch flag 3819 if (NoFusing) return NULL; 3820 3821 // Unless optimizing for size, don't fold to avoid partial 3822 // register update stalls 3823 if (!MF.getFunction()->getFnAttributes().hasOptimizeForSizeAttr() && 3824 hasPartialRegUpdate(MI->getOpcode())) 3825 return 0; 3826 3827 const MachineFrameInfo *MFI = MF.getFrameInfo(); 3828 unsigned Size = MFI->getObjectSize(FrameIndex); 3829 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 3830 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 3831 unsigned NewOpc = 0; 3832 unsigned RCSize = 0; 3833 switch (MI->getOpcode()) { 3834 default: return NULL; 3835 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 3836 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 3837 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 3838 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 3839 } 3840 // Check if it's safe to fold the load. If the size of the object is 3841 // narrower than the load width, then it's not. 3842 if (Size < RCSize) 3843 return NULL; 3844 // Change to CMPXXri r, 0 first. 3845 MI->setDesc(get(NewOpc)); 3846 MI->getOperand(1).ChangeToImmediate(0); 3847 } else if (Ops.size() != 1) 3848 return NULL; 3849 3850 SmallVector<MachineOperand,4> MOs; 3851 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 3852 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 3853} 3854 3855MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 3856 MachineInstr *MI, 3857 const SmallVectorImpl<unsigned> &Ops, 3858 MachineInstr *LoadMI) const { 3859 // Check switch flag 3860 if (NoFusing) return NULL; 3861 3862 // Unless optimizing for size, don't fold to avoid partial 3863 // register update stalls 3864 if (!MF.getFunction()->getFnAttributes().hasOptimizeForSizeAttr() && 3865 hasPartialRegUpdate(MI->getOpcode())) 3866 return 0; 3867 3868 // Determine the alignment of the load. 3869 unsigned Alignment = 0; 3870 if (LoadMI->hasOneMemOperand()) 3871 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 3872 else 3873 switch (LoadMI->getOpcode()) { 3874 case X86::AVX2_SETALLONES: 3875 case X86::AVX_SET0: 3876 Alignment = 32; 3877 break; 3878 case X86::V_SET0: 3879 case X86::V_SETALLONES: 3880 Alignment = 16; 3881 break; 3882 case X86::FsFLD0SD: 3883 Alignment = 8; 3884 break; 3885 case X86::FsFLD0SS: 3886 Alignment = 4; 3887 break; 3888 default: 3889 return 0; 3890 } 3891 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 3892 unsigned NewOpc = 0; 3893 switch (MI->getOpcode()) { 3894 default: return NULL; 3895 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 3896 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 3897 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 3898 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 3899 } 3900 // Change to CMPXXri r, 0 first. 3901 MI->setDesc(get(NewOpc)); 3902 MI->getOperand(1).ChangeToImmediate(0); 3903 } else if (Ops.size() != 1) 3904 return NULL; 3905 3906 // Make sure the subregisters match. 3907 // Otherwise we risk changing the size of the load. 3908 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg()) 3909 return NULL; 3910 3911 SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 3912 switch (LoadMI->getOpcode()) { 3913 case X86::V_SET0: 3914 case X86::V_SETALLONES: 3915 case X86::AVX2_SETALLONES: 3916 case X86::AVX_SET0: 3917 case X86::FsFLD0SD: 3918 case X86::FsFLD0SS: { 3919 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 3920 // Create a constant-pool entry and operands to load from it. 3921 3922 // Medium and large mode can't fold loads this way. 3923 if (TM.getCodeModel() != CodeModel::Small && 3924 TM.getCodeModel() != CodeModel::Kernel) 3925 return NULL; 3926 3927 // x86-32 PIC requires a PIC base register for constant pools. 3928 unsigned PICBase = 0; 3929 if (TM.getRelocationModel() == Reloc::PIC_) { 3930 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 3931 PICBase = X86::RIP; 3932 else 3933 // FIXME: PICBase = getGlobalBaseReg(&MF); 3934 // This doesn't work for several reasons. 3935 // 1. GlobalBaseReg may have been spilled. 3936 // 2. It may not be live at MI. 3937 return NULL; 3938 } 3939 3940 // Create a constant-pool entry. 3941 MachineConstantPool &MCP = *MF.getConstantPool(); 3942 Type *Ty; 3943 unsigned Opc = LoadMI->getOpcode(); 3944 if (Opc == X86::FsFLD0SS) 3945 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 3946 else if (Opc == X86::FsFLD0SD) 3947 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 3948 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0) 3949 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8); 3950 else 3951 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 3952 3953 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES); 3954 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) : 3955 Constant::getNullValue(Ty); 3956 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 3957 3958 // Create operands to load from the constant pool entry. 3959 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 3960 MOs.push_back(MachineOperand::CreateImm(1)); 3961 MOs.push_back(MachineOperand::CreateReg(0, false)); 3962 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 3963 MOs.push_back(MachineOperand::CreateReg(0, false)); 3964 break; 3965 } 3966 default: { 3967 if ((LoadMI->getOpcode() == X86::MOVSSrm || 3968 LoadMI->getOpcode() == X86::VMOVSSrm) && 3969 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize() 3970 > 4) 3971 // These instructions only load 32 bits, we can't fold them if the 3972 // destination register is wider than 32 bits (4 bytes). 3973 return NULL; 3974 if ((LoadMI->getOpcode() == X86::MOVSDrm || 3975 LoadMI->getOpcode() == X86::VMOVSDrm) && 3976 MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize() 3977 > 8) 3978 // These instructions only load 64 bits, we can't fold them if the 3979 // destination register is wider than 64 bits (8 bytes). 3980 return NULL; 3981 3982 // Folding a normal load. Just copy the load's address operands. 3983 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 3984 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i) 3985 MOs.push_back(LoadMI->getOperand(i)); 3986 break; 3987 } 3988 } 3989 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 3990} 3991 3992 3993bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 3994 const SmallVectorImpl<unsigned> &Ops) const { 3995 // Check switch flag 3996 if (NoFusing) return 0; 3997 3998 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 3999 switch (MI->getOpcode()) { 4000 default: return false; 4001 case X86::TEST8rr: 4002 case X86::TEST16rr: 4003 case X86::TEST32rr: 4004 case X86::TEST64rr: 4005 return true; 4006 case X86::ADD32ri: 4007 // FIXME: AsmPrinter doesn't know how to handle 4008 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. 4009 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS) 4010 return false; 4011 break; 4012 } 4013 } 4014 4015 if (Ops.size() != 1) 4016 return false; 4017 4018 unsigned OpNum = Ops[0]; 4019 unsigned Opc = MI->getOpcode(); 4020 unsigned NumOps = MI->getDesc().getNumOperands(); 4021 bool isTwoAddr = NumOps > 1 && 4022 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; 4023 4024 // Folding a memory location into the two-address part of a two-address 4025 // instruction is different than folding it other places. It requires 4026 // replacing the *two* registers with the memory location. 4027 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 4028 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 4029 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 4030 } else if (OpNum == 0) { // If operand 0 4031 switch (Opc) { 4032 case X86::MOV8r0: 4033 case X86::MOV16r0: 4034 case X86::MOV32r0: 4035 case X86::MOV64r0: return true; 4036 default: break; 4037 } 4038 OpcodeTablePtr = &RegOp2MemOpTable0; 4039 } else if (OpNum == 1) { 4040 OpcodeTablePtr = &RegOp2MemOpTable1; 4041 } else if (OpNum == 2) { 4042 OpcodeTablePtr = &RegOp2MemOpTable2; 4043 } else if (OpNum == 3) { 4044 OpcodeTablePtr = &RegOp2MemOpTable3; 4045 } 4046 4047 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc)) 4048 return true; 4049 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops); 4050} 4051 4052bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 4053 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 4054 SmallVectorImpl<MachineInstr*> &NewMIs) const { 4055 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4056 MemOp2RegOpTable.find(MI->getOpcode()); 4057 if (I == MemOp2RegOpTable.end()) 4058 return false; 4059 unsigned Opc = I->second.first; 4060 unsigned Index = I->second.second & TB_INDEX_MASK; 4061 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4062 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4063 if (UnfoldLoad && !FoldedLoad) 4064 return false; 4065 UnfoldLoad &= FoldedLoad; 4066 if (UnfoldStore && !FoldedStore) 4067 return false; 4068 UnfoldStore &= FoldedStore; 4069 4070 const MCInstrDesc &MCID = get(Opc); 4071 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4072 if (!MI->hasOneMemOperand() && 4073 RC == &X86::VR128RegClass && 4074 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4075 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 4076 // conservatively assume the address is unaligned. That's bad for 4077 // performance. 4078 return false; 4079 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 4080 SmallVector<MachineOperand,2> BeforeOps; 4081 SmallVector<MachineOperand,2> AfterOps; 4082 SmallVector<MachineOperand,4> ImpOps; 4083 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 4084 MachineOperand &Op = MI->getOperand(i); 4085 if (i >= Index && i < Index + X86::AddrNumOperands) 4086 AddrOps.push_back(Op); 4087 else if (Op.isReg() && Op.isImplicit()) 4088 ImpOps.push_back(Op); 4089 else if (i < Index) 4090 BeforeOps.push_back(Op); 4091 else if (i > Index) 4092 AfterOps.push_back(Op); 4093 } 4094 4095 // Emit the load instruction. 4096 if (UnfoldLoad) { 4097 std::pair<MachineInstr::mmo_iterator, 4098 MachineInstr::mmo_iterator> MMOs = 4099 MF.extractLoadMemRefs(MI->memoperands_begin(), 4100 MI->memoperands_end()); 4101 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 4102 if (UnfoldStore) { 4103 // Address operands cannot be marked isKill. 4104 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 4105 MachineOperand &MO = NewMIs[0]->getOperand(i); 4106 if (MO.isReg()) 4107 MO.setIsKill(false); 4108 } 4109 } 4110 } 4111 4112 // Emit the data processing instruction. 4113 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true); 4114 MachineInstrBuilder MIB(DataMI); 4115 4116 if (FoldedStore) 4117 MIB.addReg(Reg, RegState::Define); 4118 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 4119 MIB.addOperand(BeforeOps[i]); 4120 if (FoldedLoad) 4121 MIB.addReg(Reg); 4122 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 4123 MIB.addOperand(AfterOps[i]); 4124 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 4125 MachineOperand &MO = ImpOps[i]; 4126 MIB.addReg(MO.getReg(), 4127 getDefRegState(MO.isDef()) | 4128 RegState::Implicit | 4129 getKillRegState(MO.isKill()) | 4130 getDeadRegState(MO.isDead()) | 4131 getUndefRegState(MO.isUndef())); 4132 } 4133 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 4134 switch (DataMI->getOpcode()) { 4135 default: break; 4136 case X86::CMP64ri32: 4137 case X86::CMP64ri8: 4138 case X86::CMP32ri: 4139 case X86::CMP32ri8: 4140 case X86::CMP16ri: 4141 case X86::CMP16ri8: 4142 case X86::CMP8ri: { 4143 MachineOperand &MO0 = DataMI->getOperand(0); 4144 MachineOperand &MO1 = DataMI->getOperand(1); 4145 if (MO1.getImm() == 0) { 4146 unsigned NewOpc; 4147 switch (DataMI->getOpcode()) { 4148 default: llvm_unreachable("Unreachable!"); 4149 case X86::CMP64ri8: 4150 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 4151 case X86::CMP32ri8: 4152 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 4153 case X86::CMP16ri8: 4154 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 4155 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 4156 } 4157 DataMI->setDesc(get(NewOpc)); 4158 MO1.ChangeToRegister(MO0.getReg(), false); 4159 } 4160 } 4161 } 4162 NewMIs.push_back(DataMI); 4163 4164 // Emit the store instruction. 4165 if (UnfoldStore) { 4166 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF); 4167 std::pair<MachineInstr::mmo_iterator, 4168 MachineInstr::mmo_iterator> MMOs = 4169 MF.extractStoreMemRefs(MI->memoperands_begin(), 4170 MI->memoperands_end()); 4171 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 4172 } 4173 4174 return true; 4175} 4176 4177bool 4178X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 4179 SmallVectorImpl<SDNode*> &NewNodes) const { 4180 if (!N->isMachineOpcode()) 4181 return false; 4182 4183 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4184 MemOp2RegOpTable.find(N->getMachineOpcode()); 4185 if (I == MemOp2RegOpTable.end()) 4186 return false; 4187 unsigned Opc = I->second.first; 4188 unsigned Index = I->second.second & TB_INDEX_MASK; 4189 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4190 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4191 const MCInstrDesc &MCID = get(Opc); 4192 MachineFunction &MF = DAG.getMachineFunction(); 4193 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF); 4194 unsigned NumDefs = MCID.NumDefs; 4195 std::vector<SDValue> AddrOps; 4196 std::vector<SDValue> BeforeOps; 4197 std::vector<SDValue> AfterOps; 4198 DebugLoc dl = N->getDebugLoc(); 4199 unsigned NumOps = N->getNumOperands(); 4200 for (unsigned i = 0; i != NumOps-1; ++i) { 4201 SDValue Op = N->getOperand(i); 4202 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 4203 AddrOps.push_back(Op); 4204 else if (i < Index-NumDefs) 4205 BeforeOps.push_back(Op); 4206 else if (i > Index-NumDefs) 4207 AfterOps.push_back(Op); 4208 } 4209 SDValue Chain = N->getOperand(NumOps-1); 4210 AddrOps.push_back(Chain); 4211 4212 // Emit the load instruction. 4213 SDNode *Load = 0; 4214 if (FoldedLoad) { 4215 EVT VT = *RC->vt_begin(); 4216 std::pair<MachineInstr::mmo_iterator, 4217 MachineInstr::mmo_iterator> MMOs = 4218 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4219 cast<MachineSDNode>(N)->memoperands_end()); 4220 if (!(*MMOs.first) && 4221 RC == &X86::VR128RegClass && 4222 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4223 // Do not introduce a slow unaligned load. 4224 return false; 4225 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4226 bool isAligned = (*MMOs.first) && 4227 (*MMOs.first)->getAlignment() >= Alignment; 4228 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, 4229 VT, MVT::Other, &AddrOps[0], AddrOps.size()); 4230 NewNodes.push_back(Load); 4231 4232 // Preserve memory reference information. 4233 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4234 } 4235 4236 // Emit the data processing instruction. 4237 std::vector<EVT> VTs; 4238 const TargetRegisterClass *DstRC = 0; 4239 if (MCID.getNumDefs() > 0) { 4240 DstRC = getRegClass(MCID, 0, &RI, MF); 4241 VTs.push_back(*DstRC->vt_begin()); 4242 } 4243 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 4244 EVT VT = N->getValueType(i); 4245 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) 4246 VTs.push_back(VT); 4247 } 4248 if (Load) 4249 BeforeOps.push_back(SDValue(Load, 0)); 4250 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 4251 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0], 4252 BeforeOps.size()); 4253 NewNodes.push_back(NewNode); 4254 4255 // Emit the store instruction. 4256 if (FoldedStore) { 4257 AddrOps.pop_back(); 4258 AddrOps.push_back(SDValue(NewNode, 0)); 4259 AddrOps.push_back(Chain); 4260 std::pair<MachineInstr::mmo_iterator, 4261 MachineInstr::mmo_iterator> MMOs = 4262 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 4263 cast<MachineSDNode>(N)->memoperands_end()); 4264 if (!(*MMOs.first) && 4265 RC == &X86::VR128RegClass && 4266 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 4267 // Do not introduce a slow unaligned store. 4268 return false; 4269 unsigned Alignment = RC->getSize() == 32 ? 32 : 16; 4270 bool isAligned = (*MMOs.first) && 4271 (*MMOs.first)->getAlignment() >= Alignment; 4272 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, 4273 isAligned, TM), 4274 dl, MVT::Other, 4275 &AddrOps[0], AddrOps.size()); 4276 NewNodes.push_back(Store); 4277 4278 // Preserve memory reference information. 4279 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 4280 } 4281 4282 return true; 4283} 4284 4285unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 4286 bool UnfoldLoad, bool UnfoldStore, 4287 unsigned *LoadRegIndex) const { 4288 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 4289 MemOp2RegOpTable.find(Opc); 4290 if (I == MemOp2RegOpTable.end()) 4291 return 0; 4292 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD; 4293 bool FoldedStore = I->second.second & TB_FOLDED_STORE; 4294 if (UnfoldLoad && !FoldedLoad) 4295 return 0; 4296 if (UnfoldStore && !FoldedStore) 4297 return 0; 4298 if (LoadRegIndex) 4299 *LoadRegIndex = I->second.second & TB_INDEX_MASK; 4300 return I->second.first; 4301} 4302 4303bool 4304X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 4305 int64_t &Offset1, int64_t &Offset2) const { 4306 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 4307 return false; 4308 unsigned Opc1 = Load1->getMachineOpcode(); 4309 unsigned Opc2 = Load2->getMachineOpcode(); 4310 switch (Opc1) { 4311 default: return false; 4312 case X86::MOV8rm: 4313 case X86::MOV16rm: 4314 case X86::MOV32rm: 4315 case X86::MOV64rm: 4316 case X86::LD_Fp32m: 4317 case X86::LD_Fp64m: 4318 case X86::LD_Fp80m: 4319 case X86::MOVSSrm: 4320 case X86::MOVSDrm: 4321 case X86::MMX_MOVD64rm: 4322 case X86::MMX_MOVQ64rm: 4323 case X86::FsMOVAPSrm: 4324 case X86::FsMOVAPDrm: 4325 case X86::MOVAPSrm: 4326 case X86::MOVUPSrm: 4327 case X86::MOVAPDrm: 4328 case X86::MOVDQArm: 4329 case X86::MOVDQUrm: 4330 // AVX load instructions 4331 case X86::VMOVSSrm: 4332 case X86::VMOVSDrm: 4333 case X86::FsVMOVAPSrm: 4334 case X86::FsVMOVAPDrm: 4335 case X86::VMOVAPSrm: 4336 case X86::VMOVUPSrm: 4337 case X86::VMOVAPDrm: 4338 case X86::VMOVDQArm: 4339 case X86::VMOVDQUrm: 4340 case X86::VMOVAPSYrm: 4341 case X86::VMOVUPSYrm: 4342 case X86::VMOVAPDYrm: 4343 case X86::VMOVDQAYrm: 4344 case X86::VMOVDQUYrm: 4345 break; 4346 } 4347 switch (Opc2) { 4348 default: return false; 4349 case X86::MOV8rm: 4350 case X86::MOV16rm: 4351 case X86::MOV32rm: 4352 case X86::MOV64rm: 4353 case X86::LD_Fp32m: 4354 case X86::LD_Fp64m: 4355 case X86::LD_Fp80m: 4356 case X86::MOVSSrm: 4357 case X86::MOVSDrm: 4358 case X86::MMX_MOVD64rm: 4359 case X86::MMX_MOVQ64rm: 4360 case X86::FsMOVAPSrm: 4361 case X86::FsMOVAPDrm: 4362 case X86::MOVAPSrm: 4363 case X86::MOVUPSrm: 4364 case X86::MOVAPDrm: 4365 case X86::MOVDQArm: 4366 case X86::MOVDQUrm: 4367 // AVX load instructions 4368 case X86::VMOVSSrm: 4369 case X86::VMOVSDrm: 4370 case X86::FsVMOVAPSrm: 4371 case X86::FsVMOVAPDrm: 4372 case X86::VMOVAPSrm: 4373 case X86::VMOVUPSrm: 4374 case X86::VMOVAPDrm: 4375 case X86::VMOVDQArm: 4376 case X86::VMOVDQUrm: 4377 case X86::VMOVAPSYrm: 4378 case X86::VMOVUPSYrm: 4379 case X86::VMOVAPDYrm: 4380 case X86::VMOVDQAYrm: 4381 case X86::VMOVDQUYrm: 4382 break; 4383 } 4384 4385 // Check if chain operands and base addresses match. 4386 if (Load1->getOperand(0) != Load2->getOperand(0) || 4387 Load1->getOperand(5) != Load2->getOperand(5)) 4388 return false; 4389 // Segment operands should match as well. 4390 if (Load1->getOperand(4) != Load2->getOperand(4)) 4391 return false; 4392 // Scale should be 1, Index should be Reg0. 4393 if (Load1->getOperand(1) == Load2->getOperand(1) && 4394 Load1->getOperand(2) == Load2->getOperand(2)) { 4395 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 4396 return false; 4397 4398 // Now let's examine the displacements. 4399 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 4400 isa<ConstantSDNode>(Load2->getOperand(3))) { 4401 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 4402 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 4403 return true; 4404 } 4405 } 4406 return false; 4407} 4408 4409bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 4410 int64_t Offset1, int64_t Offset2, 4411 unsigned NumLoads) const { 4412 assert(Offset2 > Offset1); 4413 if ((Offset2 - Offset1) / 8 > 64) 4414 return false; 4415 4416 unsigned Opc1 = Load1->getMachineOpcode(); 4417 unsigned Opc2 = Load2->getMachineOpcode(); 4418 if (Opc1 != Opc2) 4419 return false; // FIXME: overly conservative? 4420 4421 switch (Opc1) { 4422 default: break; 4423 case X86::LD_Fp32m: 4424 case X86::LD_Fp64m: 4425 case X86::LD_Fp80m: 4426 case X86::MMX_MOVD64rm: 4427 case X86::MMX_MOVQ64rm: 4428 return false; 4429 } 4430 4431 EVT VT = Load1->getValueType(0); 4432 switch (VT.getSimpleVT().SimpleTy) { 4433 default: 4434 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 4435 // have 16 of them to play with. 4436 if (TM.getSubtargetImpl()->is64Bit()) { 4437 if (NumLoads >= 3) 4438 return false; 4439 } else if (NumLoads) { 4440 return false; 4441 } 4442 break; 4443 case MVT::i8: 4444 case MVT::i16: 4445 case MVT::i32: 4446 case MVT::i64: 4447 case MVT::f32: 4448 case MVT::f64: 4449 if (NumLoads) 4450 return false; 4451 break; 4452 } 4453 4454 return true; 4455} 4456 4457 4458bool X86InstrInfo:: 4459ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 4460 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 4461 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 4462 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 4463 return true; 4464 Cond[0].setImm(GetOppositeBranchCondition(CC)); 4465 return false; 4466} 4467 4468bool X86InstrInfo:: 4469isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 4470 // FIXME: Return false for x87 stack register classes for now. We can't 4471 // allow any loads of these registers before FpGet_ST0_80. 4472 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 4473 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 4474} 4475 4476/// getGlobalBaseReg - Return a virtual register initialized with the 4477/// the global base register value. Output instructions required to 4478/// initialize the register in the function entry block, if necessary. 4479/// 4480/// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 4481/// 4482unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 4483 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 4484 "X86-64 PIC uses RIP relative addressing"); 4485 4486 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 4487 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 4488 if (GlobalBaseReg != 0) 4489 return GlobalBaseReg; 4490 4491 // Create the register. The code to initialize it is inserted 4492 // later, by the CGBR pass (below). 4493 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 4494 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 4495 X86FI->setGlobalBaseReg(GlobalBaseReg); 4496 return GlobalBaseReg; 4497} 4498 4499// These are the replaceable SSE instructions. Some of these have Int variants 4500// that we don't include here. We don't want to replace instructions selected 4501// by intrinsics. 4502static const uint16_t ReplaceableInstrs[][3] = { 4503 //PackedSingle PackedDouble PackedInt 4504 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 4505 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 4506 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 4507 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 4508 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 4509 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 4510 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 4511 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 4512 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 4513 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 4514 { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 4515 { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 4516 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 4517 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 4518 // AVX 128-bit support 4519 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr }, 4520 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm }, 4521 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr }, 4522 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr }, 4523 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm }, 4524 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr }, 4525 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm }, 4526 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr }, 4527 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm }, 4528 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr }, 4529 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm }, 4530 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr }, 4531 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm }, 4532 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr }, 4533 // AVX 256-bit support 4534 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr }, 4535 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm }, 4536 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr }, 4537 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr }, 4538 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm }, 4539 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr } 4540}; 4541 4542static const uint16_t ReplaceableInstrsAVX2[][3] = { 4543 //PackedSingle PackedDouble PackedInt 4544 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm }, 4545 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr }, 4546 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm }, 4547 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr }, 4548 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm }, 4549 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr }, 4550 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm }, 4551 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }, 4552 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr }, 4553 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr }, 4554 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm }, 4555 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr }, 4556 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm }, 4557 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr } 4558}; 4559 4560// FIXME: Some shuffle and unpack instructions have equivalents in different 4561// domains, but they require a bit more work than just switching opcodes. 4562 4563static const uint16_t *lookup(unsigned opcode, unsigned domain) { 4564 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i) 4565 if (ReplaceableInstrs[i][domain-1] == opcode) 4566 return ReplaceableInstrs[i]; 4567 return 0; 4568} 4569 4570static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) { 4571 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i) 4572 if (ReplaceableInstrsAVX2[i][domain-1] == opcode) 4573 return ReplaceableInstrsAVX2[i]; 4574 return 0; 4575} 4576 4577std::pair<uint16_t, uint16_t> 4578X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const { 4579 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 4580 bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2(); 4581 uint16_t validDomains = 0; 4582 if (domain && lookup(MI->getOpcode(), domain)) 4583 validDomains = 0xe; 4584 else if (domain && lookupAVX2(MI->getOpcode(), domain)) 4585 validDomains = hasAVX2 ? 0xe : 0x6; 4586 return std::make_pair(domain, validDomains); 4587} 4588 4589void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { 4590 assert(Domain>0 && Domain<4 && "Invalid execution domain"); 4591 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 4592 assert(dom && "Not an SSE instruction"); 4593 const uint16_t *table = lookup(MI->getOpcode(), dom); 4594 if (!table) { // try the other table 4595 assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) && 4596 "256-bit vector operations only available in AVX2"); 4597 table = lookupAVX2(MI->getOpcode(), dom); 4598 } 4599 assert(table && "Cannot change domain"); 4600 MI->setDesc(get(table[Domain-1])); 4601} 4602 4603/// getNoopForMachoTarget - Return the noop instruction to use for a noop. 4604void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 4605 NopInst.setOpcode(X86::NOOP); 4606} 4607 4608bool X86InstrInfo::isHighLatencyDef(int opc) const { 4609 switch (opc) { 4610 default: return false; 4611 case X86::DIVSDrm: 4612 case X86::DIVSDrm_Int: 4613 case X86::DIVSDrr: 4614 case X86::DIVSDrr_Int: 4615 case X86::DIVSSrm: 4616 case X86::DIVSSrm_Int: 4617 case X86::DIVSSrr: 4618 case X86::DIVSSrr_Int: 4619 case X86::SQRTPDm: 4620 case X86::SQRTPDm_Int: 4621 case X86::SQRTPDr: 4622 case X86::SQRTPDr_Int: 4623 case X86::SQRTPSm: 4624 case X86::SQRTPSm_Int: 4625 case X86::SQRTPSr: 4626 case X86::SQRTPSr_Int: 4627 case X86::SQRTSDm: 4628 case X86::SQRTSDm_Int: 4629 case X86::SQRTSDr: 4630 case X86::SQRTSDr_Int: 4631 case X86::SQRTSSm: 4632 case X86::SQRTSSm_Int: 4633 case X86::SQRTSSr: 4634 case X86::SQRTSSr_Int: 4635 // AVX instructions with high latency 4636 case X86::VDIVSDrm: 4637 case X86::VDIVSDrm_Int: 4638 case X86::VDIVSDrr: 4639 case X86::VDIVSDrr_Int: 4640 case X86::VDIVSSrm: 4641 case X86::VDIVSSrm_Int: 4642 case X86::VDIVSSrr: 4643 case X86::VDIVSSrr_Int: 4644 case X86::VSQRTPDm: 4645 case X86::VSQRTPDm_Int: 4646 case X86::VSQRTPDr: 4647 case X86::VSQRTPDr_Int: 4648 case X86::VSQRTPSm: 4649 case X86::VSQRTPSm_Int: 4650 case X86::VSQRTPSr: 4651 case X86::VSQRTPSr_Int: 4652 case X86::VSQRTSDm: 4653 case X86::VSQRTSDm_Int: 4654 case X86::VSQRTSDr: 4655 case X86::VSQRTSSm: 4656 case X86::VSQRTSSm_Int: 4657 case X86::VSQRTSSr: 4658 return true; 4659 } 4660} 4661 4662bool X86InstrInfo:: 4663hasHighOperandLatency(const InstrItineraryData *ItinData, 4664 const MachineRegisterInfo *MRI, 4665 const MachineInstr *DefMI, unsigned DefIdx, 4666 const MachineInstr *UseMI, unsigned UseIdx) const { 4667 return isHighLatencyDef(DefMI->getOpcode()); 4668} 4669 4670namespace { 4671 /// CGBR - Create Global Base Reg pass. This initializes the PIC 4672 /// global base register for x86-32. 4673 struct CGBR : public MachineFunctionPass { 4674 static char ID; 4675 CGBR() : MachineFunctionPass(ID) {} 4676 4677 virtual bool runOnMachineFunction(MachineFunction &MF) { 4678 const X86TargetMachine *TM = 4679 static_cast<const X86TargetMachine *>(&MF.getTarget()); 4680 4681 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() && 4682 "X86-64 PIC uses RIP relative addressing"); 4683 4684 // Only emit a global base reg in PIC mode. 4685 if (TM->getRelocationModel() != Reloc::PIC_) 4686 return false; 4687 4688 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 4689 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 4690 4691 // If we didn't need a GlobalBaseReg, don't insert code. 4692 if (GlobalBaseReg == 0) 4693 return false; 4694 4695 // Insert the set of GlobalBaseReg into the first MBB of the function 4696 MachineBasicBlock &FirstMBB = MF.front(); 4697 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 4698 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 4699 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4700 const X86InstrInfo *TII = TM->getInstrInfo(); 4701 4702 unsigned PC; 4703 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) 4704 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass); 4705 else 4706 PC = GlobalBaseReg; 4707 4708 // Operand of MovePCtoStack is completely ignored by asm printer. It's 4709 // only used in JIT code emission as displacement to pc. 4710 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 4711 4712 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 4713 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 4714 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) { 4715 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 4716 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 4717 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 4718 X86II::MO_GOT_ABSOLUTE_ADDRESS); 4719 } 4720 4721 return true; 4722 } 4723 4724 virtual const char *getPassName() const { 4725 return "X86 PIC Global Base Reg Initialization"; 4726 } 4727 4728 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 4729 AU.setPreservesCFG(); 4730 MachineFunctionPass::getAnalysisUsage(AU); 4731 } 4732 }; 4733} 4734 4735char CGBR::ID = 0; 4736FunctionPass* 4737llvm::createGlobalBaseRegPass() { return new CGBR(); } 4738 4739namespace { 4740 struct LDTLSCleanup : public MachineFunctionPass { 4741 static char ID; 4742 LDTLSCleanup() : MachineFunctionPass(ID) {} 4743 4744 virtual bool runOnMachineFunction(MachineFunction &MF) { 4745 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>(); 4746 if (MFI->getNumLocalDynamicTLSAccesses() < 2) { 4747 // No point folding accesses if there isn't at least two. 4748 return false; 4749 } 4750 4751 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>(); 4752 return VisitNode(DT->getRootNode(), 0); 4753 } 4754 4755 // Visit the dominator subtree rooted at Node in pre-order. 4756 // If TLSBaseAddrReg is non-null, then use that to replace any 4757 // TLS_base_addr instructions. Otherwise, create the register 4758 // when the first such instruction is seen, and then use it 4759 // as we encounter more instructions. 4760 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) { 4761 MachineBasicBlock *BB = Node->getBlock(); 4762 bool Changed = false; 4763 4764 // Traverse the current block. 4765 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; 4766 ++I) { 4767 switch (I->getOpcode()) { 4768 case X86::TLS_base_addr32: 4769 case X86::TLS_base_addr64: 4770 if (TLSBaseAddrReg) 4771 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg); 4772 else 4773 I = SetRegister(I, &TLSBaseAddrReg); 4774 Changed = true; 4775 break; 4776 default: 4777 break; 4778 } 4779 } 4780 4781 // Visit the children of this block in the dominator tree. 4782 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end(); 4783 I != E; ++I) { 4784 Changed |= VisitNode(*I, TLSBaseAddrReg); 4785 } 4786 4787 return Changed; 4788 } 4789 4790 // Replace the TLS_base_addr instruction I with a copy from 4791 // TLSBaseAddrReg, returning the new instruction. 4792 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I, 4793 unsigned TLSBaseAddrReg) { 4794 MachineFunction *MF = I->getParent()->getParent(); 4795 const X86TargetMachine *TM = 4796 static_cast<const X86TargetMachine *>(&MF->getTarget()); 4797 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 4798 const X86InstrInfo *TII = TM->getInstrInfo(); 4799 4800 // Insert a Copy from TLSBaseAddrReg to RAX/EAX. 4801 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(), 4802 TII->get(TargetOpcode::COPY), 4803 is64Bit ? X86::RAX : X86::EAX) 4804 .addReg(TLSBaseAddrReg); 4805 4806 // Erase the TLS_base_addr instruction. 4807 I->eraseFromParent(); 4808 4809 return Copy; 4810 } 4811 4812 // Create a virtal register in *TLSBaseAddrReg, and populate it by 4813 // inserting a copy instruction after I. Returns the new instruction. 4814 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) { 4815 MachineFunction *MF = I->getParent()->getParent(); 4816 const X86TargetMachine *TM = 4817 static_cast<const X86TargetMachine *>(&MF->getTarget()); 4818 const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit(); 4819 const X86InstrInfo *TII = TM->getInstrInfo(); 4820 4821 // Create a virtual register for the TLS base address. 4822 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 4823 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit 4824 ? &X86::GR64RegClass 4825 : &X86::GR32RegClass); 4826 4827 // Insert a copy from RAX/EAX to TLSBaseAddrReg. 4828 MachineInstr *Next = I->getNextNode(); 4829 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(), 4830 TII->get(TargetOpcode::COPY), 4831 *TLSBaseAddrReg) 4832 .addReg(is64Bit ? X86::RAX : X86::EAX); 4833 4834 return Copy; 4835 } 4836 4837 virtual const char *getPassName() const { 4838 return "Local Dynamic TLS Access Clean-up"; 4839 } 4840 4841 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 4842 AU.setPreservesCFG(); 4843 AU.addRequired<MachineDominatorTree>(); 4844 MachineFunctionPass::getAnalysisUsage(AU); 4845 } 4846 }; 4847} 4848 4849char LDTLSCleanup::ID = 0; 4850FunctionPass* 4851llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); } 4852