Searched refs:FNEG (Results 1 - 17 of 17) sorted by relevance

/macosx-10.9.5/BerkeleyDB-21/db/java/src/com/sleepycat/asm/
H A DOpcodes.java211 int FNEG = 118; // - field in interface:Opcodes
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/
H A DISDOpcodes.h451 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
455 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator in enum:llvm::ISD::NodeType
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp59 // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB
207 case ISD::FNEG:
269 else if (Node->getOpcode() == ISD::FNEG)
H A DLegalizeFloatTypes.cpp81 case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break;
343 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
864 case ISD::FNEG: ExpandFloatRes_FNEG(N, Lo, Hi); break;
905 DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo),
1055 Lo = DAG.getNode(ISD::FNEG, dl, Lo.getValueType(), Lo);
1056 Hi = DAG.getNode(ISD::FNEG, dl, Hi.getValueType(), Hi);
H A DSelectionDAGDumper.cpp139 case ISD::FNEG: return "fneg";
H A DDAGCombiner.cpp399 if (Op.getOpcode() == ISD::FNEG) return 2;
461 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
1150 case ISD::FNEG: return visitFNEG(N);
5438 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) ||
5447 if (N0.getOpcode() == ISD::FNEG)
5862 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5863 return DAG.getNode(ISD::FNEG, dl, VT, N1);
5901 DAG.getNode(ISD::FNEG, dl, VT, N1));
5908 DAG.getNode(ISD::FNEG, dl, VT,
5914 if (N0.getOpcode() == ISD::FNEG
[all...]
H A DLegalizeDAG.cpp1549 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
3014 case ISD::FNEG:
3015 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3028 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3140 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3142 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
H A DLegalizeVectorTypes.cpp81 case ISD::FNEG:
516 case ISD::FNEG:
1362 case ISD::FNEG:
H A DFastISel.cpp861 // If the target has ISD::FNEG, use it.
864 ISD::FNEG, OpReg, OpRegIsKill);
H A DSelectionDAG.cpp2482 case ISD::FNEG:
2665 case ISD::FNEG:
2670 if (OpOpcode == ISD::FNEG) // --X -> X
2674 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
H A DSelectionDAGBuilder.cpp2629 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1161 setOperationAction(ISD::FNEG, MVT::f32, Legal);
1162 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1272 setOperationAction(ISD::FNEG, MVT::f32, Expand);
1273 setOperationAction(ISD::FNEG, MVT::f64, Expand);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/
H A DX86ISelLowering.cpp588 // Use XORP to simulate FNEG.
589 setOperationAction(ISD::FNEG , MVT::f64, Custom);
590 setOperationAction(ISD::FNEG , MVT::f32, Custom);
619 // Use XORP to simulate FNEG.
620 setOperationAction(ISD::FNEG , MVT::f32, Custom);
726 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
838 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
872 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
1039 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1048 setOperationAction(ISD::FNEG, MV
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/
H A DSPUISelDAGToDAG.cpp784 } else if (Opc == ISD::FNEG
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMipsISelLowering.cpp275 setOperationAction(ISD::FNEG, MVT::f32, Expand);
276 setOperationAction(ISD::FNEG, MVT::f64, Expand);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/
H A DPPCISelLowering.cpp349 setOperationAction(ISD::FNEG, VT, Expand);
3837 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DARMISelLowering.cpp487 // FIXME: Create unittest for FNEG and for FABS.
488 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);

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