/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/MC/ |
H A D | MCInstrItineraries.h | 201 /// index DefIdx can be bypassed when it's read by an instruction of 203 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, argument 207 if ((FirstDefIdx + DefIdx) >= LastDefIdx) 209 if (Forwardings[FirstDefIdx + DefIdx] == 0) 217 return Forwardings[FirstDefIdx + DefIdx] == 224 int getOperandLatency(unsigned DefClass, unsigned DefIdx, argument 229 int DefCycle = getOperandCycle(DefClass, DefIdx); 239 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
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H A D | MCSubtargetInfo.h | 103 unsigned DefIdx) const { 104 assert(DefIdx < SC->NumWriteLatencyEntries && 105 "MachineModel does not specify a WriteResource for DefIdx"); 107 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
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/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 111 unsigned DefIdx = 0; local 115 ++DefIdx; 117 return DefIdx; 175 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); local 176 if (DefIdx < SCDesc->NumWriteLatencyEntries) { 179 STI->getWriteLatencyEntry(SCDesc, DefIdx); 192 // If DefIdx does not exist in the model (e.g. implicit defs), then return 199 ss << "DefIdx " << DefIdx << " exceeds machine model writes for " 217 for (unsigned DefIdx [all...] |
H A D | TargetInstrInfoImpl.cpp | 517 SDNode *DefNode, unsigned DefIdx, 527 return ItinData->getOperandCycle(DefClass, DefIdx); 529 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 589 unsigned DefIdx) const { 594 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 602 const MachineInstr *DefMI, unsigned DefIdx, 606 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 649 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or 653 const MachineInstr *DefMI, unsigned DefIdx, 665 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseM 516 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument 601 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 652 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx, bool FindMin) const argument [all...] |
H A D | LiveRangeEdit.cpp | 122 SlotIndex DefIdx; 124 DefIdx = LIS.getInstructionIndex(RM.OrigMI); 126 DefIdx = RM.ParentVNI->def; 127 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx); 136 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
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H A D | LiveRangeCalc.cpp | 90 unsigned DefIdx; local 94 } else if (MI->isRegTiedToDefOperand(I.getOperandNo(), &DefIdx)) { 97 if (MI->getOperand(DefIdx).isEarlyClobber())
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H A D | MachineInstr.cpp | 735 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); local 736 if (DefIdx != -1) 737 tieOperands(DefIdx, OpNo); 1022 unsigned DefIdx; 1023 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 1024 OpIdx = DefIdx; 1160 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. 1172 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { 1173 MachineOperand &DefMO = getOperand(DefIdx); 1175 assert(DefMO.isDef() && "DefIdx mus [all...] |
H A D | MachineVerifier.cpp | 860 unsigned DefIdx; local 862 MI->isRegTiedToDefOperand(MONum, &DefIdx) && 863 Reg != MI->getOperand(DefIdx).getReg()) 1056 SlotIndex DefIdx = LiveInts->getInstructionIndex(MI); local 1057 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber()); 1060 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) { 1062 if (VNI->def != DefIdx) { 1065 << DefIdx << " in " << LI << '\n'; 1069 *OS << DefIdx << " i [all...] |
H A D | InlineSpiller.cpp | 888 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM, local 890 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' 891 << *LIS.getInstructionFromIndex(DefIdx)); 903 VNInfo *DefVNI = NewLI.getNextValue(DefIdx, LIS.getVNInfoAllocator()); 904 NewLI.addRange(LiveRange(DefIdx, UseIdx.getRegSlot(), DefVNI));
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H A D | RegisterCoalescer.cpp | 580 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg); local 581 assert(DefIdx != -1); 583 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) 683 SlotIndex DefIdx = UseIdx.getRegSlot(); local 684 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx); 687 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI); 688 assert(DVNI->def == DefIdx);
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H A D | MachineLICM.cpp | 200 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, 1010 unsigned DefIdx, unsigned Reg) const { 1029 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, UseMI, i)) 1009 HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, unsigned Reg) const argument
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H A D | RegAllocFast.cpp | 725 unsigned DefIdx = 0; local 726 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue; 728 << DefIdx << ".\n"); local
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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/ |
H A D | TargetSchedule.h | 105 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
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H A D | MachineInstr.h | 797 /// tieOperands - Add a tie between the register operands at DefIdx and 803 void tieOperands(unsigned DefIdx, unsigned UseIdx);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.h | 225 const MachineInstr *DefMI, unsigned DefIdx, 229 SDNode *DefNode, unsigned DefIdx, 250 unsigned DefIdx, unsigned DefAlign) const; 254 unsigned DefIdx, unsigned DefAlign) const; 265 unsigned DefIdx, unsigned DefAlign, 278 const MachineInstr *DefMI, unsigned DefIdx, 281 const MachineInstr *DefMI, unsigned DefIdx) const;
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H A D | ARMBaseInstrInfo.cpp | 2760 unsigned DefIdx, unsigned DefAlign) const { 2761 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2764 return ItinData->getOperandCycle(DefClass, DefIdx); 2801 unsigned DefIdx, unsigned DefAlign) const { 2802 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; 2805 return ItinData->getOperandCycle(DefClass, DefIdx); 2904 unsigned DefIdx, unsigned DefAlign, 2910 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 2911 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 2920 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); 2757 getVLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument 2798 getLDMDefCycle(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const argument 2902 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument 3013 getBundledDefMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &DefIdx, unsigned &Dist) argument 3250 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3339 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const argument 3622 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 779 SDNode *DefNode, unsigned DefIdx, 791 const MachineInstr *DefMI, unsigned DefIdx, 800 const MachineInstr *DefMI, unsigned DefIdx, 833 const MachineInstr *DefMI, unsigned DefIdx, 842 const MachineInstr *DefMI, unsigned DefIdx) const = 0; 1001 SDNode *DefNode, unsigned DefIdx, 1016 const MachineInstr *DefMI, unsigned DefIdx) const; 1019 const MachineInstr *DefMI, unsigned DefIdx, 831 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.h | 135 unsigned DefIdx; member in class:llvm::ScheduleDAGSDNodes::RegDefIter 153 return DefIdx-1;
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H A D | ScheduleDAGSDNodes.cpp | 547 DefIdx = 0; 553 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { 561 for (;DefIdx < NodeNumDefs; ++DefIdx) { 562 if (!Node->hasAnyUseOfValue(DefIdx)) 564 ValueType = Node->getValueType(DefIdx); 565 ++DefIdx; 627 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); 631 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
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H A D | InstrEmitter.cpp | 957 unsigned DefIdx = GroupIdx[DefGroup] + 1; 960 MI->tieOperands(DefIdx + j, UseIdx + j);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
H A D | X86InstrInfo.h | 375 const MachineInstr *DefMI, unsigned DefIdx,
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H A D | X86InstrInfo.cpp | 4665 const MachineInstr *DefMI, unsigned DefIdx, 4663 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument
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