1//===-- llvm/CodeGen/TargetSchedule.h - Sched Machine Model -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines a wrapper around MCSchedModel that allows the interface to
11// benefit from information currently only available in TargetInstrInfo.
12// Ideally, the scheduling interface would be fully defined in the MC layer.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_TARGET_TARGETSCHEDMODEL_H
17#define LLVM_TARGET_TARGETSCHEDMODEL_H
18
19#include "llvm/MC/MCSchedule.h"
20#include "llvm/MC/MCInstrItineraries.h"
21
22namespace llvm {
23
24class TargetRegisterInfo;
25class TargetSubtargetInfo;
26class TargetInstrInfo;
27class MachineInstr;
28
29/// Provide an instruction scheduling machine model to CodeGen passes.
30class TargetSchedModel {
31  // For efficiency, hold a copy of the statically defined MCSchedModel for this
32  // processor.
33  MCSchedModel SchedModel;
34  InstrItineraryData InstrItins;
35  const TargetSubtargetInfo *STI;
36  const TargetInstrInfo *TII;
37public:
38  TargetSchedModel(): STI(0), TII(0) {}
39
40  /// \brief Initialize the machine model for instruction scheduling.
41  ///
42  /// The machine model API keeps a copy of the top-level MCSchedModel table
43  /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
44  /// dynamic properties.
45  void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
46            const TargetInstrInfo *tii);
47
48  /// \brief TargetInstrInfo getter.
49  const TargetInstrInfo *getInstrInfo() const { return TII; }
50
51  /// \brief Return true if this machine model includes an instruction-level
52  /// scheduling model.
53  ///
54  /// This is more detailed than the course grain IssueWidth and default
55  /// latency properties, but separate from the per-cycle itinerary data.
56  bool hasInstrSchedModel() const;
57
58  const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
59
60  /// \brief Return true if this machine model includes cycle-to-cycle itinerary
61  /// data.
62  ///
63  /// This models scheduling at each stage in the processor pipeline.
64  bool hasInstrItineraries() const;
65
66  const InstrItineraryData *getInstrItineraries() const {
67    if (hasInstrItineraries())
68      return &InstrItins;
69    return 0;
70  }
71
72  /// \brief Identify the processor corresponding to the current subtarget.
73  unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
74
75  /// \brief Maximum number of micro-ops that may be scheduled per cycle.
76  unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
77
78  /// \brief Return the number of issue slots required for this MI.
79  unsigned getNumMicroOps(MachineInstr *MI) const;
80
81  /// \brief Compute operand latency based on the available machine model.
82  ///
83  /// Computes and return the latency of the given data dependent def and use
84  /// when the operand indices are already known. UseMI may be NULL for an
85  /// unknown user.
86  ///
87  /// FindMin may be set to get the minimum vs. expected latency. Minimum
88  /// latency is used for scheduling groups, while expected latency is for
89  /// instruction cost and critical path.
90  unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
91                                 const MachineInstr *UseMI, unsigned UseOperIdx,
92                                 bool FindMin) const;
93
94  /// \brief Compute the instruction latency based on the available machine
95  /// model.
96  ///
97  /// Compute and return the expected latency of this instruction independent of
98  /// a particular use. computeOperandLatency is the prefered API, but this is
99  /// occasionally useful to help estimate instruction cost.
100  unsigned computeInstrLatency(const MachineInstr *MI) const;
101
102  /// \brief Output dependency latency of a pair of defs of the same register.
103  ///
104  /// This is typically one cycle.
105  unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
106                                const MachineInstr *DepMI) const;
107
108
109private:
110  /// getDefLatency is a helper for computeOperandLatency. Return the
111  /// instruction's latency if operand lookup is not required.
112  /// Otherwise return -1.
113  int getDefLatency(const MachineInstr *DefMI, bool FindMin) const;
114
115  /// Return the MCSchedClassDesc for this instruction.
116  const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
117};
118
119} // namespace llvm
120
121#endif
122