1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Methods common to all machine instructions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineInstr.h" 15#include "llvm/Constants.h" 16#include "llvm/DebugInfo.h" 17#include "llvm/Function.h" 18#include "llvm/InlineAsm.h" 19#include "llvm/LLVMContext.h" 20#include "llvm/Metadata.h" 21#include "llvm/Module.h" 22#include "llvm/Type.h" 23#include "llvm/Value.h" 24#include "llvm/Assembly/Writer.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFunction.h" 27#include "llvm/CodeGen/MachineMemOperand.h" 28#include "llvm/CodeGen/MachineModuleInfo.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/CodeGen/PseudoSourceValue.h" 31#include "llvm/MC/MCInstrDesc.h" 32#include "llvm/MC/MCSymbol.h" 33#include "llvm/Target/TargetMachine.h" 34#include "llvm/Target/TargetInstrInfo.h" 35#include "llvm/Target/TargetRegisterInfo.h" 36#include "llvm/Analysis/AliasAnalysis.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39#include "llvm/Support/LeakDetector.h" 40#include "llvm/Support/MathExtras.h" 41#include "llvm/Support/raw_ostream.h" 42#include "llvm/ADT/FoldingSet.h" 43#include "llvm/ADT/Hashing.h" 44using namespace llvm; 45 46//===----------------------------------------------------------------------===// 47// MachineOperand Implementation 48//===----------------------------------------------------------------------===// 49 50void MachineOperand::setReg(unsigned Reg) { 51 if (getReg() == Reg) return; // No change. 52 53 // Otherwise, we have to change the register. If this operand is embedded 54 // into a machine function, we need to update the old and new register's 55 // use/def lists. 56 if (MachineInstr *MI = getParent()) 57 if (MachineBasicBlock *MBB = MI->getParent()) 58 if (MachineFunction *MF = MBB->getParent()) { 59 MachineRegisterInfo &MRI = MF->getRegInfo(); 60 MRI.removeRegOperandFromUseList(this); 61 SmallContents.RegNo = Reg; 62 MRI.addRegOperandToUseList(this); 63 return; 64 } 65 66 // Otherwise, just change the register, no problem. :) 67 SmallContents.RegNo = Reg; 68} 69 70void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, 71 const TargetRegisterInfo &TRI) { 72 assert(TargetRegisterInfo::isVirtualRegister(Reg)); 73 if (SubIdx && getSubReg()) 74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 75 setReg(Reg); 76 if (SubIdx) 77 setSubReg(SubIdx); 78} 79 80void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { 81 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 82 if (getSubReg()) { 83 Reg = TRI.getSubReg(Reg, getSubReg()); 84 // Note that getSubReg() may return 0 if the sub-register doesn't exist. 85 // That won't happen in legal code. 86 setSubReg(0); 87 } 88 setReg(Reg); 89} 90 91/// Change a def to a use, or a use to a def. 92void MachineOperand::setIsDef(bool Val) { 93 assert(isReg() && "Wrong MachineOperand accessor"); 94 assert((!Val || !isDebug()) && "Marking a debug operation as def"); 95 if (IsDef == Val) 96 return; 97 // MRI may keep uses and defs in different list positions. 98 if (MachineInstr *MI = getParent()) 99 if (MachineBasicBlock *MBB = MI->getParent()) 100 if (MachineFunction *MF = MBB->getParent()) { 101 MachineRegisterInfo &MRI = MF->getRegInfo(); 102 MRI.removeRegOperandFromUseList(this); 103 IsDef = Val; 104 MRI.addRegOperandToUseList(this); 105 return; 106 } 107 IsDef = Val; 108} 109 110/// ChangeToImmediate - Replace this operand with a new immediate operand of 111/// the specified value. If an operand is known to be an immediate already, 112/// the setImm method should be used. 113void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 114 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); 115 // If this operand is currently a register operand, and if this is in a 116 // function, deregister the operand from the register's use/def list. 117 if (isReg() && isOnRegUseList()) 118 if (MachineInstr *MI = getParent()) 119 if (MachineBasicBlock *MBB = MI->getParent()) 120 if (MachineFunction *MF = MBB->getParent()) 121 MF->getRegInfo().removeRegOperandFromUseList(this); 122 123 OpKind = MO_Immediate; 124 Contents.ImmVal = ImmVal; 125} 126 127/// ChangeToRegister - Replace this operand with a new register operand of 128/// the specified value. If an operand is known to be an register already, 129/// the setReg method should be used. 130void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 131 bool isKill, bool isDead, bool isUndef, 132 bool isDebug) { 133 MachineRegisterInfo *RegInfo = 0; 134 if (MachineInstr *MI = getParent()) 135 if (MachineBasicBlock *MBB = MI->getParent()) 136 if (MachineFunction *MF = MBB->getParent()) 137 RegInfo = &MF->getRegInfo(); 138 // If this operand is already a register operand, remove it from the 139 // register's use/def lists. 140 bool WasReg = isReg(); 141 if (RegInfo && WasReg) 142 RegInfo->removeRegOperandFromUseList(this); 143 144 // Change this to a register and set the reg#. 145 OpKind = MO_Register; 146 SmallContents.RegNo = Reg; 147 SubReg = 0; 148 IsDef = isDef; 149 IsImp = isImp; 150 IsKill = isKill; 151 IsDead = isDead; 152 IsUndef = isUndef; 153 IsInternalRead = false; 154 IsEarlyClobber = false; 155 IsDebug = isDebug; 156 // Ensure isOnRegUseList() returns false. 157 Contents.Reg.Prev = 0; 158 // Preserve the tie when the operand was already a register. 159 if (!WasReg) 160 TiedTo = 0; 161 162 // If this operand is embedded in a function, add the operand to the 163 // register's use/def list. 164 if (RegInfo) 165 RegInfo->addRegOperandToUseList(this); 166} 167 168/// isIdenticalTo - Return true if this operand is identical to the specified 169/// operand. Note that this should stay in sync with the hash_value overload 170/// below. 171bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 172 if (getType() != Other.getType() || 173 getTargetFlags() != Other.getTargetFlags()) 174 return false; 175 176 switch (getType()) { 177 case MachineOperand::MO_Register: 178 return getReg() == Other.getReg() && isDef() == Other.isDef() && 179 getSubReg() == Other.getSubReg(); 180 case MachineOperand::MO_Immediate: 181 return getImm() == Other.getImm(); 182 case MachineOperand::MO_CImmediate: 183 return getCImm() == Other.getCImm(); 184 case MachineOperand::MO_FPImmediate: 185 return getFPImm() == Other.getFPImm(); 186 case MachineOperand::MO_MachineBasicBlock: 187 return getMBB() == Other.getMBB(); 188 case MachineOperand::MO_FrameIndex: 189 return getIndex() == Other.getIndex(); 190 case MachineOperand::MO_ConstantPoolIndex: 191 case MachineOperand::MO_TargetIndex: 192 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 193 case MachineOperand::MO_JumpTableIndex: 194 return getIndex() == Other.getIndex(); 195 case MachineOperand::MO_GlobalAddress: 196 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 197 case MachineOperand::MO_ExternalSymbol: 198 return !strcmp(getSymbolName(), Other.getSymbolName()) && 199 getOffset() == Other.getOffset(); 200 case MachineOperand::MO_BlockAddress: 201 return getBlockAddress() == Other.getBlockAddress() && 202 getOffset() == Other.getOffset(); 203 case MO_RegisterMask: 204 return getRegMask() == Other.getRegMask(); 205 case MachineOperand::MO_MCSymbol: 206 return getMCSymbol() == Other.getMCSymbol(); 207 case MachineOperand::MO_Metadata: 208 return getMetadata() == Other.getMetadata(); 209 } 210 llvm_unreachable("Invalid machine operand type"); 211} 212 213// Note: this must stay exactly in sync with isIdenticalTo above. 214hash_code llvm::hash_value(const MachineOperand &MO) { 215 switch (MO.getType()) { 216 case MachineOperand::MO_Register: 217 // Register operands don't have target flags. 218 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); 219 case MachineOperand::MO_Immediate: 220 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm()); 221 case MachineOperand::MO_CImmediate: 222 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm()); 223 case MachineOperand::MO_FPImmediate: 224 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm()); 225 case MachineOperand::MO_MachineBasicBlock: 226 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB()); 227 case MachineOperand::MO_FrameIndex: 228 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); 229 case MachineOperand::MO_ConstantPoolIndex: 230 case MachineOperand::MO_TargetIndex: 231 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(), 232 MO.getOffset()); 233 case MachineOperand::MO_JumpTableIndex: 234 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); 235 case MachineOperand::MO_ExternalSymbol: 236 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(), 237 MO.getSymbolName()); 238 case MachineOperand::MO_GlobalAddress: 239 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(), 240 MO.getOffset()); 241 case MachineOperand::MO_BlockAddress: 242 return hash_combine(MO.getType(), MO.getTargetFlags(), 243 MO.getBlockAddress(), MO.getOffset()); 244 case MachineOperand::MO_RegisterMask: 245 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask()); 246 case MachineOperand::MO_Metadata: 247 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata()); 248 case MachineOperand::MO_MCSymbol: 249 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol()); 250 } 251 llvm_unreachable("Invalid machine operand type"); 252} 253 254/// print - Print the specified machine operand. 255/// 256void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 257 // If the instruction is embedded into a basic block, we can find the 258 // target info for the instruction. 259 if (!TM) 260 if (const MachineInstr *MI = getParent()) 261 if (const MachineBasicBlock *MBB = MI->getParent()) 262 if (const MachineFunction *MF = MBB->getParent()) 263 TM = &MF->getTarget(); 264 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; 265 266 switch (getType()) { 267 case MachineOperand::MO_Register: 268 OS << PrintReg(getReg(), TRI, getSubReg()); 269 270 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 271 isInternalRead() || isEarlyClobber() || isTied()) { 272 OS << '<'; 273 bool NeedComma = false; 274 if (isDef()) { 275 if (NeedComma) OS << ','; 276 if (isEarlyClobber()) 277 OS << "earlyclobber,"; 278 if (isImplicit()) 279 OS << "imp-"; 280 OS << "def"; 281 NeedComma = true; 282 // <def,read-undef> only makes sense when getSubReg() is set. 283 // Don't clutter the output otherwise. 284 if (isUndef() && getSubReg()) 285 OS << ",read-undef"; 286 } else if (isImplicit()) { 287 OS << "imp-use"; 288 NeedComma = true; 289 } 290 291 if (isKill()) { 292 if (NeedComma) OS << ','; 293 OS << "kill"; 294 NeedComma = true; 295 } 296 if (isDead()) { 297 if (NeedComma) OS << ','; 298 OS << "dead"; 299 NeedComma = true; 300 } 301 if (isUndef() && isUse()) { 302 if (NeedComma) OS << ','; 303 OS << "undef"; 304 NeedComma = true; 305 } 306 if (isInternalRead()) { 307 if (NeedComma) OS << ','; 308 OS << "internal"; 309 NeedComma = true; 310 } 311 if (isTied()) { 312 if (NeedComma) OS << ','; 313 OS << "tied"; 314 if (TiedTo != 15) 315 OS << unsigned(TiedTo - 1); 316 NeedComma = true; 317 } 318 OS << '>'; 319 } 320 break; 321 case MachineOperand::MO_Immediate: 322 OS << getImm(); 323 break; 324 case MachineOperand::MO_CImmediate: 325 getCImm()->getValue().print(OS, false); 326 break; 327 case MachineOperand::MO_FPImmediate: 328 if (getFPImm()->getType()->isFloatTy()) 329 OS << getFPImm()->getValueAPF().convertToFloat(); 330 else 331 OS << getFPImm()->getValueAPF().convertToDouble(); 332 break; 333 case MachineOperand::MO_MachineBasicBlock: 334 OS << "<BB#" << getMBB()->getNumber() << ">"; 335 break; 336 case MachineOperand::MO_FrameIndex: 337 OS << "<fi#" << getIndex() << '>'; 338 break; 339 case MachineOperand::MO_ConstantPoolIndex: 340 OS << "<cp#" << getIndex(); 341 if (getOffset()) OS << "+" << getOffset(); 342 OS << '>'; 343 break; 344 case MachineOperand::MO_TargetIndex: 345 OS << "<ti#" << getIndex(); 346 if (getOffset()) OS << "+" << getOffset(); 347 OS << '>'; 348 break; 349 case MachineOperand::MO_JumpTableIndex: 350 OS << "<jt#" << getIndex() << '>'; 351 break; 352 case MachineOperand::MO_GlobalAddress: 353 OS << "<ga:"; 354 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false); 355 if (getOffset()) OS << "+" << getOffset(); 356 OS << '>'; 357 break; 358 case MachineOperand::MO_ExternalSymbol: 359 OS << "<es:" << getSymbolName(); 360 if (getOffset()) OS << "+" << getOffset(); 361 OS << '>'; 362 break; 363 case MachineOperand::MO_BlockAddress: 364 OS << '<'; 365 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 366 if (getOffset()) OS << "+" << getOffset(); 367 OS << '>'; 368 break; 369 case MachineOperand::MO_RegisterMask: 370 OS << "<regmask>"; 371 break; 372 case MachineOperand::MO_Metadata: 373 OS << '<'; 374 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false); 375 OS << '>'; 376 break; 377 case MachineOperand::MO_MCSymbol: 378 OS << "<MCSym=" << *getMCSymbol() << '>'; 379 break; 380 } 381 382 if (unsigned TF = getTargetFlags()) 383 OS << "[TF=" << TF << ']'; 384} 385 386//===----------------------------------------------------------------------===// 387// MachineMemOperand Implementation 388//===----------------------------------------------------------------------===// 389 390/// getAddrSpace - Return the LLVM IR address space number that this pointer 391/// points into. 392unsigned MachinePointerInfo::getAddrSpace() const { 393 if (V == 0) return 0; 394 return cast<PointerType>(V->getType())->getAddressSpace(); 395} 396 397/// getConstantPool - Return a MachinePointerInfo record that refers to the 398/// constant pool. 399MachinePointerInfo MachinePointerInfo::getConstantPool() { 400 return MachinePointerInfo(PseudoSourceValue::getConstantPool()); 401} 402 403/// getFixedStack - Return a MachinePointerInfo record that refers to the 404/// the specified FrameIndex. 405MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) { 406 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset); 407} 408 409MachinePointerInfo MachinePointerInfo::getJumpTable() { 410 return MachinePointerInfo(PseudoSourceValue::getJumpTable()); 411} 412 413MachinePointerInfo MachinePointerInfo::getGOT() { 414 return MachinePointerInfo(PseudoSourceValue::getGOT()); 415} 416 417MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) { 418 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset); 419} 420 421MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f, 422 uint64_t s, unsigned int a, 423 const MDNode *TBAAInfo, 424 const MDNode *Ranges) 425 : PtrInfo(ptrinfo), Size(s), 426 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)), 427 TBAAInfo(TBAAInfo), Ranges(Ranges) { 428 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) && 429 "invalid pointer value"); 430 assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 431 assert((isLoad() || isStore()) && "Not a load/store!"); 432} 433 434/// Profile - Gather unique data for the object. 435/// 436void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 437 ID.AddInteger(getOffset()); 438 ID.AddInteger(Size); 439 ID.AddPointer(getValue()); 440 ID.AddInteger(Flags); 441} 442 443void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 444 // The Value and Offset may differ due to CSE. But the flags and size 445 // should be the same. 446 assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 447 assert(MMO->getSize() == getSize() && "Size mismatch!"); 448 449 if (MMO->getBaseAlignment() >= getBaseAlignment()) { 450 // Update the alignment value. 451 Flags = (Flags & ((1 << MOMaxBits) - 1)) | 452 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits); 453 // Also update the base and offset, because the new alignment may 454 // not be applicable with the old ones. 455 PtrInfo = MMO->PtrInfo; 456 } 457} 458 459/// getAlignment - Return the minimum known alignment in bytes of the 460/// actual memory reference. 461uint64_t MachineMemOperand::getAlignment() const { 462 return MinAlign(getBaseAlignment(), getOffset()); 463} 464 465raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 466 assert((MMO.isLoad() || MMO.isStore()) && 467 "SV has to be a load, store or both."); 468 469 if (MMO.isVolatile()) 470 OS << "Volatile "; 471 472 if (MMO.isLoad()) 473 OS << "LD"; 474 if (MMO.isStore()) 475 OS << "ST"; 476 OS << MMO.getSize(); 477 478 // Print the address information. 479 OS << "["; 480 if (!MMO.getValue()) 481 OS << "<unknown>"; 482 else 483 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 484 485 // If the alignment of the memory reference itself differs from the alignment 486 // of the base pointer, print the base alignment explicitly, next to the base 487 // pointer. 488 if (MMO.getBaseAlignment() != MMO.getAlignment()) 489 OS << "(align=" << MMO.getBaseAlignment() << ")"; 490 491 if (MMO.getOffset() != 0) 492 OS << "+" << MMO.getOffset(); 493 OS << "]"; 494 495 // Print the alignment of the reference. 496 if (MMO.getBaseAlignment() != MMO.getAlignment() || 497 MMO.getBaseAlignment() != MMO.getSize()) 498 OS << "(align=" << MMO.getAlignment() << ")"; 499 500 // Print TBAA info. 501 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) { 502 OS << "(tbaa="; 503 if (TBAAInfo->getNumOperands() > 0) 504 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false); 505 else 506 OS << "<unknown>"; 507 OS << ")"; 508 } 509 510 // Print nontemporal info. 511 if (MMO.isNonTemporal()) 512 OS << "(nontemporal)"; 513 514 return OS; 515} 516 517//===----------------------------------------------------------------------===// 518// MachineInstr Implementation 519//===----------------------------------------------------------------------===// 520 521/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 522/// MCID NULL and no operands. 523MachineInstr::MachineInstr() 524 : MCID(0), Flags(0), AsmPrinterFlags(0), 525 NumMemRefs(0), MemRefs(0), 526 Parent(0) { 527 // Make sure that we get added to a machine basicblock 528 LeakDetector::addGarbageObject(this); 529} 530 531void MachineInstr::addImplicitDefUseOperands() { 532 if (MCID->ImplicitDefs) 533 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 534 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 535 if (MCID->ImplicitUses) 536 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses) 537 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 538} 539 540/// MachineInstr ctor - This constructor creates a MachineInstr and adds the 541/// implicit operands. It reserves space for the number of operands specified by 542/// the MCInstrDesc. 543MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp) 544 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 545 NumMemRefs(0), MemRefs(0), Parent(0) { 546 unsigned NumImplicitOps = 0; 547 if (!NoImp) 548 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 549 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 550 if (!NoImp) 551 addImplicitDefUseOperands(); 552 // Make sure that we get added to a machine basicblock 553 LeakDetector::addGarbageObject(this); 554} 555 556/// MachineInstr ctor - As above, but with a DebugLoc. 557MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl, 558 bool NoImp) 559 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 560 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) { 561 unsigned NumImplicitOps = 0; 562 if (!NoImp) 563 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 564 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 565 if (!NoImp) 566 addImplicitDefUseOperands(); 567 // Make sure that we get added to a machine basicblock 568 LeakDetector::addGarbageObject(this); 569} 570 571/// MachineInstr ctor - Work exactly the same as the ctor two above, except 572/// that the MachineInstr is created and added to the end of the specified 573/// basic block. 574MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid) 575 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 576 NumMemRefs(0), MemRefs(0), Parent(0) { 577 assert(MBB && "Cannot use inserting ctor with null basic block!"); 578 unsigned NumImplicitOps = 579 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 580 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 581 addImplicitDefUseOperands(); 582 // Make sure that we get added to a machine basicblock 583 LeakDetector::addGarbageObject(this); 584 MBB->push_back(this); // Add instruction to end of basic block! 585} 586 587/// MachineInstr ctor - As above, but with a DebugLoc. 588/// 589MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, 590 const MCInstrDesc &tid) 591 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 592 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) { 593 assert(MBB && "Cannot use inserting ctor with null basic block!"); 594 unsigned NumImplicitOps = 595 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 596 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 597 addImplicitDefUseOperands(); 598 // Make sure that we get added to a machine basicblock 599 LeakDetector::addGarbageObject(this); 600 MBB->push_back(this); // Add instruction to end of basic block! 601} 602 603/// MachineInstr ctor - Copies MachineInstr arg exactly 604/// 605MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 606 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0), 607 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs), 608 Parent(0), debugLoc(MI.getDebugLoc()) { 609 Operands.reserve(MI.getNumOperands()); 610 611 // Add operands 612 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 613 addOperand(MI.getOperand(i)); 614 615 // Copy all the flags. 616 Flags = MI.Flags; 617 618 // Set parent to null. 619 Parent = 0; 620 621 LeakDetector::addGarbageObject(this); 622} 623 624MachineInstr::~MachineInstr() { 625 LeakDetector::removeGarbageObject(this); 626#ifndef NDEBUG 627 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 628 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 629 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 630 "Reg operand def/use list corrupted"); 631 } 632#endif 633} 634 635/// getRegInfo - If this instruction is embedded into a MachineFunction, 636/// return the MachineRegisterInfo object for the current function, otherwise 637/// return null. 638MachineRegisterInfo *MachineInstr::getRegInfo() { 639 if (MachineBasicBlock *MBB = getParent()) 640 return &MBB->getParent()->getRegInfo(); 641 return 0; 642} 643 644/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 645/// this instruction from their respective use lists. This requires that the 646/// operands already be on their use lists. 647void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { 648 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 649 if (Operands[i].isReg()) 650 MRI.removeRegOperandFromUseList(&Operands[i]); 651} 652 653/// AddRegOperandsToUseLists - Add all of the register operands in 654/// this instruction from their respective use lists. This requires that the 655/// operands not be on their use lists yet. 656void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { 657 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 658 if (Operands[i].isReg()) 659 MRI.addRegOperandToUseList(&Operands[i]); 660} 661 662/// addOperand - Add the specified operand to the instruction. If it is an 663/// implicit operand, it is added to the end of the operand list. If it is 664/// an explicit operand it is added at the end of the explicit operand list 665/// (before the first implicit operand). 666void MachineInstr::addOperand(const MachineOperand &Op) { 667 assert(MCID && "Cannot add operands before providing an instr descriptor"); 668 bool isImpReg = Op.isReg() && Op.isImplicit(); 669 MachineRegisterInfo *RegInfo = getRegInfo(); 670 671 // If the Operands backing store is reallocated, all register operands must 672 // be removed and re-added to RegInfo. It is storing pointers to operands. 673 bool Reallocate = RegInfo && 674 !Operands.empty() && Operands.size() == Operands.capacity(); 675 676 // Find the insert location for the new operand. Implicit registers go at 677 // the end, everything goes before the implicit regs. 678 unsigned OpNo = Operands.size(); 679 680 // Remove all the implicit operands from RegInfo if they need to be shifted. 681 // FIXME: Allow mixed explicit and implicit operands on inline asm. 682 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as 683 // implicit-defs, but they must not be moved around. See the FIXME in 684 // InstrEmitter.cpp. 685 if (!isImpReg && !isInlineAsm()) { 686 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { 687 --OpNo; 688 assert(!Operands[OpNo].isTied() && "Cannot move tied operands"); 689 if (RegInfo) 690 RegInfo->removeRegOperandFromUseList(&Operands[OpNo]); 691 } 692 } 693 694 // OpNo now points as the desired insertion point. Unless this is a variadic 695 // instruction, only implicit regs are allowed beyond MCID->getNumOperands(). 696 // RegMask operands go between the explicit and implicit operands. 697 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || 698 OpNo < MCID->getNumOperands()) && 699 "Trying to add an operand to a machine instr that is already done!"); 700 701 // All operands from OpNo have been removed from RegInfo. If the Operands 702 // backing store needs to be reallocated, we also need to remove any other 703 // register operands. 704 if (Reallocate) 705 for (unsigned i = 0; i != OpNo; ++i) 706 if (Operands[i].isReg()) 707 RegInfo->removeRegOperandFromUseList(&Operands[i]); 708 709 // Insert the new operand at OpNo. 710 Operands.insert(Operands.begin() + OpNo, Op); 711 Operands[OpNo].ParentMI = this; 712 713 // The Operands backing store has now been reallocated, so we can re-add the 714 // operands before OpNo. 715 if (Reallocate) 716 for (unsigned i = 0; i != OpNo; ++i) 717 if (Operands[i].isReg()) 718 RegInfo->addRegOperandToUseList(&Operands[i]); 719 720 // When adding a register operand, tell RegInfo about it. 721 if (Operands[OpNo].isReg()) { 722 // Ensure isOnRegUseList() returns false, regardless of Op's status. 723 Operands[OpNo].Contents.Reg.Prev = 0; 724 // Ignore existing ties. This is not a property that can be copied. 725 Operands[OpNo].TiedTo = 0; 726 // Add the new operand to RegInfo. 727 if (RegInfo) 728 RegInfo->addRegOperandToUseList(&Operands[OpNo]); 729 // The MCID operand information isn't accurate until we start adding 730 // explicit operands. The implicit operands are added first, then the 731 // explicits are inserted before them. 732 if (!isImpReg) { 733 // Tie uses to defs as indicated in MCInstrDesc. 734 if (Operands[OpNo].isUse()) { 735 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); 736 if (DefIdx != -1) 737 tieOperands(DefIdx, OpNo); 738 } 739 // If the register operand is flagged as early, mark the operand as such. 740 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) 741 Operands[OpNo].setIsEarlyClobber(true); 742 } 743 } 744 745 // Re-add all the implicit ops. 746 if (RegInfo) { 747 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) { 748 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 749 RegInfo->addRegOperandToUseList(&Operands[i]); 750 } 751 } 752} 753 754/// RemoveOperand - Erase an operand from an instruction, leaving it with one 755/// fewer operand than it started with. 756/// 757void MachineInstr::RemoveOperand(unsigned OpNo) { 758 assert(OpNo < Operands.size() && "Invalid operand number"); 759 untieRegOperand(OpNo); 760 MachineRegisterInfo *RegInfo = getRegInfo(); 761 762 // Special case removing the last one. 763 if (OpNo == Operands.size()-1) { 764 // If needed, remove from the reg def/use list. 765 if (RegInfo && Operands.back().isReg() && Operands.back().isOnRegUseList()) 766 RegInfo->removeRegOperandFromUseList(&Operands.back()); 767 768 Operands.pop_back(); 769 return; 770 } 771 772 // Otherwise, we are removing an interior operand. If we have reginfo to 773 // update, remove all operands that will be shifted down from their reg lists, 774 // move everything down, then re-add them. 775 if (RegInfo) { 776 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 777 if (Operands[i].isReg()) 778 RegInfo->removeRegOperandFromUseList(&Operands[i]); 779 } 780 } 781 782#ifndef NDEBUG 783 // Moving tied operands would break the ties. 784 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) 785 if (Operands[i].isReg()) 786 assert(!Operands[i].isTied() && "Cannot move tied operands"); 787#endif 788 789 Operands.erase(Operands.begin()+OpNo); 790 791 if (RegInfo) { 792 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 793 if (Operands[i].isReg()) 794 RegInfo->addRegOperandToUseList(&Operands[i]); 795 } 796 } 797} 798 799/// addMemOperand - Add a MachineMemOperand to the machine instruction. 800/// This function should be used only occasionally. The setMemRefs function 801/// is the primary method for setting up a MachineInstr's MemRefs list. 802void MachineInstr::addMemOperand(MachineFunction &MF, 803 MachineMemOperand *MO) { 804 mmo_iterator OldMemRefs = MemRefs; 805 uint16_t OldNumMemRefs = NumMemRefs; 806 807 uint16_t NewNum = NumMemRefs + 1; 808 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 809 810 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs); 811 NewMemRefs[NewNum - 1] = MO; 812 813 MemRefs = NewMemRefs; 814 NumMemRefs = NewNum; 815} 816 817bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const { 818 const MachineBasicBlock *MBB = getParent(); 819 MachineBasicBlock::const_instr_iterator MII = *this; ++MII; 820 while (MII != MBB->end() && MII->isInsideBundle()) { 821 if (MII->getDesc().getFlags() & Mask) { 822 if (Type == AnyInBundle) 823 return true; 824 } else { 825 if (Type == AllInBundle) 826 return false; 827 } 828 ++MII; 829 } 830 831 return Type == AllInBundle; 832} 833 834bool MachineInstr::isIdenticalTo(const MachineInstr *Other, 835 MICheckType Check) const { 836 // If opcodes or number of operands are not the same then the two 837 // instructions are obviously not identical. 838 if (Other->getOpcode() != getOpcode() || 839 Other->getNumOperands() != getNumOperands()) 840 return false; 841 842 if (isBundle()) { 843 // Both instructions are bundles, compare MIs inside the bundle. 844 MachineBasicBlock::const_instr_iterator I1 = *this; 845 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end(); 846 MachineBasicBlock::const_instr_iterator I2 = *Other; 847 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end(); 848 while (++I1 != E1 && I1->isInsideBundle()) { 849 ++I2; 850 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check)) 851 return false; 852 } 853 } 854 855 // Check operands to make sure they match. 856 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 857 const MachineOperand &MO = getOperand(i); 858 const MachineOperand &OMO = Other->getOperand(i); 859 if (!MO.isReg()) { 860 if (!MO.isIdenticalTo(OMO)) 861 return false; 862 continue; 863 } 864 865 // Clients may or may not want to ignore defs when testing for equality. 866 // For example, machine CSE pass only cares about finding common 867 // subexpressions, so it's safe to ignore virtual register defs. 868 if (MO.isDef()) { 869 if (Check == IgnoreDefs) 870 continue; 871 else if (Check == IgnoreVRegDefs) { 872 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || 873 TargetRegisterInfo::isPhysicalRegister(OMO.getReg())) 874 if (MO.getReg() != OMO.getReg()) 875 return false; 876 } else { 877 if (!MO.isIdenticalTo(OMO)) 878 return false; 879 if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) 880 return false; 881 } 882 } else { 883 if (!MO.isIdenticalTo(OMO)) 884 return false; 885 if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) 886 return false; 887 } 888 } 889 // If DebugLoc does not match then two dbg.values are not identical. 890 if (isDebugValue()) 891 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown() 892 && getDebugLoc() != Other->getDebugLoc()) 893 return false; 894 return true; 895} 896 897/// removeFromParent - This method unlinks 'this' from the containing basic 898/// block, and returns it, but does not delete it. 899MachineInstr *MachineInstr::removeFromParent() { 900 assert(getParent() && "Not embedded in a basic block!"); 901 902 // If it's a bundle then remove the MIs inside the bundle as well. 903 if (isBundle()) { 904 MachineBasicBlock *MBB = getParent(); 905 MachineBasicBlock::instr_iterator MII = *this; ++MII; 906 MachineBasicBlock::instr_iterator E = MBB->instr_end(); 907 while (MII != E && MII->isInsideBundle()) { 908 MachineInstr *MI = &*MII; 909 ++MII; 910 MBB->remove(MI); 911 } 912 } 913 getParent()->remove(this); 914 return this; 915} 916 917 918/// eraseFromParent - This method unlinks 'this' from the containing basic 919/// block, and deletes it. 920void MachineInstr::eraseFromParent() { 921 assert(getParent() && "Not embedded in a basic block!"); 922 // If it's a bundle then remove the MIs inside the bundle as well. 923 if (isBundle()) { 924 MachineBasicBlock *MBB = getParent(); 925 MachineBasicBlock::instr_iterator MII = *this; ++MII; 926 MachineBasicBlock::instr_iterator E = MBB->instr_end(); 927 while (MII != E && MII->isInsideBundle()) { 928 MachineInstr *MI = &*MII; 929 ++MII; 930 MBB->erase(MI); 931 } 932 } 933 // Erase the individual instruction, which may itself be inside a bundle. 934 getParent()->erase_instr(this); 935} 936 937 938/// getNumExplicitOperands - Returns the number of non-implicit operands. 939/// 940unsigned MachineInstr::getNumExplicitOperands() const { 941 unsigned NumOperands = MCID->getNumOperands(); 942 if (!MCID->isVariadic()) 943 return NumOperands; 944 945 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 946 const MachineOperand &MO = getOperand(i); 947 if (!MO.isReg() || !MO.isImplicit()) 948 NumOperands++; 949 } 950 return NumOperands; 951} 952 953/// isBundled - Return true if this instruction part of a bundle. This is true 954/// if either itself or its following instruction is marked "InsideBundle". 955bool MachineInstr::isBundled() const { 956 if (isInsideBundle()) 957 return true; 958 MachineBasicBlock::const_instr_iterator nextMI = this; 959 ++nextMI; 960 return nextMI != Parent->instr_end() && nextMI->isInsideBundle(); 961} 962 963bool MachineInstr::isStackAligningInlineAsm() const { 964 if (isInlineAsm()) { 965 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 966 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 967 return true; 968 } 969 return false; 970} 971 972InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const { 973 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!"); 974 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 975 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0); 976} 977 978int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, 979 unsigned *GroupNo) const { 980 assert(isInlineAsm() && "Expected an inline asm instruction"); 981 assert(OpIdx < getNumOperands() && "OpIdx out of range"); 982 983 // Ignore queries about the initial operands. 984 if (OpIdx < InlineAsm::MIOp_FirstOperand) 985 return -1; 986 987 unsigned Group = 0; 988 unsigned NumOps; 989 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 990 i += NumOps) { 991 const MachineOperand &FlagMO = getOperand(i); 992 // If we reach the implicit register operands, stop looking. 993 if (!FlagMO.isImm()) 994 return -1; 995 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 996 if (i + NumOps > OpIdx) { 997 if (GroupNo) 998 *GroupNo = Group; 999 return i; 1000 } 1001 ++Group; 1002 } 1003 return -1; 1004} 1005 1006const TargetRegisterClass* 1007MachineInstr::getRegClassConstraint(unsigned OpIdx, 1008 const TargetInstrInfo *TII, 1009 const TargetRegisterInfo *TRI) const { 1010 assert(getParent() && "Can't have an MBB reference here!"); 1011 assert(getParent()->getParent() && "Can't have an MF reference here!"); 1012 const MachineFunction &MF = *getParent()->getParent(); 1013 1014 // Most opcodes have fixed constraints in their MCInstrDesc. 1015 if (!isInlineAsm()) 1016 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); 1017 1018 if (!getOperand(OpIdx).isReg()) 1019 return NULL; 1020 1021 // For tied uses on inline asm, get the constraint from the def. 1022 unsigned DefIdx; 1023 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 1024 OpIdx = DefIdx; 1025 1026 // Inline asm stores register class constraints in the flag word. 1027 int FlagIdx = findInlineAsmFlagIdx(OpIdx); 1028 if (FlagIdx < 0) 1029 return NULL; 1030 1031 unsigned Flag = getOperand(FlagIdx).getImm(); 1032 unsigned RCID; 1033 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) 1034 return TRI->getRegClass(RCID); 1035 1036 // Assume that all registers in a memory operand are pointers. 1037 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem) 1038 return TRI->getPointerRegClass(MF); 1039 1040 return NULL; 1041} 1042 1043/// getBundleSize - Return the number of instructions inside the MI bundle. 1044unsigned MachineInstr::getBundleSize() const { 1045 assert(isBundle() && "Expecting a bundle"); 1046 1047 MachineBasicBlock::const_instr_iterator I = *this; 1048 unsigned Size = 0; 1049 while ((++I)->isInsideBundle()) { 1050 ++Size; 1051 } 1052 assert(Size > 1 && "Malformed bundle"); 1053 1054 return Size; 1055} 1056 1057/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 1058/// the specific register or -1 if it is not found. It further tightens 1059/// the search criteria to a use that kills the register if isKill is true. 1060int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 1061 const TargetRegisterInfo *TRI) const { 1062 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1063 const MachineOperand &MO = getOperand(i); 1064 if (!MO.isReg() || !MO.isUse()) 1065 continue; 1066 unsigned MOReg = MO.getReg(); 1067 if (!MOReg) 1068 continue; 1069 if (MOReg == Reg || 1070 (TRI && 1071 TargetRegisterInfo::isPhysicalRegister(MOReg) && 1072 TargetRegisterInfo::isPhysicalRegister(Reg) && 1073 TRI->isSubRegister(MOReg, Reg))) 1074 if (!isKill || MO.isKill()) 1075 return i; 1076 } 1077 return -1; 1078} 1079 1080/// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 1081/// indicating if this instruction reads or writes Reg. This also considers 1082/// partial defines. 1083std::pair<bool,bool> 1084MachineInstr::readsWritesVirtualRegister(unsigned Reg, 1085 SmallVectorImpl<unsigned> *Ops) const { 1086 bool PartDef = false; // Partial redefine. 1087 bool FullDef = false; // Full define. 1088 bool Use = false; 1089 1090 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1091 const MachineOperand &MO = getOperand(i); 1092 if (!MO.isReg() || MO.getReg() != Reg) 1093 continue; 1094 if (Ops) 1095 Ops->push_back(i); 1096 if (MO.isUse()) 1097 Use |= !MO.isUndef(); 1098 else if (MO.getSubReg() && !MO.isUndef()) 1099 // A partial <def,undef> doesn't count as reading the register. 1100 PartDef = true; 1101 else 1102 FullDef = true; 1103 } 1104 // A partial redefine uses Reg unless there is also a full define. 1105 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef); 1106} 1107 1108/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 1109/// the specified register or -1 if it is not found. If isDead is true, defs 1110/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 1111/// also checks if there is a def of a super-register. 1112int 1113MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, 1114 const TargetRegisterInfo *TRI) const { 1115 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg); 1116 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1117 const MachineOperand &MO = getOperand(i); 1118 // Accept regmask operands when Overlap is set. 1119 // Ignore them when looking for a specific def operand (Overlap == false). 1120 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) 1121 return i; 1122 if (!MO.isReg() || !MO.isDef()) 1123 continue; 1124 unsigned MOReg = MO.getReg(); 1125 bool Found = (MOReg == Reg); 1126 if (!Found && TRI && isPhys && 1127 TargetRegisterInfo::isPhysicalRegister(MOReg)) { 1128 if (Overlap) 1129 Found = TRI->regsOverlap(MOReg, Reg); 1130 else 1131 Found = TRI->isSubRegister(MOReg, Reg); 1132 } 1133 if (Found && (!isDead || MO.isDead())) 1134 return i; 1135 } 1136 return -1; 1137} 1138 1139/// findFirstPredOperandIdx() - Find the index of the first operand in the 1140/// operand list that is used to represent the predicate. It returns -1 if 1141/// none is found. 1142int MachineInstr::findFirstPredOperandIdx() const { 1143 // Don't call MCID.findFirstPredOperandIdx() because this variant 1144 // is sometimes called on an instruction that's not yet complete, and 1145 // so the number of operands is less than the MCID indicates. In 1146 // particular, the PTX target does this. 1147 const MCInstrDesc &MCID = getDesc(); 1148 if (MCID.isPredicable()) { 1149 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 1150 if (MCID.OpInfo[i].isPredicate()) 1151 return i; 1152 } 1153 1154 return -1; 1155} 1156 1157// MachineOperand::TiedTo is 4 bits wide. 1158const unsigned TiedMax = 15; 1159 1160/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. 1161/// 1162/// Use and def operands can be tied together, indicated by a non-zero TiedTo 1163/// field. TiedTo can have these values: 1164/// 1165/// 0: Operand is not tied to anything. 1166/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1). 1167/// TiedMax: Tied to an operand >= TiedMax-1. 1168/// 1169/// The tied def must be one of the first TiedMax operands on a normal 1170/// instruction. INLINEASM instructions allow more tied defs. 1171/// 1172void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { 1173 MachineOperand &DefMO = getOperand(DefIdx); 1174 MachineOperand &UseMO = getOperand(UseIdx); 1175 assert(DefMO.isDef() && "DefIdx must be a def operand"); 1176 assert(UseMO.isUse() && "UseIdx must be a use operand"); 1177 assert(!DefMO.isTied() && "Def is already tied to another use"); 1178 assert(!UseMO.isTied() && "Use is already tied to another def"); 1179 1180 if (DefIdx < TiedMax) 1181 UseMO.TiedTo = DefIdx + 1; 1182 else { 1183 // Inline asm can use the group descriptors to find tied operands, but on 1184 // normal instruction, the tied def must be within the first TiedMax 1185 // operands. 1186 assert(isInlineAsm() && "DefIdx out of range"); 1187 UseMO.TiedTo = TiedMax; 1188 } 1189 1190 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx(). 1191 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); 1192} 1193 1194/// Given the index of a tied register operand, find the operand it is tied to. 1195/// Defs are tied to uses and vice versa. Returns the index of the tied operand 1196/// which must exist. 1197unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const { 1198 const MachineOperand &MO = getOperand(OpIdx); 1199 assert(MO.isTied() && "Operand isn't tied"); 1200 1201 // Normally TiedTo is in range. 1202 if (MO.TiedTo < TiedMax) 1203 return MO.TiedTo - 1; 1204 1205 // Uses on normal instructions can be out of range. 1206 if (!isInlineAsm()) { 1207 // Normal tied defs must be in the 0..TiedMax-1 range. 1208 if (MO.isUse()) 1209 return TiedMax - 1; 1210 // MO is a def. Search for the tied use. 1211 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) { 1212 const MachineOperand &UseMO = getOperand(i); 1213 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) 1214 return i; 1215 } 1216 llvm_unreachable("Can't find tied use"); 1217 } 1218 1219 // Now deal with inline asm by parsing the operand group descriptor flags. 1220 // Find the beginning of each operand group. 1221 SmallVector<unsigned, 8> GroupIdx; 1222 unsigned OpIdxGroup = ~0u; 1223 unsigned NumOps; 1224 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 1225 i += NumOps) { 1226 const MachineOperand &FlagMO = getOperand(i); 1227 assert(FlagMO.isImm() && "Invalid tied operand on inline asm"); 1228 unsigned CurGroup = GroupIdx.size(); 1229 GroupIdx.push_back(i); 1230 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 1231 // OpIdx belongs to this operand group. 1232 if (OpIdx > i && OpIdx < i + NumOps) 1233 OpIdxGroup = CurGroup; 1234 unsigned TiedGroup; 1235 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup)) 1236 continue; 1237 // Operands in this group are tied to operands in TiedGroup which must be 1238 // earlier. Find the number of operands between the two groups. 1239 unsigned Delta = i - GroupIdx[TiedGroup]; 1240 1241 // OpIdx is a use tied to TiedGroup. 1242 if (OpIdxGroup == CurGroup) 1243 return OpIdx - Delta; 1244 1245 // OpIdx is a def tied to this use group. 1246 if (OpIdxGroup == TiedGroup) 1247 return OpIdx + Delta; 1248 } 1249 llvm_unreachable("Invalid tied operand on inline asm"); 1250} 1251 1252/// clearKillInfo - Clears kill flags on all operands. 1253/// 1254void MachineInstr::clearKillInfo() { 1255 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1256 MachineOperand &MO = getOperand(i); 1257 if (MO.isReg() && MO.isUse()) 1258 MO.setIsKill(false); 1259 } 1260} 1261 1262/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 1263/// 1264void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 1265 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1266 const MachineOperand &MO = MI->getOperand(i); 1267 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 1268 continue; 1269 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 1270 MachineOperand &MOp = getOperand(j); 1271 if (!MOp.isIdenticalTo(MO)) 1272 continue; 1273 if (MO.isKill()) 1274 MOp.setIsKill(); 1275 else 1276 MOp.setIsDead(); 1277 break; 1278 } 1279 } 1280} 1281 1282/// copyPredicates - Copies predicate operand(s) from MI. 1283void MachineInstr::copyPredicates(const MachineInstr *MI) { 1284 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles"); 1285 1286 const MCInstrDesc &MCID = MI->getDesc(); 1287 if (!MCID.isPredicable()) 1288 return; 1289 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1290 if (MCID.OpInfo[i].isPredicate()) { 1291 // Predicated operands must be last operands. 1292 addOperand(MI->getOperand(i)); 1293 } 1294 } 1295} 1296 1297void MachineInstr::substituteRegister(unsigned FromReg, 1298 unsigned ToReg, 1299 unsigned SubIdx, 1300 const TargetRegisterInfo &RegInfo) { 1301 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) { 1302 if (SubIdx) 1303 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1304 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1305 MachineOperand &MO = getOperand(i); 1306 if (!MO.isReg() || MO.getReg() != FromReg) 1307 continue; 1308 MO.substPhysReg(ToReg, RegInfo); 1309 } 1310 } else { 1311 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1312 MachineOperand &MO = getOperand(i); 1313 if (!MO.isReg() || MO.getReg() != FromReg) 1314 continue; 1315 MO.substVirtReg(ToReg, SubIdx, RegInfo); 1316 } 1317 } 1318} 1319 1320/// isSafeToMove - Return true if it is safe to move this instruction. If 1321/// SawStore is set to true, it means that there is a store (or call) between 1322/// the instruction's location and its intended destination. 1323bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 1324 AliasAnalysis *AA, 1325 bool &SawStore) const { 1326 // Ignore stuff that we obviously can't move. 1327 // 1328 // Treat volatile loads as stores. This is not strictly necessary for 1329 // volatiles, but it is required for atomic loads. It is not allowed to move 1330 // a load across an atomic load with Ordering > Monotonic. 1331 if (mayStore() || isCall() || 1332 (mayLoad() && hasOrderedMemoryRef())) { 1333 SawStore = true; 1334 return false; 1335 } 1336 1337 if (isLabel() || isDebugValue() || 1338 isTerminator() || hasUnmodeledSideEffects()) 1339 return false; 1340 1341 // See if this instruction does a load. If so, we have to guarantee that the 1342 // loaded value doesn't change between the load and the its intended 1343 // destination. The check for isInvariantLoad gives the targe the chance to 1344 // classify the load as always returning a constant, e.g. a constant pool 1345 // load. 1346 if (mayLoad() && !isInvariantLoad(AA)) 1347 // Otherwise, this is a real load. If there is a store between the load and 1348 // end of block, we can't move it. 1349 return !SawStore; 1350 1351 return true; 1352} 1353 1354/// isSafeToReMat - Return true if it's safe to rematerialize the specified 1355/// instruction which defined the specified register instead of copying it. 1356bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 1357 AliasAnalysis *AA, 1358 unsigned DstReg) const { 1359 bool SawStore = false; 1360 if (!TII->isTriviallyReMaterializable(this, AA) || 1361 !isSafeToMove(TII, AA, SawStore)) 1362 return false; 1363 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1364 const MachineOperand &MO = getOperand(i); 1365 if (!MO.isReg()) 1366 continue; 1367 // FIXME: For now, do not remat any instruction with register operands. 1368 // Later on, we can loosen the restriction is the register operands have 1369 // not been modified between the def and use. Note, this is different from 1370 // MachineSink because the code is no longer in two-address form (at least 1371 // partially). 1372 if (MO.isUse()) 1373 return false; 1374 else if (!MO.isDead() && MO.getReg() != DstReg) 1375 return false; 1376 } 1377 return true; 1378} 1379 1380/// hasOrderedMemoryRef - Return true if this instruction may have an ordered 1381/// or volatile memory reference, or if the information describing the memory 1382/// reference is not available. Return false if it is known to have no ordered 1383/// memory references. 1384bool MachineInstr::hasOrderedMemoryRef() const { 1385 // An instruction known never to access memory won't have a volatile access. 1386 if (!mayStore() && 1387 !mayLoad() && 1388 !isCall() && 1389 !hasUnmodeledSideEffects()) 1390 return false; 1391 1392 // Otherwise, if the instruction has no memory reference information, 1393 // conservatively assume it wasn't preserved. 1394 if (memoperands_empty()) 1395 return true; 1396 1397 // Check the memory reference information for ordered references. 1398 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1399 if (!(*I)->isUnordered()) 1400 return true; 1401 1402 return false; 1403} 1404 1405/// isInvariantLoad - Return true if this instruction is loading from a 1406/// location whose value is invariant across the function. For example, 1407/// loading a value from the constant pool or from the argument area 1408/// of a function if it does not change. This should only return true of 1409/// *all* loads the instruction does are invariant (if it does multiple loads). 1410bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1411 // If the instruction doesn't load at all, it isn't an invariant load. 1412 if (!mayLoad()) 1413 return false; 1414 1415 // If the instruction has lost its memoperands, conservatively assume that 1416 // it may not be an invariant load. 1417 if (memoperands_empty()) 1418 return false; 1419 1420 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1421 1422 for (mmo_iterator I = memoperands_begin(), 1423 E = memoperands_end(); I != E; ++I) { 1424 if ((*I)->isVolatile()) return false; 1425 if ((*I)->isStore()) return false; 1426 if ((*I)->isInvariant()) return true; 1427 1428 if (const Value *V = (*I)->getValue()) { 1429 // A load from a constant PseudoSourceValue is invariant. 1430 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1431 if (PSV->isConstant(MFI)) 1432 continue; 1433 // If we have an AliasAnalysis, ask it whether the memory is constant. 1434 if (AA && AA->pointsToConstantMemory( 1435 AliasAnalysis::Location(V, (*I)->getSize(), 1436 (*I)->getTBAAInfo()))) 1437 continue; 1438 } 1439 1440 // Otherwise assume conservatively. 1441 return false; 1442 } 1443 1444 // Everything checks out. 1445 return true; 1446} 1447 1448/// isConstantValuePHI - If the specified instruction is a PHI that always 1449/// merges together the same virtual register, return the register, otherwise 1450/// return 0. 1451unsigned MachineInstr::isConstantValuePHI() const { 1452 if (!isPHI()) 1453 return 0; 1454 assert(getNumOperands() >= 3 && 1455 "It's illegal to have a PHI without source operands"); 1456 1457 unsigned Reg = getOperand(1).getReg(); 1458 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1459 if (getOperand(i).getReg() != Reg) 1460 return 0; 1461 return Reg; 1462} 1463 1464bool MachineInstr::hasUnmodeledSideEffects() const { 1465 if (hasProperty(MCID::UnmodeledSideEffects)) 1466 return true; 1467 if (isInlineAsm()) { 1468 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1469 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1470 return true; 1471 } 1472 1473 return false; 1474} 1475 1476/// allDefsAreDead - Return true if all the defs of this instruction are dead. 1477/// 1478bool MachineInstr::allDefsAreDead() const { 1479 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { 1480 const MachineOperand &MO = getOperand(i); 1481 if (!MO.isReg() || MO.isUse()) 1482 continue; 1483 if (!MO.isDead()) 1484 return false; 1485 } 1486 return true; 1487} 1488 1489/// copyImplicitOps - Copy implicit register operands from specified 1490/// instruction to this instruction. 1491void MachineInstr::copyImplicitOps(const MachineInstr *MI) { 1492 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands(); 1493 i != e; ++i) { 1494 const MachineOperand &MO = MI->getOperand(i); 1495 if (MO.isReg() && MO.isImplicit()) 1496 addOperand(MO); 1497 } 1498} 1499 1500void MachineInstr::dump() const { 1501#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 1502 dbgs() << " " << *this; 1503#endif 1504} 1505 1506static void printDebugLoc(DebugLoc DL, const MachineFunction *MF, 1507 raw_ostream &CommentOS) { 1508 const LLVMContext &Ctx = MF->getFunction()->getContext(); 1509 if (!DL.isUnknown()) { // Print source line info. 1510 DIScope Scope(DL.getScope(Ctx)); 1511 // Omit the directory, because it's likely to be long and uninteresting. 1512 if (Scope.Verify()) 1513 CommentOS << Scope.getFilename(); 1514 else 1515 CommentOS << "<unknown>"; 1516 CommentOS << ':' << DL.getLine(); 1517 if (DL.getCol() != 0) 1518 CommentOS << ':' << DL.getCol(); 1519 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx)); 1520 if (!InlinedAtDL.isUnknown()) { 1521 CommentOS << " @[ "; 1522 printDebugLoc(InlinedAtDL, MF, CommentOS); 1523 CommentOS << " ]"; 1524 } 1525 } 1526} 1527 1528void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1529 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction. 1530 const MachineFunction *MF = 0; 1531 const MachineRegisterInfo *MRI = 0; 1532 if (const MachineBasicBlock *MBB = getParent()) { 1533 MF = MBB->getParent(); 1534 if (!TM && MF) 1535 TM = &MF->getTarget(); 1536 if (MF) 1537 MRI = &MF->getRegInfo(); 1538 } 1539 1540 // Save a list of virtual registers. 1541 SmallVector<unsigned, 8> VirtRegs; 1542 1543 // Print explicitly defined operands on the left of an assignment syntax. 1544 unsigned StartOp = 0, e = getNumOperands(); 1545 for (; StartOp < e && getOperand(StartOp).isReg() && 1546 getOperand(StartOp).isDef() && 1547 !getOperand(StartOp).isImplicit(); 1548 ++StartOp) { 1549 if (StartOp != 0) OS << ", "; 1550 getOperand(StartOp).print(OS, TM); 1551 unsigned Reg = getOperand(StartOp).getReg(); 1552 if (TargetRegisterInfo::isVirtualRegister(Reg)) 1553 VirtRegs.push_back(Reg); 1554 } 1555 1556 if (StartOp != 0) 1557 OS << " = "; 1558 1559 // Print the opcode name. 1560 if (TM && TM->getInstrInfo()) 1561 OS << TM->getInstrInfo()->getName(getOpcode()); 1562 else 1563 OS << "UNKNOWN"; 1564 1565 // Print the rest of the operands. 1566 bool OmittedAnyCallClobbers = false; 1567 bool FirstOp = true; 1568 unsigned AsmDescOp = ~0u; 1569 unsigned AsmOpCount = 0; 1570 1571 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { 1572 // Print asm string. 1573 OS << " "; 1574 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM); 1575 1576 // Print HasSideEffects, IsAlignStack 1577 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1578 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1579 OS << " [sideeffect]"; 1580 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 1581 OS << " [alignstack]"; 1582 if (getInlineAsmDialect() == InlineAsm::AD_ATT) 1583 OS << " [attdialect]"; 1584 if (getInlineAsmDialect() == InlineAsm::AD_Intel) 1585 OS << " [inteldialect]"; 1586 1587 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand; 1588 FirstOp = false; 1589 } 1590 1591 1592 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1593 const MachineOperand &MO = getOperand(i); 1594 1595 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1596 VirtRegs.push_back(MO.getReg()); 1597 1598 // Omit call-clobbered registers which aren't used anywhere. This makes 1599 // call instructions much less noisy on targets where calls clobber lots 1600 // of registers. Don't rely on MO.isDead() because we may be called before 1601 // LiveVariables is run, or we may be looking at a non-allocatable reg. 1602 if (MF && isCall() && 1603 MO.isReg() && MO.isImplicit() && MO.isDef()) { 1604 unsigned Reg = MO.getReg(); 1605 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 1606 const MachineRegisterInfo &MRI = MF->getRegInfo(); 1607 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) { 1608 bool HasAliasLive = false; 1609 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true); 1610 AI.isValid(); ++AI) { 1611 unsigned AliasReg = *AI; 1612 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) { 1613 HasAliasLive = true; 1614 break; 1615 } 1616 } 1617 if (!HasAliasLive) { 1618 OmittedAnyCallClobbers = true; 1619 continue; 1620 } 1621 } 1622 } 1623 } 1624 1625 if (FirstOp) FirstOp = false; else OS << ","; 1626 OS << " "; 1627 if (i < getDesc().NumOperands) { 1628 const MCOperandInfo &MCOI = getDesc().OpInfo[i]; 1629 if (MCOI.isPredicate()) 1630 OS << "pred:"; 1631 if (MCOI.isOptionalDef()) 1632 OS << "opt:"; 1633 } 1634 if (isDebugValue() && MO.isMetadata()) { 1635 // Pretty print DBG_VALUE instructions. 1636 const MDNode *MD = MO.getMetadata(); 1637 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2))) 1638 OS << "!\"" << MDS->getString() << '\"'; 1639 else 1640 MO.print(OS, TM); 1641 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { 1642 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm()); 1643 } else if (i == AsmDescOp && MO.isImm()) { 1644 // Pretty print the inline asm operand descriptor. 1645 OS << '$' << AsmOpCount++; 1646 unsigned Flag = MO.getImm(); 1647 switch (InlineAsm::getKind(Flag)) { 1648 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break; 1649 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break; 1650 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break; 1651 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break; 1652 case InlineAsm::Kind_Imm: OS << ":[imm"; break; 1653 case InlineAsm::Kind_Mem: OS << ":[mem"; break; 1654 default: OS << ":[??" << InlineAsm::getKind(Flag); break; 1655 } 1656 1657 unsigned RCID = 0; 1658 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { 1659 if (TM) 1660 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName(); 1661 else 1662 OS << ":RC" << RCID; 1663 } 1664 1665 unsigned TiedTo = 0; 1666 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) 1667 OS << " tiedto:$" << TiedTo; 1668 1669 OS << ']'; 1670 1671 // Compute the index of the next operand descriptor. 1672 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); 1673 } else 1674 MO.print(OS, TM); 1675 } 1676 1677 // Briefly indicate whether any call clobbers were omitted. 1678 if (OmittedAnyCallClobbers) { 1679 if (!FirstOp) OS << ","; 1680 OS << " ..."; 1681 } 1682 1683 bool HaveSemi = false; 1684 if (Flags) { 1685 if (!HaveSemi) OS << ";"; HaveSemi = true; 1686 OS << " flags: "; 1687 1688 if (Flags & FrameSetup) 1689 OS << "FrameSetup"; 1690 } 1691 1692 if (!memoperands_empty()) { 1693 if (!HaveSemi) OS << ";"; HaveSemi = true; 1694 1695 OS << " mem:"; 1696 for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1697 i != e; ++i) { 1698 OS << **i; 1699 if (llvm::next(i) != e) 1700 OS << " "; 1701 } 1702 } 1703 1704 // Print the regclass of any virtual registers encountered. 1705 if (MRI && !VirtRegs.empty()) { 1706 if (!HaveSemi) OS << ";"; HaveSemi = true; 1707 for (unsigned i = 0; i != VirtRegs.size(); ++i) { 1708 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]); 1709 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]); 1710 for (unsigned j = i+1; j != VirtRegs.size();) { 1711 if (MRI->getRegClass(VirtRegs[j]) != RC) { 1712 ++j; 1713 continue; 1714 } 1715 if (VirtRegs[i] != VirtRegs[j]) 1716 OS << "," << PrintReg(VirtRegs[j]); 1717 VirtRegs.erase(VirtRegs.begin()+j); 1718 } 1719 } 1720 } 1721 1722 // Print debug location information. 1723 if (isDebugValue() && getOperand(e - 1).isMetadata()) { 1724 if (!HaveSemi) OS << ";"; HaveSemi = true; 1725 DIVariable DV(getOperand(e - 1).getMetadata()); 1726 OS << " line no:" << DV.getLineNumber(); 1727 if (MDNode *InlinedAt = DV.getInlinedAt()) { 1728 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt); 1729 if (!InlinedAtDL.isUnknown()) { 1730 OS << " inlined @[ "; 1731 printDebugLoc(InlinedAtDL, MF, OS); 1732 OS << " ]"; 1733 } 1734 } 1735 } else if (!debugLoc.isUnknown() && MF) { 1736 if (!HaveSemi) OS << ";"; HaveSemi = true; 1737 OS << " dbg:"; 1738 printDebugLoc(debugLoc, MF, OS); 1739 } 1740 1741 OS << '\n'; 1742} 1743 1744bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1745 const TargetRegisterInfo *RegInfo, 1746 bool AddIfNotFound) { 1747 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1748 bool hasAliases = isPhysReg && 1749 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1750 bool Found = false; 1751 SmallVector<unsigned,4> DeadOps; 1752 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1753 MachineOperand &MO = getOperand(i); 1754 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1755 continue; 1756 unsigned Reg = MO.getReg(); 1757 if (!Reg) 1758 continue; 1759 1760 if (Reg == IncomingReg) { 1761 if (!Found) { 1762 if (MO.isKill()) 1763 // The register is already marked kill. 1764 return true; 1765 if (isPhysReg && isRegTiedToDefOperand(i)) 1766 // Two-address uses of physregs must not be marked kill. 1767 return true; 1768 MO.setIsKill(); 1769 Found = true; 1770 } 1771 } else if (hasAliases && MO.isKill() && 1772 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1773 // A super-register kill already exists. 1774 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1775 return true; 1776 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1777 DeadOps.push_back(i); 1778 } 1779 } 1780 1781 // Trim unneeded kill operands. 1782 while (!DeadOps.empty()) { 1783 unsigned OpIdx = DeadOps.back(); 1784 if (getOperand(OpIdx).isImplicit()) 1785 RemoveOperand(OpIdx); 1786 else 1787 getOperand(OpIdx).setIsKill(false); 1788 DeadOps.pop_back(); 1789 } 1790 1791 // If not found, this means an alias of one of the operands is killed. Add a 1792 // new implicit operand if required. 1793 if (!Found && AddIfNotFound) { 1794 addOperand(MachineOperand::CreateReg(IncomingReg, 1795 false /*IsDef*/, 1796 true /*IsImp*/, 1797 true /*IsKill*/)); 1798 return true; 1799 } 1800 return Found; 1801} 1802 1803void MachineInstr::clearRegisterKills(unsigned Reg, 1804 const TargetRegisterInfo *RegInfo) { 1805 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) 1806 RegInfo = 0; 1807 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1808 MachineOperand &MO = getOperand(i); 1809 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) 1810 continue; 1811 unsigned OpReg = MO.getReg(); 1812 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg))) 1813 MO.setIsKill(false); 1814 } 1815} 1816 1817bool MachineInstr::addRegisterDead(unsigned IncomingReg, 1818 const TargetRegisterInfo *RegInfo, 1819 bool AddIfNotFound) { 1820 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1821 bool hasAliases = isPhysReg && 1822 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1823 bool Found = false; 1824 SmallVector<unsigned,4> DeadOps; 1825 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1826 MachineOperand &MO = getOperand(i); 1827 if (!MO.isReg() || !MO.isDef()) 1828 continue; 1829 unsigned Reg = MO.getReg(); 1830 if (!Reg) 1831 continue; 1832 1833 if (Reg == IncomingReg) { 1834 MO.setIsDead(); 1835 Found = true; 1836 } else if (hasAliases && MO.isDead() && 1837 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1838 // There exists a super-register that's marked dead. 1839 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1840 return true; 1841 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1842 DeadOps.push_back(i); 1843 } 1844 } 1845 1846 // Trim unneeded dead operands. 1847 while (!DeadOps.empty()) { 1848 unsigned OpIdx = DeadOps.back(); 1849 if (getOperand(OpIdx).isImplicit()) 1850 RemoveOperand(OpIdx); 1851 else 1852 getOperand(OpIdx).setIsDead(false); 1853 DeadOps.pop_back(); 1854 } 1855 1856 // If not found, this means an alias of one of the operands is dead. Add a 1857 // new implicit operand if required. 1858 if (Found || !AddIfNotFound) 1859 return Found; 1860 1861 addOperand(MachineOperand::CreateReg(IncomingReg, 1862 true /*IsDef*/, 1863 true /*IsImp*/, 1864 false /*IsKill*/, 1865 true /*IsDead*/)); 1866 return true; 1867} 1868 1869void MachineInstr::addRegisterDefined(unsigned IncomingReg, 1870 const TargetRegisterInfo *RegInfo) { 1871 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { 1872 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); 1873 if (MO) 1874 return; 1875 } else { 1876 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1877 const MachineOperand &MO = getOperand(i); 1878 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() && 1879 MO.getSubReg() == 0) 1880 return; 1881 } 1882 } 1883 addOperand(MachineOperand::CreateReg(IncomingReg, 1884 true /*IsDef*/, 1885 true /*IsImp*/)); 1886} 1887 1888void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, 1889 const TargetRegisterInfo &TRI) { 1890 bool HasRegMask = false; 1891 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1892 MachineOperand &MO = getOperand(i); 1893 if (MO.isRegMask()) { 1894 HasRegMask = true; 1895 continue; 1896 } 1897 if (!MO.isReg() || !MO.isDef()) continue; 1898 unsigned Reg = MO.getReg(); 1899 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 1900 bool Dead = true; 1901 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 1902 I != E; ++I) 1903 if (TRI.regsOverlap(*I, Reg)) { 1904 Dead = false; 1905 break; 1906 } 1907 // If there are no uses, including partial uses, the def is dead. 1908 if (Dead) MO.setIsDead(); 1909 } 1910 1911 // This is a call with a register mask operand. 1912 // Mask clobbers are always dead, so add defs for the non-dead defines. 1913 if (HasRegMask) 1914 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 1915 I != E; ++I) 1916 addRegisterDefined(*I, &TRI); 1917} 1918 1919unsigned 1920MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { 1921 // Build up a buffer of hash code components. 1922 SmallVector<size_t, 8> HashComponents; 1923 HashComponents.reserve(MI->getNumOperands() + 1); 1924 HashComponents.push_back(MI->getOpcode()); 1925 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1926 const MachineOperand &MO = MI->getOperand(i); 1927 if (MO.isReg() && MO.isDef() && 1928 TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1929 continue; // Skip virtual register defs. 1930 1931 HashComponents.push_back(hash_value(MO)); 1932 } 1933 return hash_combine_range(HashComponents.begin(), HashComponents.end()); 1934} 1935 1936void MachineInstr::emitError(StringRef Msg) const { 1937 // Find the source location cookie. 1938 unsigned LocCookie = 0; 1939 const MDNode *LocMD = 0; 1940 for (unsigned i = getNumOperands(); i != 0; --i) { 1941 if (getOperand(i-1).isMetadata() && 1942 (LocMD = getOperand(i-1).getMetadata()) && 1943 LocMD->getNumOperands() != 0) { 1944 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) { 1945 LocCookie = CI->getZExtValue(); 1946 break; 1947 } 1948 } 1949 } 1950 1951 if (const MachineBasicBlock *MBB = getParent()) 1952 if (const MachineFunction *MF = MBB->getParent()) 1953 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg); 1954 report_fatal_error(Msg); 1955} 1956