/macosx-10.5.8/xnu-1228.15.4/osfmk/i386/ |
H A D | cpu_affinity.h | 37 struct x86_cpu_cache *cache; /* The L2 cache concerned */ member in struct:x86_affinity_set
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H A D | cpu_threads.c | 79 x86_cpu_cache_t *cache; local 83 cache = kalloc(sizeof(x86_cpu_cache_t) + (MAX_CPUS * sizeof(x86_lcpu_t *))); 84 if (cache == NULL) 87 cache = x86_caches; 88 x86_caches = cache->next; 89 cache->next = NULL; 92 bzero(cache, sizeof(x86_cpu_cache_t)); 93 cache->next = NULL; 94 cache->maxcpus = MAX_CPUS; 95 for (i = 0; i < cache 262 x86_cache_free(x86_cpu_cache_t *cache) argument 616 x86_cache_add_lcpu(x86_cpu_cache_t *cache, x86_lcpu_t *lcpu) argument [all...] |
H A D | cpu_topology.c | 155 * for their LLC cache. Each affinity set possesses a processor set 175 aset->cache = LLC_cachep; 181 DBG("\tnew set %p(%d) pset %p for cache %p\n", 182 aset, aset->num, aset->pset, aset->cache); 224 if (l2_cachep == aset->cache)
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/macosx-10.5.8/xnu-1228.15.4/iokit/Tests/ |
H A D | TestContainers.cpp | 128 // very first test initialises the OSMetaClass cache. 255 // very first test initialises the OSMetaClass cache. 363 const OSSymbol *cache[numStrCache]; local 366 // very first test initialises the OSMetaClass cache. 367 cache[0] = IOSymbol::withCStringNoCopy(testC00); 368 TEST_ASSERT('u', "0a", cache[0]); 369 if (cache[0]) 370 cache[0]->release(); 374 // Setup the symbol cache, make sure it grows the symbol unique'ing 378 cache[ [all...] |
H A D | TestCollections.cpp | 43 OSObject *cache[numStrCache], *str, *sym; local 54 cache[i] = (OSObject *) OSSymbol::withCStringNoCopy(strCache[i]); 56 cache[i]->release(); 71 cache[0] = IOString::withCStringNoCopy(strCache[0]); 74 TEST_ASSERT('A', "1h", array1->setObject(cache[0])); 75 TEST_ASSERT('A', "1i", cache[0] == array1->getObject(0)); 76 cache[0]->release(); 92 cache[i] = OSString::withCStringNoCopy(strCache[i]); 93 array1 = OSArray::withObjects(cache, numStrCache, numStrCache); 96 cache[ 281 OSObject *cache[numStrCache], *str, *sym; local 485 OSObject *cache[numStrCache]; local 712 OSObject *cache[numStrCache]; local [all...] |
/macosx-10.5.8/xnu-1228.15.4/osfmk/kern/ |
H A D | stack.c | 171 struct stack_cache *cache; local 175 cache = &PROCESSOR_DATA(current_processor(), stack_cache); 176 if (cache->count < STACK_CACHE_SIZE) { 177 stack_next(stack) = cache->free; 178 cache->free = stack; 179 cache->count++; 207 struct stack_cache *cache; local 210 cache = &PROCESSOR_DATA(current_processor(), stack_cache); 211 stack = cache->free; 213 cache [all...] |
/macosx-10.5.8/xnu-1228.15.4/bsd/hfs/ |
H A D | hfs_readwrite.c | 91 SYSCTL_INT (_kern, OID_AUTO, flush_cache_on_write, CTLFLAG_RW, &flush_cache_on_write, 0, "always flush the drive cache on writes to uncached files"); 699 lookup_bucket(struct access_cache *cache, int *indexp, cnid_t parent_id) argument 705 if (cache->numcached == 0) { 710 if (cache->numcached > NUM_CACHE_ENTRIES) { 712 cache->numcached, NUM_CACHE_ENTRIES);*/ 713 cache->numcached = NUM_CACHE_ENTRIES; 716 hi = cache->numcached - 1; 718 index = cache_binSearch(cache->acache, hi, parent_id, &no_match_index); 735 * than an insert if the cache is full. 738 add_node(struct access_cache *cache, in argument 812 do_attr_lookup(struct hfsmount *hfsmp, struct access_cache *cache, dev_t dev, cnid_t cnid, struct cnode *skip_cp, CatalogKey *keyp, struct cat_attr *cnattrp) argument 856 do_access_check(struct hfsmount *hfsmp, int *err, struct access_cache *cache, HFSCatalogNodeID nodeID, struct cnode *skip_cp, struct proc *theProcPtr, kauth_cred_t myp_ucred, dev_t dev, struct vfs_context *my_context, char *bitmap, uint32_t map_size, cnid_t* parents, uint32_t num_parents) argument 1024 struct access_cache cache; local [all...] |
/macosx-10.5.8/xnu-1228.15.4/pexpert/ppc/ |
H A D | pe_clock_speed_asm.s | 59 li r4, 1 ; flag for cache load 93 cmpi cr0, r4, 1 ; see if the was the cache run
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/macosx-10.5.8/xnu-1228.15.4/osfmk/ppc/ |
H A D | hibernate_restore.s | 70 dcbz 0,r6 ; avoid prefetch of next cache line 131 dcbz128 0,r4 ; avoid prefetch of next cache line
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H A D | cswtch.s | 1847 mtcrf 0x02,r11 ; put cache line size bits in cr6 1856 la r11,savefp16(r3) ; Point to the 2nd cache line 1895 dcbz 0,r11 ; Allocate cache 1900 dcbz 0,r11 ; Allocate cache 1906 dcbz 0,r11 ; Allocate cache 1912 dcbz 0,r11 ; Allocate cache 1918 dcbz 0,r11 ; Allocate cache 1924 dcbz 0,r11 ; Allocate cache 1950 // unnecessary cache blocks, we either save all or none of the VRs in a block. We have separate paths 1951 // for each cache bloc [all...] |
H A D | machine_routines_asm.s | 225 dcbf 0,r12 ; Make sure we kill the cache to avoid paradoxes 319 or r2,r8,r0 ; Set bit to make real accesses cache-inhibited 321 mtspr hid4,r2 ; Make real accesses cache-inhibited 340 mtspr hid4,r8 ; Make real accesses not cache-inhibited 368 * Read the byte at physical address paddr. Memory should not be cache inhibited. 399 * Read the half word at physical address paddr. Memory should not be cache inhibited. 432 * Read the word at physical address paddr. Memory should not be cache inhibited. 467 * Read the double word at physical address paddr. Memory should not be cache inhibited. 499 * Write the byte at physical address paddr. Memory should not be cache inhibited. 529 * Write the half word at physical address paddr. Memory should not be cache inhibite [all...] |
H A D | start.s | 205 lwz r13,ptLineSize(r26) ; Get the cache line size 244 icbi 0,r13 ; Flush the i-cache 515 rlwinm r17,r17,0,pfL2b+1,pfL2b-1 ; No level 2 cache 655 mtspr 1016,r13 ; Turn off direct cache 687 ; Take care of level 3 cache 706 rlwinm r17,r17,0,pfL3fab+1,pfL3b-1 ; No 3rd level cache or assist 911 ; .long ptLineSize - Level 1 cache line size 912 ; .long ptl1iSize - Level 1 instruction cache size 913 ; .long ptl1dSize - Level 1 data cache size
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H A D | asm.h | 170 #define ictc 1019 /* I-cache throttling control */ 479 ; L2 cache control 532 ; L3 cache control
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H A D | hw_vm.s | 2572 * used to set cache attribute or protection 2850 ; We changed the attributes of a mapped page. Make sure there are no cache paradoxes. 2851 ; NOTE: Do we have to deal with i-cache here? 2856 dcbf r11,r5 ; Flush the line in the data cache 2925 ; Copy in the cache inhibited bit 2935 andi. r9,r9,pf32Byte+pf128Byte ; Get cache line size 4008 rlwinm r12,r12,9,20,22 ; Isolate and position key for cache entry 4013 ; Note: ESID is in R22:R23 pair; VSID is in R14:R15; cache form VSID is R14:R12 4018 ; Here is the only place that we make an entry in the pmap segment cache. 4020 ; Note that we do not make an entry in the segment cache fo [all...] |
H A D | bcopy.s | 214 bl EXT(bcopy) ; do copy with DR off and SF on, cache enabled 230 ; which cannot handle a cache burst in I/O space, we must turn caching off for the real memory access. 240 or r2,r2,r0 ; Set bit to make real accesses cache-inhibited 242 mtspr hid4,r2 ; Make real accesses cache-inhibited 252 bl EXT(bcopy_nc) ; copy with SF on and EE, DR, VEC, and FP off, cache inhibited 257 andc r2,r2,r0 ; Clear bit to make real accesses cache-inhibited 259 mtspr hid4,r2 ; Make real accesses not cache-inhibited 305 ; - on 32-bit processors (32-byte cache line) 306 ; - on 64-bit processors running in 32-bit mode (128-byte cache line) 307 ; - on 64-bit processors running in 64-bit mode (128-byte cache lin [all...] |
H A D | lowmem_vectors.s | 1190 * instruction to clear and allcoate a line in the cache. This way we won't take any cache 1192 * we can't do a DCBZ if the L1 D-cache is off. The rest we will skip if they are 1251 dcbz 0,r1 ; allocate r4-r7 32-byte line in cache 1280 dcbz 0,r3 ; allocate r8-r11 32-byte line in cache 1291 dcbz 0,r3 ; allocate r12-r15 32-byte line in cache 2602 rlwinm. r0,r21,0,mckL1DCPE,mckL1DCPE ; An L1 data cache parity error? 2727 .align 7 ; Force into cache line 2820 mckL1D: lwz r21,hwMckL1DPE(r2) ; Get data cache parity error count 3134 li r3,32 ; Get cache lin [all...] |
H A D | Emulate.s | 248 dcbz r29,r31 ; Clear and allocate a cache line for us to work in 956 ; Data cache block zero
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H A D | vmachmon_asm.s | 56 .align 5 ; Line up on cache line 895 ; still be in the cache.
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/macosx-10.5.8/xnu-1228.15.4/osfmk/ipc/ |
H A D | ipc_kmsg.c | 195 * We keep a per-processor cache of kernel message buffers. 196 * The cache saves the overhead/locking of using kalloc/kfree. 197 * The per-processor cache seems to miss less than a per-thread cache, 198 * and it also uses less memory. Access to the cache doesn't 206 * the cache, that is best. Otherwise, allocate a new one. 250 struct ikm_cache *cache; local 254 cache = &PROCESSOR_DATA(current_processor(), ikm_cache); 255 if ((i = cache->avail) > 0) { 257 kmsg = cache 331 struct ikm_cache *cache; local [all...] |
/macosx-10.5.8/xnu-1228.15.4/bsd/dev/ppc/ |
H A D | xsumas.s | 65 dcbt 0,r3 ; touch in 1st cache line 105 dcbt r4,r3 ; touch in 2nd cache line 256 dcbt r3,r0 ; touch in next cache line, and keep loads away from the above stores
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/macosx-10.5.8/xnu-1228.15.4/bsd/dev/i386/ |
H A D | sysctl.c | 332 SYSCTL_NODE(_machdep_cpu, OID_AUTO, cache, CTLFLAG_RW|CTLFLAG_LOCKED, 0, 333 "cache"); 345 hw_cpu_sysctl, "I", "L2 cache associativity");
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