Lines Matching refs:cache
2572 * used to set cache attribute or protection
2850 ; We changed the attributes of a mapped page. Make sure there are no cache paradoxes.
2851 ; NOTE: Do we have to deal with i-cache here?
2856 dcbf r11,r5 ; Flush the line in the data cache
2925 ; Copy in the cache inhibited bit
2935 andi. r9,r9,pf32Byte+pf128Byte ; Get cache line size
4008 rlwinm r12,r12,9,20,22 ; Isolate and position key for cache entry
4013 ; Note: ESID is in R22:R23 pair; VSID is in R14:R15; cache form VSID is R14:R12
4018 ; Here is the only place that we make an entry in the pmap segment cache.
4020 ; Note that we do not make an entry in the segment cache for special
4025 ; into a segment in the pmap cache. If it is already there, this is
4027 ; If all is correct, then it was another processors that made the cache
4031 ; If we get a hit, we just bail, otherwise, lock the pmap cache, select
4032 ; an entry based on the generation number, update the cache entry, and
4042 ; The cache entry contains an image of the ESID/VSID pair we would load for
4045 ; Remember, this cache entry goes in the ORIGINAL pmap (saved in R25), not
4052 bne-- cr5,hpfNoCacheEnt2 ; Skip the cache entry if this is a "special nest" fault....
4057 bl pmapCacheLookup ; Go see if this is in the cache already
4080 la r9,pmapSegCache(r25) ; Point to the segment cache
4081 slwi r6,r7,4 ; Get index into the segment cache
4082 slwi r2,r7,2 ; Get index into the segment cache sub-tag index
4086 rlwinm r2,r2,0,27,31 ; Wrap shift so we do not shift cache entries 8-F out
4088 add r9,r9,r6 ; Point to the cache slot
4111 eieio ; Make sure cache is updated before lock
4141 ; Note that the cache entry is the right format except for valid bit.
5436 ; This routine invadates the entire pmap segment cache
5446 la r10,pmapCCtl(r3) ; Point to the segment cache control
5449 isInv: lwarx r4,0,r10 ; Get the segment cache control value
5462 isInv1: lwz r4,pmapCCtl(r3) ; Get the segment cache control
5518 la r10,pmapCCtl(r28) ; Point to the segment cache control
5519 la r9,pmapSegCache(r28) ; Point to the segment cache
5521 ssgLock: lwarx r15,0,r10 ; Get and reserve the segment cache control
5539 b ssg64Enter ; Start on a cache line...
5546 ssgLock1: lwz r15,pmapCCtl(r28) ; Get the segment cache controls
5552 ; We take a reservation on the segment cache and walk through.
5557 ; Afterwards, we unlock the segment cache.
5564 slwi r14,r12,4 ; Index to the cache slot
5592 stw r15,pmapCCtl(r28) ; Unlock the segment cache controls
5623 ; loading the SLB. Afterwards, we release the cache lock
5633 slwi r14,r12,4 ; Index to the cache slot
5650 ssg64Done: stw r15,pmapCCtl(r28) ; Unlock the segment cache controls
8038 ; pmapCacheLookup - This function will look up an entry in the pmap segment cache.
8040 ; How the pmap cache lookup works:
8043 ; ESID (aka the "tag"). The mask indicates which of the cache slots actually contain
8045 ; of the ESID, bits 32:36 of the effective for 64-bit and 0:3 for 32-bit. The cache
8049 ; for an existing cache entry. Because there are 16 slots in the cache, we could end up
8061 ; R3 = pmap cache slot if found, 0 if not
8070 la r10,pmapCCtl(r3) ; Point to the segment cache control
8073 lwarx r11,0,r10 ; Get the segment cache control value
8117 la r10,pmapSegCache(r3) ; Point at the cache slots
8126 rlwinm r7,r5,4,0,27 ; Index to the cache entry
8128 add r7,r7,r10 ; Point to the cache slot
8148 lwz r11,pmapCCtl(r3) ; Get the segment cache control
8700 li r2,4096/32 ; Get number of cache lines
8729 li r2,4096/128 ; Get number of cache lines