Lines Matching refs:cache
225 dcbf 0,r12 ; Make sure we kill the cache to avoid paradoxes
319 or r2,r8,r0 ; Set bit to make real accesses cache-inhibited
321 mtspr hid4,r2 ; Make real accesses cache-inhibited
340 mtspr hid4,r8 ; Make real accesses not cache-inhibited
368 * Read the byte at physical address paddr. Memory should not be cache inhibited.
399 * Read the half word at physical address paddr. Memory should not be cache inhibited.
432 * Read the word at physical address paddr. Memory should not be cache inhibited.
467 * Read the double word at physical address paddr. Memory should not be cache inhibited.
499 * Write the byte at physical address paddr. Memory should not be cache inhibited.
529 * Write the half word at physical address paddr. Memory should not be cache inhibited.
561 * Write the word at physical address paddr. Memory should not be cache inhibited.
595 * Write the double word at physical address paddr. Memory should not be cache inhibited.
646 or r2,r8,r0 ; Set bit to make real accesses cache-inhibited
648 mtspr hid4,r2 ; Make real accesses cache-inhibited
678 mtspr hid4,r8 ; Make real accesses not cache-inhibited
1180 * check if the cache is on, if so, we need to flush the contents to memory.
1294 ; snoop occurs that invalidates one of the lines in the cache, the
1302 ciswdl1: lwz r0,pfl1dSize(r12) ; Get the level 1 cache size
1370 cisnlck: rlwinm r2,r0,0,1,30 ; Double cache size
1371 add r0,r0,r2 ; Get 3 times cache size
1372 rlwinm r0,r0,26,6,31 ; Get 3/2 number of cache lines
1383 rlwinm r8,r8,0,dce+1,ice-1 ; Clear cache enables
1384 mtspr hid0,r8 ; and turn off L1 cache
1392 mtspr hid0,r8 ; Start the invalidate and turn on cache
1404 beq cinol2 ; No level 2 cache to flush
1428 mtspr l2cr,r10 ; Lock out the cache
1484 b cinlc ; Jump back up and turn off cache...
1504 b cinol2 ; No level 2 cache to flush
1516 bf pfL3b,cinol3 ; No level 3 cache to flush
1539 mtspr l3cr,r10 ; Lock out the cache
1603 rlwinm. r0,r0,0,pfL2b,pfL2b ; is there an L2 cache?
1604 beq cinol2a ; No level 2 cache to enable
1619 rlwinm r8,r9,0,dce+1,ice-1 ; Clear the I- and D- cache enables
1628 mtspr hid0,r8 ; Start the invalidate and turn on L1 cache
1694 ori r6,r11,lo16(GUSMdmapen) ; Set the bit that means direct L2 cache address
1814 rlwinm r5,r5,0,dce+1,ice-1 ; Clear the I- and D- cache enables
1836 b cinlcc ; Jump back up and turn off cache...
1844 rlwinm r5,r5,0,l3clken+1,l3clken-1 ; Turn off cache enable bit