Lines Matching refs:cache
1847 mtcrf 0x02,r11 ; put cache line size bits in cr6
1856 la r11,savefp16(r3) ; Point to the 2nd cache line
1895 dcbz 0,r11 ; Allocate cache
1900 dcbz 0,r11 ; Allocate cache
1906 dcbz 0,r11 ; Allocate cache
1912 dcbz 0,r11 ; Allocate cache
1918 dcbz 0,r11 ; Allocate cache
1924 dcbz 0,r11 ; Allocate cache
1950 // unnecessary cache blocks, we either save all or none of the VRs in a block. We have separate paths
1951 // for each cache block size.
1965 mtcrf 0x02,r9 ; put cache line size bits in cr6 where we can test
1971 ; the four cache lines. This minimizes mispredicted branches yet handles cache lines optimally.
2168 // of "vr_store". Like it, we avoid touching unnecessary cache blocks and minimize conditional
2169 // branches by loading all VRs from a cache line, if we have to load any. If we don't load the VRs
2170 // in a cache line, we bug them. Note that this behavior is slightly different from earlier kernels,
2185 mtcrf 0x02,r9 ; set cache line size bits in cr6
2191 // Loop touching in cache blocks we will load from.
2205 vr_ld1: ; loop over each cache line we will load
2212 srw. r9,r7,r4 ; position bits for VRs in that cache line
2218 // Handle a processor with 128-byte cache lines. Four groups of 8 VRs.
2256 vr_ld128b: ; here to handle next cache line
2278 vr_ld128d: ; here to handle next cache line
2300 vr_ld128f: ; here to handle next cache line
2322 // Handle a processor with 32-byte cache lines. Sixteen groups of two VRs.
2338 vr_ld32test2: ; here to handle next cache line
2339 la r11,savevr2(r3) ; get offset to next cache line
2348 vr_ld32test4: ; here to handle next cache line
2349 la r11,savevr4(r3) ; get offset to next cache line
2358 vr_ld32test6: ; here to handle next cache line
2359 la r11,savevr6(r3) ; get offset to next cache line
2368 vr_ld32test8: ; here to handle next cache line
2369 la r11,savevr8(r3) ; get offset to next cache line
2378 vr_ld32test10: ; here to handle next cache line
2379 la r11,savevr10(r3) ; get offset to next cache line
2388 vr_ld32test12: ; here to handle next cache line
2389 la r11,savevr12(r3) ; get offset to next cache line
2398 vr_ld32test14: ; here to handle next cache line
2399 la r11,savevr14(r3) ; get offset to next cache line
2408 vr_ld32test16: ; here to handle next cache line
2409 la r11,savevr16(r3) ; get offset to next cache line
2418 vr_ld32test18: ; here to handle next cache line
2419 la r11,savevr18(r3) ; get offset to next cache line
2428 vr_ld32test20: ; here to handle next cache line
2429 la r11,savevr20(r3) ; get offset to next cache line
2438 vr_ld32test22: ; here to handle next cache line
2439 la r11,savevr22(r3) ; get offset to next cache line
2448 vr_ld32test24: ; here to handle next cache line
2449 la r11,savevr24(r3) ; get offset to next cache line
2458 vr_ld32test26: ; here to handle next cache line
2459 la r11,savevr26(r3) ; get offset to next cache line
2468 vr_ld32test28: ; here to handle next cache line
2469 la r11,savevr28(r3) ; get offset to next cache line
2478 vr_ld32test30: ; here to handle next cache line
2479 la r11,savevr30(r3) ; get offset to next cache line