1/*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
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25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28/*
29 *  clock_speed_asm.s - Uses the Via timer, decrementer, and counter
30 *			to determine the clock and bus rates.
31 *
32 *  (c) Apple Computer, Inc. 1998-9
33 *
34 *  Writen by:	 Josh de Cesare
35 *
36 */
37
38#include <ppc/asm.h>
39
40// constants for the via
41#define CountLow  0x800
42#define CountHigh 0xa00
43#define LatchLow  0xc00
44#define LatchHigh 0xe00
45
46
47// void pe_run_clock_test(clock_test_data *data)
48//
49// data points to the base address of the via and two longs
50// for storing the via and dec results.
51//
52// The basic idea is this...
53// Use the counter register to execute a loop that will take
54// 10,000,000 processor clocks.  Time it using both the via counter
55// and the time base.  Return the number of ticks for both so the
56// raw values for processor and bus speed can be calculated.
57ENTRY(pe_run_clock_test, TAG_NO_FRAME_USED)
58
59	li	r4,	1		; flag for cache load
60	li	r5,	1		; Only once through this time
61	lwz	r9,	0(r3)		; r9 is the via addr
62
63L_again:
64	mtctr	r5			; set the count
65	li	r5,	0xff		; Start the counter at 0xffff
66	stb	r5,	CountLow(r9)	; clear the via counter
67	eieio
68	stb	r5,	CountHigh(r9)
69	eieio
70	mftb	r10			; save starting value of the time base
71	isync
72
73L_loop:
74	addi	r5,	r5,	1	; 8 adds for 8 cycles
75	addi	r5,	r5,	2	; the bdnz should be 0 cycles
76	addi	r5,	r5,	3
77	addi	r5,	r5,	4
78	addi	r5,	r5,	5
79	addi	r5,	r5,	6
80	addi	r5,	r5,	7
81	addi	r5,	r5,	8
82	bdnz	L_loop
83
84	sync
85	mftb	r5			; save the raw time base value
86	lbz	r6,	CountHigh(r9)	; get the via counter values
87	eieio
88	lbz	r7,	CountLow(r9)
89	eieio
90	lbz	r8,	CountHigh(r9)
91	eieio
92
93	cmpi	cr0,	r4,	1	; see if the was the cache run
94	bne	L_finish_up		; nope, we are done.
95
96	li	r4,	0		; set flag for the real test
97	li	r5,	0x12d0		; set the initial count to 1.25e+6
98	oris	r5,	r5,	0x13
99	b	L_again
100
101L_finish_up:
102	cmpi    cr0,    r7,     0	; if L1 is zero then H1 is good.
103	beq     L_use_H1		; else H2 will be good.
104
105	mr      r6,     r8		; use H2 instead.
106
107L_use_H1:
108	rlwimi	r7,	r6,	8, 16, 23
109	not	r6,	r7	        ; neg - 1 is not
110	andi.	r6,	r6,	0xffff
111	stw	r6,	4(r3)		; save via ticks
112
113	sub	r5,	r5,	r10	; r5 is the number of time base ticks
114	stw	r5,	8(r3)		; save time base ticks
115
116        blr
117