Lines Matching refs:cache
214 bl EXT(bcopy) ; do copy with DR off and SF on, cache enabled
230 ; which cannot handle a cache burst in I/O space, we must turn caching off for the real memory access.
240 or r2,r2,r0 ; Set bit to make real accesses cache-inhibited
242 mtspr hid4,r2 ; Make real accesses cache-inhibited
252 bl EXT(bcopy_nc) ; copy with SF on and EE, DR, VEC, and FP off, cache inhibited
257 andc r2,r2,r0 ; Clear bit to make real accesses cache-inhibited
259 mtspr hid4,r2 ; Make real accesses not cache-inhibited
305 ; - on 32-bit processors (32-byte cache line)
306 ; - on 64-bit processors running in 32-bit mode (128-byte cache line)
307 ; - on 64-bit processors running in 64-bit mode (128-byte cache line)
327 ; bcopy_nc() operates on non-cached memory so we can not use any kind of cache instructions.
375 ; also can not use the cache instructions if we are from bcopy_nc.
561 rlwinm r7,r4,0,0x1F ; Calculate the length to align dest on cache boundary
568 beq- balline ; Aready on cache line boundary (or too short to bother)
704 // Here on 64-bit processors, which have a 128-byte cache line. This can be
721 dcbtst 0,r4 // touch in 1st destination cache block
748 cmpwi cr1,r9,0 // any doublewords to move to cache align?
764 beq cr1,c64double4 // no doublewords to xfer in order to cache align
794 c64InnerLoop: // loop copying 128-byte cache lines to 128-aligned destination
804 dcbz128 0,r4 // avoid prefetch of next cache line