Searched refs:mmGRBM_GFX_CNTL (Results 1 - 10 of 10) sorted by relevance
| /linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_1_offset.h | 74 #define mmGRBM_GFX_CNTL 0x0022 macro
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| H A D | gc_9_0_offset.h | 83 #define mmGRBM_GFX_CNTL 0x0022 macro
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| H A D | gc_9_2_1_offset.h | 81 #define mmGRBM_GFX_CNTL 0x0022 macro
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| H A D | gc_9_1_offset.h | 83 #define mmGRBM_GFX_CNTL 0x0022 macro
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| H A D | gc_10_3_0_offset.h | 2166 #define mmGRBM_GFX_CNTL 0x0dc2 macro
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| H A D | gc_10_1_0_offset.h | 2089 #define mmGRBM_GFX_CNTL 0x0dc2 macro
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| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | nv.c | 327 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
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| H A D | soc15.c | 348 WREG32_SOC15_RLC_SHADOW(GC, xcc_id, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
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| H A D | gfx_v10_0.c | 4243 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
6157 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6160 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
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| H A D | gfx_v9_0.c | 1642 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
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