#
4504f143 |
|
30-Mar-2022 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: setup hw debug registers on driver initialization Add missing debug trap registers references and initialize all debug registers on boot by clearing the hardware exception overrides and the wave allocation ID index. The debugger requires that TTMPs 6 & 7 save the dispatch ID to map waves onto dispatch during compute context inspection. In order to correctly set this up, set the special reserved CP bit by default whenever the MQD is initailized. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
67f3c209 |
|
09-Mar-2023 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add missing INT_STAT_DEBUG registers to GC 10.1 and 10.3 headers Checked against database, copied from GC 9.4.2 header. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
1ed1f6be |
|
08-Sep-2022 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: update GC 10.3.0 pwrdec The 10.3 GC headers were missing most of the pwrdec block. This patch adds the registers and bits present in the 10.1 header but based on the contents of the 10.3 specs. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
780244a2 |
|
07-Sep-2022 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add missing CGTS*TCC_DISABLE to 10.3 headers The TCC_DISABLE registers were not included in the 10.3 headers and instead just placed directly in the gfx_v10_0.c source. This patch adds them to the headers so tools like umr can scan them and support them. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
bfaced6e |
|
21-Jun-2022 |
Victor Zhao <Victor.Zhao@amd.com> |
drm/amdgpu: save and restore gc hub regs Save and restore gfxhub regs as they will be reset during mode 2 Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
53df89dd |
|
26-Mar-2021 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headers Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
d0279204 |
|
01-May-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add GC 10.3 NOALLOC registers This adds the NOALLOC registers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
5d5b71e8 |
|
01-May-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add the GC 10.3 VRS registers Add the VRS registers. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
7663edc1 |
|
01-May-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: add the GC 10.3 VRS registers Add the VRS registers. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
26cfd12b |
|
23-Jul-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add RLC_CGTT_MGCG_OVERRIDE to gfx 10.3 headers Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
614c5611 |
|
16-Jun-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2) Despite having different IP offsets the computed address of the register(s) are the same between gfx7..gfx10. This patch fixes the offset relative to the GC block on gfx10. (v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ... Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
e3569fab |
|
14-Jun-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers Forgot to subtract the SOC15 IP offsetand add the BASE_IDX values. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
8d7fb7a1 |
|
11-Jun-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits Even though they are technically MMIO registers I put the bits with the sqind block for organizational purposes. Requested for UMR debugging. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
055e23e3 |
|
09-Jun-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2) Requested for UMR support. (v2): Also add reg/bits for gfx9 headers Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
#
b4ebd871 |
|
19-Mar-2019 |
Likun Gao <Likun.Gao@amd.com> |
drm/amdgpu: add GC 10.3 header files (v2) Add GC10.3 related header files. v2: squash in updates (Alex) Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|