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4504f143 |
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30-Mar-2022 |
Jonathan Kim <jonathan.kim@amd.com> |
drm/amdgpu: setup hw debug registers on driver initialization Add missing debug trap registers references and initialize all debug registers on boot by clearing the hardware exception overrides and the wave allocation ID index. The debugger requires that TTMPs 6 & 7 save the dispatch ID to map waves onto dispatch during compute context inspection. In order to correctly set this up, set the special reserved CP bit by default whenever the MQD is initailized. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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67f3c209 |
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09-Mar-2023 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add missing INT_STAT_DEBUG registers to GC 10.1 and 10.3 headers Checked against database, copied from GC 9.4.2 header. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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614c5611 |
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16-Jun-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2) Despite having different IP offsets the computed address of the register(s) are the same between gfx7..gfx10. This patch fixes the offset relative to the GC block on gfx10. (v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ... Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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e3569fab |
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14-Jun-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Fix SQ_DEBUG_STS_GLOBAL* registers Forgot to subtract the SOC15 IP offsetand add the BASE_IDX values. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8d7fb7a1 |
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11-Jun-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add SQ_DEBUG_STS_GLOBAL* registers/bits Even though they are technically MMIO registers I put the bits with the sqind block for organizational purposes. Requested for UMR debugging. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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055e23e3 |
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09-Jun-2020 |
Tom St Denis <tom.stdenis@amd.com> |
drm/amd/amdgpu: Add SQ debug registers to GFX9/GFX10 headers (v2) Requested for UMR support. (v2): Also add reg/bits for gfx9 headers Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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87190edc |
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10-Jul-2019 |
Xiaojie Yuan <xiaojie.yuan@amd.com> |
drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc header gc 10.1.2 introduced this new register Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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be4008b8 |
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02-Mar-2019 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: add GC 10.1 register headers (v4) v2: Update regs (Alex) v3: More updates (Alex) v4: more updates (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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