Searched refs:clk_zero (Results 1 - 14 of 14) sorted by relevance
| /linux-master/include/linux/phy/ |
| H A D | phy-mipi-dphy.h | 95 * @clk_zero:
100 unsigned int clk_zero; member in struct:phy_configure_opts_mipi_dphy
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| /linux-master/drivers/phy/ |
| H A D | phy-core-mipi-dphy.c | 46 cfg->clk_zero = 262000;
138 if ((cfg->clk_prepare + cfg->clk_zero) < 300000)
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| /linux-master/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy_20nm.c | 15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),
21 if (timing->clk_zero & BIT(8))
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| H A D | dsi_phy.c | 47 timing->clk_zero = clk_z + 8 - temp;
80 /* Calculate clk_zero after clk_prepare and hs_rqst */
118 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui;
137 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
190 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
230 temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui;
251 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
298 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
338 temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
361 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
[all...] |
| H A D | dsi_phy.h | 64 u32 clk_zero; member in struct:msm_dsi_dphy_timing
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| H A D | dsi_phy_28nm.c | 723 writel(DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),
729 if (timing->clk_zero & BIT(8))
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| H A D | dsi_phy_28nm_8960.c | 472 writel(DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),
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| H A D | dsi_phy_14nm.c | 915 u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero;
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| H A D | dsi_phy_10nm.c | 838 writel(timing->clk_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1);
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| H A D | dsi_phy_7nm.c | 1036 writel(timing->clk_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1);
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| /linux-master/drivers/phy/amlogic/ |
| H A D | phy-meson-axg-mipi-dphy.c | 251 (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) |
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| /linux-master/drivers/gpu/drm/bridge/ |
| H A D | samsung-dsim.c | 755 int clk_prepare, lpx, clk_zero, clk_post, clk_trail; local
784 clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock);
822 DSIM_PHYTIMING1_CLK_ZERO(clk_zero) |
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| H A D | nwl-dsi.c | 235 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
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| /linux-master/drivers/media/i2c/ |
| H A D | tc358746.c | 512 val2 = tc358746_ps_to_cnt(cfg->clk_zero, hs_byte_clk) - 1;
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