/freebsd-9.3-release/contrib/llvm/lib/MC/ |
H A D | MCCodeGenInfo.cpp | 18 void MCCodeGenInfo::InitMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, argument 21 CMModel = CM;
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/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcTargetMachine.cpp | 31 Reloc::Model RM, CodeModel::Model CM, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 90 CodeModel::Model CM, 92 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 102 CodeModel::Model CM, 104 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 28 SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument 85 SparcV8TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 97 SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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H A D | SparcTargetMachine.h | 40 Reloc::Model RM, CodeModel::Model CM, 75 Reloc::Model RM, CodeModel::Model CM, 87 Reloc::Model RM, CodeModel::Model CM,
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/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCTargetDesc.cpp | 86 CodeModel::Model CM, 92 switch (CM) { 95 case CodeModel::JITDefault: CM = CodeModel::Small; break; 98 X->InitMCCodeGenInfo(RM, CM, OL); 103 CodeModel::Model CM, 109 switch (CM) { 112 CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 115 CM = CodeModel::Large; 119 X->InitMCCodeGenInfo(RM, CM, OL); 85 createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 102 createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-9.3-release/usr.bin/tip/tip/ |
H A D | acu.c | 75 if (CM != NOSTR) 76 parwrite(FD, CM, size(CM)); 149 if (CM != NOSTR) 150 parwrite(FD, CM, size(CM));
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/freebsd-9.3-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430TargetMachine.cpp | 32 Reloc::Model RM, CodeModel::Model CM, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZSubtarget.cpp | 53 CodeModel::Model CM) const { 60 if (CM == CodeModel::Small)
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H A D | SystemZTargetMachine.cpp | 26 CodeModel::Model CM, 28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 22 SystemZTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCTargetDesc.cpp | 73 CodeModel::Model CM, 83 if (CM == CodeModel::Default) 84 CM = CodeModel::Small; 85 else if (CM == CodeModel::JITDefault) { 89 CM = CodeModel::Large; 92 X->InitMCCodeGenInfo(RM, CM, OL); 72 createAArch64MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXTargetMachine.cpp | 68 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 70 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 82 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 84 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 90 const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 92 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 66 NVPTXTargetMachine( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument 80 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 88 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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H A D | NVPTXTargetMachine.h | 52 CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit); 103 Reloc::Model RM, CodeModel::Model CM, 112 Reloc::Model RM, CodeModel::Model CM,
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/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCTargetMachine.cpp | 76 Reloc::Model RM, CodeModel::Model CM, 79 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 97 Reloc::Model RM, CodeModel::Model CM, 99 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 107 Reloc::Model RM, CodeModel::Model CM, 109 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 73 PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument 94 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 104 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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H A D | PPCTargetMachine.h | 43 Reloc::Model RM, CodeModel::Model CM, 83 Reloc::Model RM, CodeModel::Model CM, 94 Reloc::Model RM, CodeModel::Model CM,
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/freebsd-9.3-release/contrib/llvm/lib/Target/X86/ |
H A D | X86TargetMachine.cpp | 36 Reloc::Model RM, CodeModel::Model CM, 38 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false), 60 Reloc::Model RM, CodeModel::Model CM, 62 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true), 81 Reloc::Model RM, CodeModel::Model CM, 84 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 33 X86_32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 57 X86_64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 78 X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64Bit) argument
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H A D | X86TargetMachine.h | 40 Reloc::Model RM, CodeModel::Model CM, 89 Reloc::Model RM, CodeModel::Model CM, 118 Reloc::Model RM, CodeModel::Model CM,
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/freebsd-9.3-release/contrib/llvm/include/llvm/MC/ |
H A D | MCCodeGenInfo.h | 37 CodeModel::Model CM = CodeModel::Default,
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/freebsd-9.3-release/contrib/llvm/lib/Target/CppBackend/ |
H A D | CPPTargetMachine.h | 27 Reloc::Model RM, CodeModel::Model CM, 25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetMachine.cpp | 32 Reloc::Model RM, CodeModel::Model CM, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 29 AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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H A D | AArch64TargetMachine.h | 38 Reloc::Model RM, CodeModel::Model CM,
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/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCTargetDesc.cpp | 70 CodeModel::Model CM, 75 X->InitMCCodeGenInfo(Reloc::Static, CM, OL); 69 createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/MSP430/MCTargetDesc/ |
H A D | MSP430MCTargetDesc.cpp | 54 CodeModel::Model CM, 57 X->InitMCCodeGenInfo(RM, CM, OL); 53 createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreTargetMachine.cpp | 26 Reloc::Model RM, CodeModel::Model CM, 28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMTargetMachine.h | 44 Reloc::Model RM, CodeModel::Model CM, 79 Reloc::Model RM, CodeModel::Model CM, 117 Reloc::Model RM, CodeModel::Model CM,
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/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsTargetMachine.h | 53 Reloc::Model RM, CodeModel::Model CM, 108 Reloc::Model RM, CodeModel::Model CM, 119 Reloc::Model RM, CodeModel::Model CM,
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/freebsd-9.3-release/contrib/llvm/tools/clang/lib/StaticAnalyzer/Checkers/ |
H A D | BoolAssignmentChecker.cpp | 81 ConstraintManager &CM = C.getConstraintManager(); local 99 llvm::tie(stateGE, stateLT) = CM.assumeDual(state, *greaterThanEqualToZero); 135 llvm::tie(stateLE, stateGT) = CM.assumeDual(state, *lessThanEqToOne);
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