1193323Sed//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// 11193323Sed//===----------------------------------------------------------------------===// 12193323Sed 13235633Sdim#include "SparcTargetMachine.h" 14218893Sdim#include "Sparc.h" 15252723Sdim#include "llvm/CodeGen/Passes.h" 16193323Sed#include "llvm/PassManager.h" 17226890Sdim#include "llvm/Support/TargetRegistry.h" 18193323Sedusing namespace llvm; 19193323Sed 20198090Srdivackyextern "C" void LLVMInitializeSparcTarget() { 21198090Srdivacky // Register the target. 22203954Srdivacky RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget); 23203954Srdivacky RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); 24193323Sed} 25193323Sed 26193323Sed/// SparcTargetMachine ctor - Create an ILP32 architecture model 27193323Sed/// 28235633SdimSparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, 29226890Sdim StringRef CPU, StringRef FS, 30235633Sdim const TargetOptions &Options, 31226890Sdim Reloc::Model RM, CodeModel::Model CM, 32235633Sdim CodeGenOpt::Level OL, 33226890Sdim bool is64bit) 34235633Sdim : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 35224145Sdim Subtarget(TT, CPU, FS, is64bit), 36245431Sdim DL(Subtarget.getDataLayout()), 37245431Sdim InstrInfo(Subtarget), 38245431Sdim TLInfo(*this), TSInfo(*this), 39252723Sdim FrameLowering(Subtarget) { 40263509Sdim initAsmInfo(); 41193323Sed} 42193323Sed 43235633Sdimnamespace { 44235633Sdim/// Sparc Code Generator Pass Configuration Options. 45235633Sdimclass SparcPassConfig : public TargetPassConfig { 46235633Sdimpublic: 47235633Sdim SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM) 48235633Sdim : TargetPassConfig(TM, PM) {} 49235633Sdim 50235633Sdim SparcTargetMachine &getSparcTargetMachine() const { 51235633Sdim return getTM<SparcTargetMachine>(); 52235633Sdim } 53235633Sdim 54235633Sdim virtual bool addInstSelector(); 55235633Sdim virtual bool addPreEmitPass(); 56235633Sdim}; 57235633Sdim} // namespace 58235633Sdim 59235633SdimTargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { 60235633Sdim return new SparcPassConfig(this, PM); 61235633Sdim} 62235633Sdim 63235633Sdimbool SparcPassConfig::addInstSelector() { 64245431Sdim addPass(createSparcISelDag(getSparcTargetMachine())); 65193323Sed return false; 66193323Sed} 67193323Sed 68263509Sdimbool SparcTargetMachine::addCodeEmitter(PassManagerBase &PM, 69263509Sdim JITCodeEmitter &JCE) { 70263509Sdim // Machine code emitter pass for Sparc. 71263509Sdim PM.add(createSparcJITCodeEmitterPass(*this, JCE)); 72263509Sdim return false; 73263509Sdim} 74263509Sdim 75193323Sed/// addPreEmitPass - This pass may be implemented by targets that want to run 76193323Sed/// passes immediately before machine code is emitted. This should return 77193323Sed/// true if -print-machineinstrs should print out the code after the passes. 78235633Sdimbool SparcPassConfig::addPreEmitPass(){ 79245431Sdim addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine())); 80193323Sed return true; 81193323Sed} 82203954Srdivacky 83235633Sdimvoid SparcV8TargetMachine::anchor() { } 84235633Sdim 85203954SrdivackySparcV8TargetMachine::SparcV8TargetMachine(const Target &T, 86226890Sdim StringRef TT, StringRef CPU, 87235633Sdim StringRef FS, 88235633Sdim const TargetOptions &Options, 89235633Sdim Reloc::Model RM, 90235633Sdim CodeModel::Model CM, 91235633Sdim CodeGenOpt::Level OL) 92235633Sdim : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { 93203954Srdivacky} 94203954Srdivacky 95235633Sdimvoid SparcV9TargetMachine::anchor() { } 96235633Sdim 97235633SdimSparcV9TargetMachine::SparcV9TargetMachine(const Target &T, 98226890Sdim StringRef TT, StringRef CPU, 99235633Sdim StringRef FS, 100235633Sdim const TargetOptions &Options, 101235633Sdim Reloc::Model RM, 102235633Sdim CodeModel::Model CM, 103235633Sdim CodeGenOpt::Level OL) 104235633Sdim : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { 105203954Srdivacky} 106