1144648Sdas//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===// 2144648Sdas// 3144648Sdas// The LLVM Compiler Infrastructure 4144648Sdas// 5144648Sdas// This file is distributed under the University of Illinois Open Source 6144648Sdas// License. See LICENSE.TXT for details. 7144648Sdas// 8144648Sdas//===----------------------------------------------------------------------===// 9144648Sdas// 10144648Sdas// Top-level implementation for the NVPTX target. 11144648Sdas// 12144648Sdas//===----------------------------------------------------------------------===// 13144648Sdas 14144648Sdas#include "NVPTXTargetMachine.h" 15144648Sdas#include "MCTargetDesc/NVPTXMCAsmInfo.h" 16144648Sdas#include "NVPTX.h" 17144648Sdas#include "NVPTXAllocaHoisting.h" 18144648Sdas#include "NVPTXLowerAggrCopies.h" 19144648Sdas#include "NVPTXSplitBBatBar.h" 20144648Sdas#include "llvm/ADT/OwningPtr.h" 21144648Sdas#include "llvm/Analysis/Passes.h" 22144648Sdas#include "llvm/Analysis/Verifier.h" 23144648Sdas#include "llvm/Assembly/PrintModulePass.h" 24144648Sdas#include "llvm/CodeGen/AsmPrinter.h" 25144648Sdas#include "llvm/CodeGen/MachineFunctionAnalysis.h" 26144648Sdas#include "llvm/CodeGen/MachineModuleInfo.h" 27144648Sdas#include "llvm/CodeGen/Passes.h" 28144648Sdas#include "llvm/IR/DataLayout.h" 29144648Sdas#include "llvm/MC/MCAsmInfo.h" 30144648Sdas#include "llvm/MC/MCInstrInfo.h" 31144648Sdas#include "llvm/MC/MCStreamer.h" 32144648Sdas#include "llvm/MC/MCSubtargetInfo.h" 33144648Sdas#include "llvm/PassManager.h" 34144648Sdas#include "llvm/Support/CommandLine.h" 35144648Sdas#include "llvm/Support/Debug.h" 36144648Sdas#include "llvm/Support/FormattedStream.h" 37144648Sdas#include "llvm/Support/TargetRegistry.h" 38144648Sdas#include "llvm/Support/raw_ostream.h" 39144648Sdas#include "llvm/Target/TargetInstrInfo.h" 40144648Sdas#include "llvm/Target/TargetLowering.h" 41144648Sdas#include "llvm/Target/TargetLoweringObjectFile.h" 42144648Sdas#include "llvm/Target/TargetMachine.h" 43144648Sdas#include "llvm/Target/TargetOptions.h" 44144648Sdas#include "llvm/Target/TargetRegisterInfo.h" 45144648Sdas#include "llvm/Target/TargetSubtargetInfo.h" 46144648Sdas#include "llvm/Transforms/Scalar.h" 47144648Sdas 48144648Sdasusing namespace llvm; 49144648Sdas 50144648Sdasnamespace llvm { 51144648Sdasvoid initializeNVVMReflectPass(PassRegistry&); 52144648Sdasvoid initializeGenericToNVVMPass(PassRegistry&); 53144648Sdas} 54144648Sdas 55144648Sdasextern "C" void LLVMInitializeNVPTXTarget() { 56144648Sdas // Register the target. 57144648Sdas RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32); 58144648Sdas RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64); 59144648Sdas 60144648Sdas // FIXME: This pass is really intended to be invoked during IR optimization, 61144648Sdas // but it's very NVPTX-specific. 62144648Sdas initializeNVVMReflectPass(*PassRegistry::getPassRegistry()); 63144648Sdas initializeGenericToNVVMPass(*PassRegistry::getPassRegistry()); 64144648Sdas} 65144648Sdas 66144648SdasNVPTXTargetMachine::NVPTXTargetMachine( 67144648Sdas const Target &T, StringRef TT, StringRef CPU, StringRef FS, 68144648Sdas const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 69144648Sdas CodeGenOpt::Level OL, bool is64bit) 70144648Sdas : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 71144648Sdas Subtarget(TT, CPU, FS, is64bit), DL(Subtarget.getDataLayout()), 72144648Sdas InstrInfo(*this), TLInfo(*this), TSInfo(*this), 73144648Sdas FrameLowering( 74144648Sdas *this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ { 75144648Sdas initAsmInfo(); 76144648Sdas} 77144648Sdas 78144648Sdasvoid NVPTXTargetMachine32::anchor() {} 79144648Sdas 80144648SdasNVPTXTargetMachine32::NVPTXTargetMachine32( 81144648Sdas const Target &T, StringRef TT, StringRef CPU, StringRef FS, 82144648Sdas const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 83144648Sdas CodeGenOpt::Level OL) 84144648Sdas : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 85144648Sdas 86144648Sdasvoid NVPTXTargetMachine64::anchor() {} 87144648Sdas 88144648SdasNVPTXTargetMachine64::NVPTXTargetMachine64( 89144648Sdas const Target &T, StringRef TT, StringRef CPU, StringRef FS, 90144648Sdas const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, 91144648Sdas CodeGenOpt::Level OL) 92144648Sdas : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 93144648Sdas 94144648Sdasnamespace { 95144648Sdasclass NVPTXPassConfig : public TargetPassConfig { 96144648Sdaspublic: 97144648Sdas NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM) 98144648Sdas : TargetPassConfig(TM, PM) {} 99144648Sdas 100144648Sdas NVPTXTargetMachine &getNVPTXTargetMachine() const { 101144648Sdas return getTM<NVPTXTargetMachine>(); 102144648Sdas } 103144648Sdas 104144648Sdas virtual void addIRPasses(); 105144648Sdas virtual bool addInstSelector(); 106144648Sdas virtual bool addPreRegAlloc(); 107144648Sdas virtual bool addPostRegAlloc(); 108144648Sdas 109144648Sdas virtual FunctionPass *createTargetRegisterAllocator(bool) LLVM_OVERRIDE; 110144648Sdas virtual void addFastRegAlloc(FunctionPass *RegAllocPass); 111144648Sdas virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass); 112144648Sdas}; 113144648Sdas} // end anonymous namespace 114144648Sdas 115144648SdasTargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) { 116144648Sdas NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM); 117144648Sdas return PassConfig; 118144648Sdas} 119144648Sdas 120144648Sdasvoid NVPTXPassConfig::addIRPasses() { 121144648Sdas // The following passes are known to not play well with virtual regs hanging 122144648Sdas // around after register allocation (which in our case, is *all* registers). 123144648Sdas // We explicitly disable them here. We do, however, need some functionality 124144648Sdas // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the 125144648Sdas // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp). 126144648Sdas disablePass(&PrologEpilogCodeInserterID); 127144648Sdas disablePass(&MachineCopyPropagationID); 128144648Sdas disablePass(&BranchFolderPassID); 129144648Sdas disablePass(&TailDuplicateID); 130144648Sdas 131144648Sdas TargetPassConfig::addIRPasses(); 132144648Sdas addPass(createGenericToNVVMPass()); 133144648Sdas} 134144648Sdas 135144648Sdasbool NVPTXPassConfig::addInstSelector() { 136144648Sdas addPass(createLowerAggrCopies()); 137144648Sdas addPass(createSplitBBatBarPass()); 138144648Sdas addPass(createAllocaHoisting()); 139144648Sdas addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel())); 140144648Sdas return false; 141144648Sdas} 142144648Sdas 143144648Sdasbool NVPTXPassConfig::addPreRegAlloc() { return false; } 144144648Sdasbool NVPTXPassConfig::addPostRegAlloc() { 145144648Sdas addPass(createNVPTXPrologEpilogPass()); 146144648Sdas return false; 147144648Sdas} 148144648Sdas 149144648SdasFunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) { 150144648Sdas return 0; // No reg alloc 151144648Sdas} 152144648Sdas 153144648Sdasvoid NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) { 154144648Sdas assert(!RegAllocPass && "NVPTX uses no regalloc!"); 155144648Sdas addPass(&PHIEliminationID); 156144648Sdas addPass(&TwoAddressInstructionPassID); 157144648Sdas} 158144648Sdas 159144648Sdasvoid NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) { 160144648Sdas assert(!RegAllocPass && "NVPTX uses no regalloc!"); 161144648Sdas 162144648Sdas addPass(&ProcessImplicitDefsID); 163144648Sdas addPass(&LiveVariablesID); 164144648Sdas addPass(&MachineLoopInfoID); 165144648Sdas addPass(&PHIEliminationID); 166144648Sdas 167144648Sdas addPass(&TwoAddressInstructionPassID); 168144648Sdas addPass(&RegisterCoalescerID); 169144648Sdas 170144648Sdas // PreRA instruction scheduling. 171144648Sdas if (addPass(&MachineSchedulerID)) 172144648Sdas printAndVerify("After Machine Scheduling"); 173144648Sdas 174144648Sdas 175144648Sdas addPass(&StackSlotColoringID); 176144648Sdas 177144648Sdas // FIXME: Needs physical registers 178144648Sdas //addPass(&PostRAMachineLICMID); 179144648Sdas 180144648Sdas printAndVerify("After StackSlotColoring"); 181144648Sdas} 182144648Sdas