1//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Top-level implementation for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCTargetMachine.h"
15#include "PPC.h"
16#include "llvm/CodeGen/Passes.h"
17#include "llvm/MC/MCStreamer.h"
18#include "llvm/PassManager.h"
19#include "llvm/Support/CommandLine.h"
20#include "llvm/Support/FormattedStream.h"
21#include "llvm/Support/TargetRegistry.h"
22#include "llvm/Target/TargetOptions.h"
23using namespace llvm;
24
25static cl::
26opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
27                        cl::desc("Disable CTR loops for PPC"));
28
29extern "C" void LLVMInitializePowerPCTarget() {
30  // Register the targets
31  RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
32  RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
33  RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
34}
35
36/// Return the datalayout string of a subtarget.
37static std::string getDataLayoutString(const PPCSubtarget &ST) {
38  const Triple &T = ST.getTargetTriple();
39
40  // PPC is big endian
41  std::string Ret = "E";
42
43  // PPC64 has 64 bit pointers, PPC32 has 32 bit pointers.
44  if (ST.isPPC64())
45    Ret += "-p:64:64";
46  else
47    Ret += "-p:32:32";
48
49  // Note, the alignment values for f64 and i64 on ppc64 in Darwin
50  // documentation are wrong; these are correct (i.e. "what gcc does").
51  if (ST.isPPC64() || ST.isSVR4ABI())
52    Ret += "-f64:64:64-i64:64:64";
53  else
54    Ret += "-f64:32:64";
55
56  // Set support for 128 floats depending on the ABI.
57  if (!ST.isPPC64() && ST.isSVR4ABI())
58    Ret += "-f128:64:128";
59
60  // Some ABIs support 128 bit vectors.
61  if (ST.isPPC64() && ST.isSVR4ABI())
62    Ret += "-v128:128:128";
63
64  // PPC64 has 32 and 64 bit register, PPC32 has only 32 bit ones.
65  if (ST.isPPC64())
66    Ret += "-n32:64";
67  else
68    Ret += "-n32";
69
70  return Ret;
71}
72
73PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
74                                   StringRef CPU, StringRef FS,
75                                   const TargetOptions &Options,
76                                   Reloc::Model RM, CodeModel::Model CM,
77                                   CodeGenOpt::Level OL,
78                                   bool is64Bit)
79  : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
80    Subtarget(TT, CPU, FS, is64Bit),
81    DL(getDataLayoutString(Subtarget)), InstrInfo(*this),
82    FrameLowering(Subtarget), JITInfo(*this, is64Bit),
83    TLInfo(*this), TSInfo(*this),
84    InstrItins(Subtarget.getInstrItineraryData()) {
85
86  // The binutils for the BG/P are too old for CFI.
87  if (Subtarget.isBGP())
88    setMCUseCFI(false);
89  initAsmInfo();
90}
91
92void PPC32TargetMachine::anchor() { }
93
94PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
95                                       StringRef CPU, StringRef FS,
96                                       const TargetOptions &Options,
97                                       Reloc::Model RM, CodeModel::Model CM,
98                                       CodeGenOpt::Level OL)
99  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
100}
101
102void PPC64TargetMachine::anchor() { }
103
104PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
105                                       StringRef CPU,  StringRef FS,
106                                       const TargetOptions &Options,
107                                       Reloc::Model RM, CodeModel::Model CM,
108                                       CodeGenOpt::Level OL)
109  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
110}
111
112
113//===----------------------------------------------------------------------===//
114// Pass Pipeline Configuration
115//===----------------------------------------------------------------------===//
116
117namespace {
118/// PPC Code Generator Pass Configuration Options.
119class PPCPassConfig : public TargetPassConfig {
120public:
121  PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
122    : TargetPassConfig(TM, PM) {}
123
124  PPCTargetMachine &getPPCTargetMachine() const {
125    return getTM<PPCTargetMachine>();
126  }
127
128  const PPCSubtarget &getPPCSubtarget() const {
129    return *getPPCTargetMachine().getSubtargetImpl();
130  }
131
132  virtual bool addPreISel();
133  virtual bool addILPOpts();
134  virtual bool addInstSelector();
135  virtual bool addPreSched2();
136  virtual bool addPreEmitPass();
137};
138} // namespace
139
140TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
141  return new PPCPassConfig(this, PM);
142}
143
144bool PPCPassConfig::addPreISel() {
145  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
146    addPass(createPPCCTRLoops(getPPCTargetMachine()));
147
148  return false;
149}
150
151bool PPCPassConfig::addILPOpts() {
152  if (getPPCSubtarget().hasISEL()) {
153    addPass(&EarlyIfConverterID);
154    return true;
155  }
156
157  return false;
158}
159
160bool PPCPassConfig::addInstSelector() {
161  // Install an instruction selector.
162  addPass(createPPCISelDag(getPPCTargetMachine()));
163
164#ifndef NDEBUG
165  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
166    addPass(createPPCCTRLoopsVerify());
167#endif
168
169  return false;
170}
171
172bool PPCPassConfig::addPreSched2() {
173  if (getOptLevel() != CodeGenOpt::None)
174    addPass(&IfConverterID);
175
176  return true;
177}
178
179bool PPCPassConfig::addPreEmitPass() {
180  if (getOptLevel() != CodeGenOpt::None)
181    addPass(createPPCEarlyReturnPass());
182  // Must run branch selection immediately preceding the asm printer.
183  addPass(createPPCBranchSelectionPass());
184  return false;
185}
186
187bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
188                                      JITCodeEmitter &JCE) {
189  // Inform the subtarget that we are in JIT mode.  FIXME: does this break macho
190  // writing?
191  Subtarget.SetJITMode();
192
193  // Machine code emitter pass for PowerPC.
194  PM.add(createPPCJITCodeEmitterPass(*this, JCE));
195
196  return false;
197}
198
199void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
200  // Add first the target-independent BasicTTI pass, then our PPC pass. This
201  // allows the PPC pass to delegate to the target independent layer when
202  // appropriate.
203  PM.add(createBasicTargetTransformInfoPass(this));
204  PM.add(createPPCTargetTransformInfoPass(this));
205}
206
207