Searched refs:isUse (Results 1 - 25 of 108) sorted by relevance
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ProcessImplicitDefs.cpp | 70 if (MO.isReg() && MO.isUse() && MO.readsReg()) 110 if (MO.isUse())
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H A D | RegAllocFast.cpp | 372 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { 797 if (LRI->LastUse != &MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse()) 824 if (MO.isUse()) 896 if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) || 926 if (MO.isUse()) { 1051 if (MO.isUse()) { 1063 if (MO.isUse()) { 1101 if (MO.isUse()) { 1125 if (!MO.isReg() || !MO.isUse())
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H A D | DeadMachineInstructionElim.cpp | 171 if (MO.isReg() && MO.isUse()) {
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H A D | LiveIntervals.cpp | 790 if (MO.isUse()) { 862 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, argument 865 return getSpillWeight(isDef, isUse, MBFI, MI.getParent()); 868 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, argument 873 return (isDef + isUse) * (Freq.getFrequency() * Scale); 990 if (MO.isUse()) { 1088 if (MOP.isReg() && MOP.isUse()) 1389 if (MO->isReg() && !MO->isUse()) 1615 } else if (MO.isUse()) {
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H A D | TwoAddressInstructionPass.cpp | 257 if (MO.isUse() && DI->second < LastUse) 367 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) 947 if (MO.isUse()) { 986 if (MO.isUse()) { 1249 if (MO.isUse()) { 1328 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); 1440 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && 1465 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { 1505 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
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H A D | MachineSink.cpp | 466 if (!MO.isReg() || !MO.isUse()) 670 if (MO.isUse()) { 682 if (MO.isUse()) continue; 1030 if (MO.isReg() && MO.isUse()) 1256 // FIXME: instead of isUse(), readsReg() would be a better fix here, 1260 } else if (MO.isUse()) {
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H A D | MachineInstr.cpp | 281 if (NewMO->isUse()) { 883 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 970 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg) 983 if (!MO.isReg() || !MO.isUse()) 1011 if (MO.isUse()) 1090 assert(UseMO.isUse() && "UseIdx must be a use operand"); 1122 if (MO.isUse()) 1127 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) 1170 if (MO.isReg() && MO.isUse()) 1428 if (!MO.isReg() || MO.isUse()) [all...] |
H A D | CriticalAntiDepBreaker.cpp | 239 if (MO.isUse() && Special) { 315 if (!MO.isUse()) continue; 625 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
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H A D | LiveIntervalCalc.cpp | 159 if (MO.isUse())
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H A D | LiveRangeShrink.cpp | 144 if (MO.isUse())
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H A D | BreakFalseDeps.cpp | 214 if (MO.isUse())
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMIChecking.cpp | 115 if (!MO.isReg() || MO.isUse())
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | LiveRegUnits.h | 66 assert(O->isUse() && "Reg operand not a def and not a use");
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H A D | LiveIntervals.h | 105 static float getSpillWeight(bool isDef, bool isUse, 110 static float getSpillWeight(bool isDef, bool isUse,
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H A D | MachineRegisterInfo.h | 980 if ((!ReturnUses && op->isUse()) || 994 if (Op->isUse()) 1086 if ((!ReturnUses && op->isUse()) || 1100 if (Op->isUse())
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | DelaySlotFiller.cpp | 263 if (MO.isUse()) { 304 assert(Reg.isUse() && "CALL first operand is not a use."); 311 assert(Operand1.isUse() && "CALLrr second operand is not a use."); 332 if (MO.isUse()) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiDelaySlotFiller.cpp | 215 if (MO.isUse()) { 241 else if (MO.isUse())
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegColoring.cpp | 70 Weight += LiveIntervals::getSpillWeight(MO.isDef(), MO.isUse(), MBFI,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FixupBWInsts.cpp | 264 assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!"); 273 if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) &&
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 259 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); 355 if (MO.isReg() && MO.isUse()) 376 if (!MO.isReg() || !MO.isUse())
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H A D | HexagonNewValueJump.cpp | 178 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { 653 if (!MO.isReg() || !MO.isUse()) 660 if (!Op.isReg() || !Op.isUse() || !Op.isKill())
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H A D | HexagonSubtarget.cpp | 241 if (MO.isUse() && !MI->isCopy() && 352 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) { 444 if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | Utils.cpp | 56 if (RegMO.isUse()) { 101 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) && 158 if (MO.isUse()) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | Thumb2ITBlockPass.cpp | 93 if (MO.isUse())
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsOptimizePICCall.cpp | 130 if (!MO.isReg() || !MO.isUse() || !Register::isVirtualRegister(MO.getReg()))
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