1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// Methods common to all machine instructions. 10// 11//===----------------------------------------------------------------------===// 12 13#include "llvm/CodeGen/MachineInstr.h" 14#include "llvm/ADT/APFloat.h" 15#include "llvm/ADT/ArrayRef.h" 16#include "llvm/ADT/FoldingSet.h" 17#include "llvm/ADT/Hashing.h" 18#include "llvm/ADT/None.h" 19#include "llvm/ADT/STLExtras.h" 20#include "llvm/ADT/SmallBitVector.h" 21#include "llvm/ADT/SmallString.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/Analysis/AliasAnalysis.h" 24#include "llvm/Analysis/Loads.h" 25#include "llvm/Analysis/MemoryLocation.h" 26#include "llvm/CodeGen/GlobalISel/RegisterBank.h" 27#include "llvm/CodeGen/MachineBasicBlock.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineFunction.h" 30#include "llvm/CodeGen/MachineInstrBuilder.h" 31#include "llvm/CodeGen/MachineInstrBundle.h" 32#include "llvm/CodeGen/MachineMemOperand.h" 33#include "llvm/CodeGen/MachineModuleInfo.h" 34#include "llvm/CodeGen/MachineOperand.h" 35#include "llvm/CodeGen/MachineRegisterInfo.h" 36#include "llvm/CodeGen/PseudoSourceValue.h" 37#include "llvm/CodeGen/TargetInstrInfo.h" 38#include "llvm/CodeGen/TargetRegisterInfo.h" 39#include "llvm/CodeGen/TargetSubtargetInfo.h" 40#include "llvm/Config/llvm-config.h" 41#include "llvm/IR/Constants.h" 42#include "llvm/IR/DebugInfoMetadata.h" 43#include "llvm/IR/DebugLoc.h" 44#include "llvm/IR/DerivedTypes.h" 45#include "llvm/IR/Function.h" 46#include "llvm/IR/InlineAsm.h" 47#include "llvm/IR/InstrTypes.h" 48#include "llvm/IR/Intrinsics.h" 49#include "llvm/IR/LLVMContext.h" 50#include "llvm/IR/Metadata.h" 51#include "llvm/IR/Module.h" 52#include "llvm/IR/ModuleSlotTracker.h" 53#include "llvm/IR/Operator.h" 54#include "llvm/IR/Type.h" 55#include "llvm/IR/Value.h" 56#include "llvm/MC/MCInstrDesc.h" 57#include "llvm/MC/MCRegisterInfo.h" 58#include "llvm/MC/MCSymbol.h" 59#include "llvm/Support/Casting.h" 60#include "llvm/Support/CommandLine.h" 61#include "llvm/Support/Compiler.h" 62#include "llvm/Support/Debug.h" 63#include "llvm/Support/ErrorHandling.h" 64#include "llvm/Support/FormattedStream.h" 65#include "llvm/Support/LowLevelTypeImpl.h" 66#include "llvm/Support/MathExtras.h" 67#include "llvm/Support/raw_ostream.h" 68#include "llvm/Target/TargetIntrinsicInfo.h" 69#include "llvm/Target/TargetMachine.h" 70#include <algorithm> 71#include <cassert> 72#include <cstddef> 73#include <cstdint> 74#include <cstring> 75#include <iterator> 76#include <utility> 77 78using namespace llvm; 79 80static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) { 81 if (const MachineBasicBlock *MBB = MI.getParent()) 82 if (const MachineFunction *MF = MBB->getParent()) 83 return MF; 84 return nullptr; 85} 86 87// Try to crawl up to the machine function and get TRI and IntrinsicInfo from 88// it. 89static void tryToGetTargetInfo(const MachineInstr &MI, 90 const TargetRegisterInfo *&TRI, 91 const MachineRegisterInfo *&MRI, 92 const TargetIntrinsicInfo *&IntrinsicInfo, 93 const TargetInstrInfo *&TII) { 94 95 if (const MachineFunction *MF = getMFIfAvailable(MI)) { 96 TRI = MF->getSubtarget().getRegisterInfo(); 97 MRI = &MF->getRegInfo(); 98 IntrinsicInfo = MF->getTarget().getIntrinsicInfo(); 99 TII = MF->getSubtarget().getInstrInfo(); 100 } 101} 102 103void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) { 104 if (MCID->ImplicitDefs) 105 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; 106 ++ImpDefs) 107 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true)); 108 if (MCID->ImplicitUses) 109 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses; 110 ++ImpUses) 111 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true)); 112} 113 114/// MachineInstr ctor - This constructor creates a MachineInstr and adds the 115/// implicit operands. It reserves space for the number of operands specified by 116/// the MCInstrDesc. 117MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid, 118 DebugLoc dl, bool NoImp) 119 : MCID(&tid), debugLoc(std::move(dl)) { 120 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor"); 121 122 // Reserve space for the expected number of operands. 123 if (unsigned NumOps = MCID->getNumOperands() + 124 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) { 125 CapOperands = OperandCapacity::get(NumOps); 126 Operands = MF.allocateOperandArray(CapOperands); 127 } 128 129 if (!NoImp) 130 addImplicitDefUseOperands(MF); 131} 132 133/// MachineInstr ctor - Copies MachineInstr arg exactly 134/// 135MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 136 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) { 137 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor"); 138 139 CapOperands = OperandCapacity::get(MI.getNumOperands()); 140 Operands = MF.allocateOperandArray(CapOperands); 141 142 // Copy operands. 143 for (const MachineOperand &MO : MI.operands()) 144 addOperand(MF, MO); 145 146 // Copy all the sensible flags. 147 setFlags(MI.Flags); 148} 149 150/// getRegInfo - If this instruction is embedded into a MachineFunction, 151/// return the MachineRegisterInfo object for the current function, otherwise 152/// return null. 153MachineRegisterInfo *MachineInstr::getRegInfo() { 154 if (MachineBasicBlock *MBB = getParent()) 155 return &MBB->getParent()->getRegInfo(); 156 return nullptr; 157} 158 159/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 160/// this instruction from their respective use lists. This requires that the 161/// operands already be on their use lists. 162void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { 163 for (MachineOperand &MO : operands()) 164 if (MO.isReg()) 165 MRI.removeRegOperandFromUseList(&MO); 166} 167 168/// AddRegOperandsToUseLists - Add all of the register operands in 169/// this instruction from their respective use lists. This requires that the 170/// operands not be on their use lists yet. 171void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { 172 for (MachineOperand &MO : operands()) 173 if (MO.isReg()) 174 MRI.addRegOperandToUseList(&MO); 175} 176 177void MachineInstr::addOperand(const MachineOperand &Op) { 178 MachineBasicBlock *MBB = getParent(); 179 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs"); 180 MachineFunction *MF = MBB->getParent(); 181 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs"); 182 addOperand(*MF, Op); 183} 184 185/// Move NumOps MachineOperands from Src to Dst, with support for overlapping 186/// ranges. If MRI is non-null also update use-def chains. 187static void moveOperands(MachineOperand *Dst, MachineOperand *Src, 188 unsigned NumOps, MachineRegisterInfo *MRI) { 189 if (MRI) 190 return MRI->moveOperands(Dst, Src, NumOps); 191 // MachineOperand is a trivially copyable type so we can just use memmove. 192 assert(Dst && Src && "Unknown operands"); 193 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand)); 194} 195 196/// addOperand - Add the specified operand to the instruction. If it is an 197/// implicit operand, it is added to the end of the operand list. If it is 198/// an explicit operand it is added at the end of the explicit operand list 199/// (before the first implicit operand). 200void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) { 201 assert(MCID && "Cannot add operands before providing an instr descriptor"); 202 203 // Check if we're adding one of our existing operands. 204 if (&Op >= Operands && &Op < Operands + NumOperands) { 205 // This is unusual: MI->addOperand(MI->getOperand(i)). 206 // If adding Op requires reallocating or moving existing operands around, 207 // the Op reference could go stale. Support it by copying Op. 208 MachineOperand CopyOp(Op); 209 return addOperand(MF, CopyOp); 210 } 211 212 // Find the insert location for the new operand. Implicit registers go at 213 // the end, everything else goes before the implicit regs. 214 // 215 // FIXME: Allow mixed explicit and implicit operands on inline asm. 216 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as 217 // implicit-defs, but they must not be moved around. See the FIXME in 218 // InstrEmitter.cpp. 219 unsigned OpNo = getNumOperands(); 220 bool isImpReg = Op.isReg() && Op.isImplicit(); 221 if (!isImpReg && !isInlineAsm()) { 222 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { 223 --OpNo; 224 assert(!Operands[OpNo].isTied() && "Cannot move tied operands"); 225 } 226 } 227 228#ifndef NDEBUG 229 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata || 230 Op.getType() == MachineOperand::MO_MCSymbol; 231 // OpNo now points as the desired insertion point. Unless this is a variadic 232 // instruction, only implicit regs are allowed beyond MCID->getNumOperands(). 233 // RegMask operands go between the explicit and implicit operands. 234 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || 235 OpNo < MCID->getNumOperands() || isDebugOp) && 236 "Trying to add an operand to a machine instr that is already done!"); 237#endif 238 239 MachineRegisterInfo *MRI = getRegInfo(); 240 241 // Determine if the Operands array needs to be reallocated. 242 // Save the old capacity and operand array. 243 OperandCapacity OldCap = CapOperands; 244 MachineOperand *OldOperands = Operands; 245 if (!OldOperands || OldCap.getSize() == getNumOperands()) { 246 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1); 247 Operands = MF.allocateOperandArray(CapOperands); 248 // Move the operands before the insertion point. 249 if (OpNo) 250 moveOperands(Operands, OldOperands, OpNo, MRI); 251 } 252 253 // Move the operands following the insertion point. 254 if (OpNo != NumOperands) 255 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo, 256 MRI); 257 ++NumOperands; 258 259 // Deallocate the old operand array. 260 if (OldOperands != Operands && OldOperands) 261 MF.deallocateOperandArray(OldCap, OldOperands); 262 263 // Copy Op into place. It still needs to be inserted into the MRI use lists. 264 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op); 265 NewMO->ParentMI = this; 266 267 // When adding a register operand, tell MRI about it. 268 if (NewMO->isReg()) { 269 // Ensure isOnRegUseList() returns false, regardless of Op's status. 270 NewMO->Contents.Reg.Prev = nullptr; 271 // Ignore existing ties. This is not a property that can be copied. 272 NewMO->TiedTo = 0; 273 // Add the new operand to MRI, but only for instructions in an MBB. 274 if (MRI) 275 MRI->addRegOperandToUseList(NewMO); 276 // The MCID operand information isn't accurate until we start adding 277 // explicit operands. The implicit operands are added first, then the 278 // explicits are inserted before them. 279 if (!isImpReg) { 280 // Tie uses to defs as indicated in MCInstrDesc. 281 if (NewMO->isUse()) { 282 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); 283 if (DefIdx != -1) 284 tieOperands(DefIdx, OpNo); 285 } 286 // If the register operand is flagged as early, mark the operand as such. 287 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) 288 NewMO->setIsEarlyClobber(true); 289 } 290 } 291} 292 293/// RemoveOperand - Erase an operand from an instruction, leaving it with one 294/// fewer operand than it started with. 295/// 296void MachineInstr::RemoveOperand(unsigned OpNo) { 297 assert(OpNo < getNumOperands() && "Invalid operand number"); 298 untieRegOperand(OpNo); 299 300#ifndef NDEBUG 301 // Moving tied operands would break the ties. 302 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i) 303 if (Operands[i].isReg()) 304 assert(!Operands[i].isTied() && "Cannot move tied operands"); 305#endif 306 307 MachineRegisterInfo *MRI = getRegInfo(); 308 if (MRI && Operands[OpNo].isReg()) 309 MRI->removeRegOperandFromUseList(Operands + OpNo); 310 311 // Don't call the MachineOperand destructor. A lot of this code depends on 312 // MachineOperand having a trivial destructor anyway, and adding a call here 313 // wouldn't make it 'destructor-correct'. 314 315 if (unsigned N = NumOperands - 1 - OpNo) 316 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI); 317 --NumOperands; 318} 319 320void MachineInstr::setExtraInfo(MachineFunction &MF, 321 ArrayRef<MachineMemOperand *> MMOs, 322 MCSymbol *PreInstrSymbol, 323 MCSymbol *PostInstrSymbol, 324 MDNode *HeapAllocMarker) { 325 bool HasPreInstrSymbol = PreInstrSymbol != nullptr; 326 bool HasPostInstrSymbol = PostInstrSymbol != nullptr; 327 bool HasHeapAllocMarker = HeapAllocMarker != nullptr; 328 int NumPointers = 329 MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker; 330 331 // Drop all extra info if there is none. 332 if (NumPointers <= 0) { 333 Info.clear(); 334 return; 335 } 336 337 // If more than one pointer, then store out of line. Store heap alloc markers 338 // out of line because PointerSumType cannot hold more than 4 tag types with 339 // 32-bit pointers. 340 // FIXME: Maybe we should make the symbols in the extra info mutable? 341 else if (NumPointers > 1 || HasHeapAllocMarker) { 342 Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo( 343 MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker)); 344 return; 345 } 346 347 // Otherwise store the single pointer inline. 348 if (HasPreInstrSymbol) 349 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol); 350 else if (HasPostInstrSymbol) 351 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol); 352 else 353 Info.set<EIIK_MMO>(MMOs[0]); 354} 355 356void MachineInstr::dropMemRefs(MachineFunction &MF) { 357 if (memoperands_empty()) 358 return; 359 360 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(), 361 getHeapAllocMarker()); 362} 363 364void MachineInstr::setMemRefs(MachineFunction &MF, 365 ArrayRef<MachineMemOperand *> MMOs) { 366 if (MMOs.empty()) { 367 dropMemRefs(MF); 368 return; 369 } 370 371 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(), 372 getHeapAllocMarker()); 373} 374 375void MachineInstr::addMemOperand(MachineFunction &MF, 376 MachineMemOperand *MO) { 377 SmallVector<MachineMemOperand *, 2> MMOs; 378 MMOs.append(memoperands_begin(), memoperands_end()); 379 MMOs.push_back(MO); 380 setMemRefs(MF, MMOs); 381} 382 383void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) { 384 if (this == &MI) 385 // Nothing to do for a self-clone! 386 return; 387 388 assert(&MF == MI.getMF() && 389 "Invalid machine functions when cloning memory refrences!"); 390 // See if we can just steal the extra info already allocated for the 391 // instruction. We can do this whenever the pre- and post-instruction symbols 392 // are the same (including null). 393 if (getPreInstrSymbol() == MI.getPreInstrSymbol() && 394 getPostInstrSymbol() == MI.getPostInstrSymbol() && 395 getHeapAllocMarker() == MI.getHeapAllocMarker()) { 396 Info = MI.Info; 397 return; 398 } 399 400 // Otherwise, fall back on a copy-based clone. 401 setMemRefs(MF, MI.memoperands()); 402} 403 404/// Check to see if the MMOs pointed to by the two MemRefs arrays are 405/// identical. 406static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS, 407 ArrayRef<MachineMemOperand *> RHS) { 408 if (LHS.size() != RHS.size()) 409 return false; 410 411 auto LHSPointees = make_pointee_range(LHS); 412 auto RHSPointees = make_pointee_range(RHS); 413 return std::equal(LHSPointees.begin(), LHSPointees.end(), 414 RHSPointees.begin()); 415} 416 417void MachineInstr::cloneMergedMemRefs(MachineFunction &MF, 418 ArrayRef<const MachineInstr *> MIs) { 419 // Try handling easy numbers of MIs with simpler mechanisms. 420 if (MIs.empty()) { 421 dropMemRefs(MF); 422 return; 423 } 424 if (MIs.size() == 1) { 425 cloneMemRefs(MF, *MIs[0]); 426 return; 427 } 428 // Because an empty memoperands list provides *no* information and must be 429 // handled conservatively (assuming the instruction can do anything), the only 430 // way to merge with it is to drop all other memoperands. 431 if (MIs[0]->memoperands_empty()) { 432 dropMemRefs(MF); 433 return; 434 } 435 436 // Handle the general case. 437 SmallVector<MachineMemOperand *, 2> MergedMMOs; 438 // Start with the first instruction. 439 assert(&MF == MIs[0]->getMF() && 440 "Invalid machine functions when cloning memory references!"); 441 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end()); 442 // Now walk all the other instructions and accumulate any different MMOs. 443 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) { 444 assert(&MF == MI.getMF() && 445 "Invalid machine functions when cloning memory references!"); 446 447 // Skip MIs with identical operands to the first. This is a somewhat 448 // arbitrary hack but will catch common cases without being quadratic. 449 // TODO: We could fully implement merge semantics here if needed. 450 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands())) 451 continue; 452 453 // Because an empty memoperands list provides *no* information and must be 454 // handled conservatively (assuming the instruction can do anything), the 455 // only way to merge with it is to drop all other memoperands. 456 if (MI.memoperands_empty()) { 457 dropMemRefs(MF); 458 return; 459 } 460 461 // Otherwise accumulate these into our temporary buffer of the merged state. 462 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end()); 463 } 464 465 setMemRefs(MF, MergedMMOs); 466} 467 468void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) { 469 // Do nothing if old and new symbols are the same. 470 if (Symbol == getPreInstrSymbol()) 471 return; 472 473 // If there was only one symbol and we're removing it, just clear info. 474 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) { 475 Info.clear(); 476 return; 477 } 478 479 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(), 480 getHeapAllocMarker()); 481} 482 483void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) { 484 // Do nothing if old and new symbols are the same. 485 if (Symbol == getPostInstrSymbol()) 486 return; 487 488 // If there was only one symbol and we're removing it, just clear info. 489 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) { 490 Info.clear(); 491 return; 492 } 493 494 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol, 495 getHeapAllocMarker()); 496} 497 498void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) { 499 // Do nothing if old and new symbols are the same. 500 if (Marker == getHeapAllocMarker()) 501 return; 502 503 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(), 504 Marker); 505} 506 507void MachineInstr::cloneInstrSymbols(MachineFunction &MF, 508 const MachineInstr &MI) { 509 if (this == &MI) 510 // Nothing to do for a self-clone! 511 return; 512 513 assert(&MF == MI.getMF() && 514 "Invalid machine functions when cloning instruction symbols!"); 515 516 setPreInstrSymbol(MF, MI.getPreInstrSymbol()); 517 setPostInstrSymbol(MF, MI.getPostInstrSymbol()); 518 setHeapAllocMarker(MF, MI.getHeapAllocMarker()); 519} 520 521uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const { 522 // For now, the just return the union of the flags. If the flags get more 523 // complicated over time, we might need more logic here. 524 return getFlags() | Other.getFlags(); 525} 526 527uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) { 528 uint16_t MIFlags = 0; 529 // Copy the wrapping flags. 530 if (const OverflowingBinaryOperator *OB = 531 dyn_cast<OverflowingBinaryOperator>(&I)) { 532 if (OB->hasNoSignedWrap()) 533 MIFlags |= MachineInstr::MIFlag::NoSWrap; 534 if (OB->hasNoUnsignedWrap()) 535 MIFlags |= MachineInstr::MIFlag::NoUWrap; 536 } 537 538 // Copy the exact flag. 539 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I)) 540 if (PE->isExact()) 541 MIFlags |= MachineInstr::MIFlag::IsExact; 542 543 // Copy the fast-math flags. 544 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) { 545 const FastMathFlags Flags = FP->getFastMathFlags(); 546 if (Flags.noNaNs()) 547 MIFlags |= MachineInstr::MIFlag::FmNoNans; 548 if (Flags.noInfs()) 549 MIFlags |= MachineInstr::MIFlag::FmNoInfs; 550 if (Flags.noSignedZeros()) 551 MIFlags |= MachineInstr::MIFlag::FmNsz; 552 if (Flags.allowReciprocal()) 553 MIFlags |= MachineInstr::MIFlag::FmArcp; 554 if (Flags.allowContract()) 555 MIFlags |= MachineInstr::MIFlag::FmContract; 556 if (Flags.approxFunc()) 557 MIFlags |= MachineInstr::MIFlag::FmAfn; 558 if (Flags.allowReassoc()) 559 MIFlags |= MachineInstr::MIFlag::FmReassoc; 560 } 561 562 return MIFlags; 563} 564 565void MachineInstr::copyIRFlags(const Instruction &I) { 566 Flags = copyFlagsFromInstruction(I); 567} 568 569bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const { 570 assert(!isBundledWithPred() && "Must be called on bundle header"); 571 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) { 572 if (MII->getDesc().getFlags() & Mask) { 573 if (Type == AnyInBundle) 574 return true; 575 } else { 576 if (Type == AllInBundle && !MII->isBundle()) 577 return false; 578 } 579 // This was the last instruction in the bundle. 580 if (!MII->isBundledWithSucc()) 581 return Type == AllInBundle; 582 } 583} 584 585bool MachineInstr::isIdenticalTo(const MachineInstr &Other, 586 MICheckType Check) const { 587 // If opcodes or number of operands are not the same then the two 588 // instructions are obviously not identical. 589 if (Other.getOpcode() != getOpcode() || 590 Other.getNumOperands() != getNumOperands()) 591 return false; 592 593 if (isBundle()) { 594 // We have passed the test above that both instructions have the same 595 // opcode, so we know that both instructions are bundles here. Let's compare 596 // MIs inside the bundle. 597 assert(Other.isBundle() && "Expected that both instructions are bundles."); 598 MachineBasicBlock::const_instr_iterator I1 = getIterator(); 599 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator(); 600 // Loop until we analysed the last intruction inside at least one of the 601 // bundles. 602 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) { 603 ++I1; 604 ++I2; 605 if (!I1->isIdenticalTo(*I2, Check)) 606 return false; 607 } 608 // If we've reached the end of just one of the two bundles, but not both, 609 // the instructions are not identical. 610 if (I1->isBundledWithSucc() || I2->isBundledWithSucc()) 611 return false; 612 } 613 614 // Check operands to make sure they match. 615 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 616 const MachineOperand &MO = getOperand(i); 617 const MachineOperand &OMO = Other.getOperand(i); 618 if (!MO.isReg()) { 619 if (!MO.isIdenticalTo(OMO)) 620 return false; 621 continue; 622 } 623 624 // Clients may or may not want to ignore defs when testing for equality. 625 // For example, machine CSE pass only cares about finding common 626 // subexpressions, so it's safe to ignore virtual register defs. 627 if (MO.isDef()) { 628 if (Check == IgnoreDefs) 629 continue; 630 else if (Check == IgnoreVRegDefs) { 631 if (!Register::isVirtualRegister(MO.getReg()) || 632 !Register::isVirtualRegister(OMO.getReg())) 633 if (!MO.isIdenticalTo(OMO)) 634 return false; 635 } else { 636 if (!MO.isIdenticalTo(OMO)) 637 return false; 638 if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) 639 return false; 640 } 641 } else { 642 if (!MO.isIdenticalTo(OMO)) 643 return false; 644 if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) 645 return false; 646 } 647 } 648 // If DebugLoc does not match then two debug instructions are not identical. 649 if (isDebugInstr()) 650 if (getDebugLoc() && Other.getDebugLoc() && 651 getDebugLoc() != Other.getDebugLoc()) 652 return false; 653 return true; 654} 655 656const MachineFunction *MachineInstr::getMF() const { 657 return getParent()->getParent(); 658} 659 660MachineInstr *MachineInstr::removeFromParent() { 661 assert(getParent() && "Not embedded in a basic block!"); 662 return getParent()->remove(this); 663} 664 665MachineInstr *MachineInstr::removeFromBundle() { 666 assert(getParent() && "Not embedded in a basic block!"); 667 return getParent()->remove_instr(this); 668} 669 670void MachineInstr::eraseFromParent() { 671 assert(getParent() && "Not embedded in a basic block!"); 672 getParent()->erase(this); 673} 674 675void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() { 676 assert(getParent() && "Not embedded in a basic block!"); 677 MachineBasicBlock *MBB = getParent(); 678 MachineFunction *MF = MBB->getParent(); 679 assert(MF && "Not embedded in a function!"); 680 681 MachineInstr *MI = (MachineInstr *)this; 682 MachineRegisterInfo &MRI = MF->getRegInfo(); 683 684 for (const MachineOperand &MO : MI->operands()) { 685 if (!MO.isReg() || !MO.isDef()) 686 continue; 687 Register Reg = MO.getReg(); 688 if (!Reg.isVirtual()) 689 continue; 690 MRI.markUsesInDebugValueAsUndef(Reg); 691 } 692 MI->eraseFromParent(); 693} 694 695void MachineInstr::eraseFromBundle() { 696 assert(getParent() && "Not embedded in a basic block!"); 697 getParent()->erase_instr(this); 698} 699 700bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const { 701 if (!isCall(Type)) 702 return false; 703 switch (getOpcode()) { 704 case TargetOpcode::PATCHABLE_EVENT_CALL: 705 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL: 706 case TargetOpcode::PATCHPOINT: 707 case TargetOpcode::STACKMAP: 708 case TargetOpcode::STATEPOINT: 709 return false; 710 } 711 return true; 712} 713 714bool MachineInstr::shouldUpdateCallSiteInfo() const { 715 if (isBundle()) 716 return isCandidateForCallSiteEntry(MachineInstr::AnyInBundle); 717 return isCandidateForCallSiteEntry(); 718} 719 720unsigned MachineInstr::getNumExplicitOperands() const { 721 unsigned NumOperands = MCID->getNumOperands(); 722 if (!MCID->isVariadic()) 723 return NumOperands; 724 725 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) { 726 const MachineOperand &MO = getOperand(I); 727 // The operands must always be in the following order: 728 // - explicit reg defs, 729 // - other explicit operands (reg uses, immediates, etc.), 730 // - implicit reg defs 731 // - implicit reg uses 732 if (MO.isReg() && MO.isImplicit()) 733 break; 734 ++NumOperands; 735 } 736 return NumOperands; 737} 738 739unsigned MachineInstr::getNumExplicitDefs() const { 740 unsigned NumDefs = MCID->getNumDefs(); 741 if (!MCID->isVariadic()) 742 return NumDefs; 743 744 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) { 745 const MachineOperand &MO = getOperand(I); 746 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) 747 break; 748 ++NumDefs; 749 } 750 return NumDefs; 751} 752 753void MachineInstr::bundleWithPred() { 754 assert(!isBundledWithPred() && "MI is already bundled with its predecessor"); 755 setFlag(BundledPred); 756 MachineBasicBlock::instr_iterator Pred = getIterator(); 757 --Pred; 758 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags"); 759 Pred->setFlag(BundledSucc); 760} 761 762void MachineInstr::bundleWithSucc() { 763 assert(!isBundledWithSucc() && "MI is already bundled with its successor"); 764 setFlag(BundledSucc); 765 MachineBasicBlock::instr_iterator Succ = getIterator(); 766 ++Succ; 767 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags"); 768 Succ->setFlag(BundledPred); 769} 770 771void MachineInstr::unbundleFromPred() { 772 assert(isBundledWithPred() && "MI isn't bundled with its predecessor"); 773 clearFlag(BundledPred); 774 MachineBasicBlock::instr_iterator Pred = getIterator(); 775 --Pred; 776 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags"); 777 Pred->clearFlag(BundledSucc); 778} 779 780void MachineInstr::unbundleFromSucc() { 781 assert(isBundledWithSucc() && "MI isn't bundled with its successor"); 782 clearFlag(BundledSucc); 783 MachineBasicBlock::instr_iterator Succ = getIterator(); 784 ++Succ; 785 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags"); 786 Succ->clearFlag(BundledPred); 787} 788 789bool MachineInstr::isStackAligningInlineAsm() const { 790 if (isInlineAsm()) { 791 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 792 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 793 return true; 794 } 795 return false; 796} 797 798InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const { 799 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!"); 800 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 801 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0); 802} 803 804int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, 805 unsigned *GroupNo) const { 806 assert(isInlineAsm() && "Expected an inline asm instruction"); 807 assert(OpIdx < getNumOperands() && "OpIdx out of range"); 808 809 // Ignore queries about the initial operands. 810 if (OpIdx < InlineAsm::MIOp_FirstOperand) 811 return -1; 812 813 unsigned Group = 0; 814 unsigned NumOps; 815 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 816 i += NumOps) { 817 const MachineOperand &FlagMO = getOperand(i); 818 // If we reach the implicit register operands, stop looking. 819 if (!FlagMO.isImm()) 820 return -1; 821 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 822 if (i + NumOps > OpIdx) { 823 if (GroupNo) 824 *GroupNo = Group; 825 return i; 826 } 827 ++Group; 828 } 829 return -1; 830} 831 832const DILabel *MachineInstr::getDebugLabel() const { 833 assert(isDebugLabel() && "not a DBG_LABEL"); 834 return cast<DILabel>(getOperand(0).getMetadata()); 835} 836 837const MachineOperand &MachineInstr::getDebugVariableOp() const { 838 assert(isDebugValue() && "not a DBG_VALUE"); 839 return getOperand(2); 840} 841 842MachineOperand &MachineInstr::getDebugVariableOp() { 843 assert(isDebugValue() && "not a DBG_VALUE"); 844 return getOperand(2); 845} 846 847const DILocalVariable *MachineInstr::getDebugVariable() const { 848 assert(isDebugValue() && "not a DBG_VALUE"); 849 return cast<DILocalVariable>(getOperand(2).getMetadata()); 850} 851 852MachineOperand &MachineInstr::getDebugExpressionOp() { 853 assert(isDebugValue() && "not a DBG_VALUE"); 854 return getOperand(3); 855} 856 857const DIExpression *MachineInstr::getDebugExpression() const { 858 assert(isDebugValue() && "not a DBG_VALUE"); 859 return cast<DIExpression>(getOperand(3).getMetadata()); 860} 861 862bool MachineInstr::isDebugEntryValue() const { 863 return isDebugValue() && getDebugExpression()->isEntryValue(); 864} 865 866const TargetRegisterClass* 867MachineInstr::getRegClassConstraint(unsigned OpIdx, 868 const TargetInstrInfo *TII, 869 const TargetRegisterInfo *TRI) const { 870 assert(getParent() && "Can't have an MBB reference here!"); 871 assert(getMF() && "Can't have an MF reference here!"); 872 const MachineFunction &MF = *getMF(); 873 874 // Most opcodes have fixed constraints in their MCInstrDesc. 875 if (!isInlineAsm()) 876 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); 877 878 if (!getOperand(OpIdx).isReg()) 879 return nullptr; 880 881 // For tied uses on inline asm, get the constraint from the def. 882 unsigned DefIdx; 883 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 884 OpIdx = DefIdx; 885 886 // Inline asm stores register class constraints in the flag word. 887 int FlagIdx = findInlineAsmFlagIdx(OpIdx); 888 if (FlagIdx < 0) 889 return nullptr; 890 891 unsigned Flag = getOperand(FlagIdx).getImm(); 892 unsigned RCID; 893 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse || 894 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef || 895 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) && 896 InlineAsm::hasRegClassConstraint(Flag, RCID)) 897 return TRI->getRegClass(RCID); 898 899 // Assume that all registers in a memory operand are pointers. 900 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem) 901 return TRI->getPointerRegClass(MF); 902 903 return nullptr; 904} 905 906const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg( 907 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, 908 const TargetRegisterInfo *TRI, bool ExploreBundle) const { 909 // Check every operands inside the bundle if we have 910 // been asked to. 911 if (ExploreBundle) 912 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC; 913 ++OpndIt) 914 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl( 915 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI); 916 else 917 // Otherwise, just check the current operands. 918 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i) 919 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI); 920 return CurRC; 921} 922 923const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl( 924 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC, 925 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const { 926 assert(CurRC && "Invalid initial register class"); 927 // Check if Reg is constrained by some of its use/def from MI. 928 const MachineOperand &MO = getOperand(OpIdx); 929 if (!MO.isReg() || MO.getReg() != Reg) 930 return CurRC; 931 // If yes, accumulate the constraints through the operand. 932 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI); 933} 934 935const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect( 936 unsigned OpIdx, const TargetRegisterClass *CurRC, 937 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const { 938 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); 939 const MachineOperand &MO = getOperand(OpIdx); 940 assert(MO.isReg() && 941 "Cannot get register constraints for non-register operand"); 942 assert(CurRC && "Invalid initial register class"); 943 if (unsigned SubIdx = MO.getSubReg()) { 944 if (OpRC) 945 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); 946 else 947 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx); 948 } else if (OpRC) 949 CurRC = TRI->getCommonSubClass(CurRC, OpRC); 950 return CurRC; 951} 952 953/// Return the number of instructions inside the MI bundle, not counting the 954/// header instruction. 955unsigned MachineInstr::getBundleSize() const { 956 MachineBasicBlock::const_instr_iterator I = getIterator(); 957 unsigned Size = 0; 958 while (I->isBundledWithSucc()) { 959 ++Size; 960 ++I; 961 } 962 return Size; 963} 964 965/// Returns true if the MachineInstr has an implicit-use operand of exactly 966/// the given register (not considering sub/super-registers). 967bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const { 968 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 969 const MachineOperand &MO = getOperand(i); 970 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg) 971 return true; 972 } 973 return false; 974} 975 976/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 977/// the specific register or -1 if it is not found. It further tightens 978/// the search criteria to a use that kills the register if isKill is true. 979int MachineInstr::findRegisterUseOperandIdx( 980 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const { 981 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 982 const MachineOperand &MO = getOperand(i); 983 if (!MO.isReg() || !MO.isUse()) 984 continue; 985 Register MOReg = MO.getReg(); 986 if (!MOReg) 987 continue; 988 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg))) 989 if (!isKill || MO.isKill()) 990 return i; 991 } 992 return -1; 993} 994 995/// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 996/// indicating if this instruction reads or writes Reg. This also considers 997/// partial defines. 998std::pair<bool,bool> 999MachineInstr::readsWritesVirtualRegister(Register Reg, 1000 SmallVectorImpl<unsigned> *Ops) const { 1001 bool PartDef = false; // Partial redefine. 1002 bool FullDef = false; // Full define. 1003 bool Use = false; 1004 1005 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1006 const MachineOperand &MO = getOperand(i); 1007 if (!MO.isReg() || MO.getReg() != Reg) 1008 continue; 1009 if (Ops) 1010 Ops->push_back(i); 1011 if (MO.isUse()) 1012 Use |= !MO.isUndef(); 1013 else if (MO.getSubReg() && !MO.isUndef()) 1014 // A partial def undef doesn't count as reading the register. 1015 PartDef = true; 1016 else 1017 FullDef = true; 1018 } 1019 // A partial redefine uses Reg unless there is also a full define. 1020 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef); 1021} 1022 1023/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 1024/// the specified register or -1 if it is not found. If isDead is true, defs 1025/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 1026/// also checks if there is a def of a super-register. 1027int 1028MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap, 1029 const TargetRegisterInfo *TRI) const { 1030 bool isPhys = Register::isPhysicalRegister(Reg); 1031 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1032 const MachineOperand &MO = getOperand(i); 1033 // Accept regmask operands when Overlap is set. 1034 // Ignore them when looking for a specific def operand (Overlap == false). 1035 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) 1036 return i; 1037 if (!MO.isReg() || !MO.isDef()) 1038 continue; 1039 Register MOReg = MO.getReg(); 1040 bool Found = (MOReg == Reg); 1041 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) { 1042 if (Overlap) 1043 Found = TRI->regsOverlap(MOReg, Reg); 1044 else 1045 Found = TRI->isSubRegister(MOReg, Reg); 1046 } 1047 if (Found && (!isDead || MO.isDead())) 1048 return i; 1049 } 1050 return -1; 1051} 1052 1053/// findFirstPredOperandIdx() - Find the index of the first operand in the 1054/// operand list that is used to represent the predicate. It returns -1 if 1055/// none is found. 1056int MachineInstr::findFirstPredOperandIdx() const { 1057 // Don't call MCID.findFirstPredOperandIdx() because this variant 1058 // is sometimes called on an instruction that's not yet complete, and 1059 // so the number of operands is less than the MCID indicates. In 1060 // particular, the PTX target does this. 1061 const MCInstrDesc &MCID = getDesc(); 1062 if (MCID.isPredicable()) { 1063 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 1064 if (MCID.OpInfo[i].isPredicate()) 1065 return i; 1066 } 1067 1068 return -1; 1069} 1070 1071// MachineOperand::TiedTo is 4 bits wide. 1072const unsigned TiedMax = 15; 1073 1074/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. 1075/// 1076/// Use and def operands can be tied together, indicated by a non-zero TiedTo 1077/// field. TiedTo can have these values: 1078/// 1079/// 0: Operand is not tied to anything. 1080/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1). 1081/// TiedMax: Tied to an operand >= TiedMax-1. 1082/// 1083/// The tied def must be one of the first TiedMax operands on a normal 1084/// instruction. INLINEASM instructions allow more tied defs. 1085/// 1086void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { 1087 MachineOperand &DefMO = getOperand(DefIdx); 1088 MachineOperand &UseMO = getOperand(UseIdx); 1089 assert(DefMO.isDef() && "DefIdx must be a def operand"); 1090 assert(UseMO.isUse() && "UseIdx must be a use operand"); 1091 assert(!DefMO.isTied() && "Def is already tied to another use"); 1092 assert(!UseMO.isTied() && "Use is already tied to another def"); 1093 1094 if (DefIdx < TiedMax) 1095 UseMO.TiedTo = DefIdx + 1; 1096 else { 1097 // Inline asm can use the group descriptors to find tied operands, but on 1098 // normal instruction, the tied def must be within the first TiedMax 1099 // operands. 1100 assert(isInlineAsm() && "DefIdx out of range"); 1101 UseMO.TiedTo = TiedMax; 1102 } 1103 1104 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx(). 1105 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); 1106} 1107 1108/// Given the index of a tied register operand, find the operand it is tied to. 1109/// Defs are tied to uses and vice versa. Returns the index of the tied operand 1110/// which must exist. 1111unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const { 1112 const MachineOperand &MO = getOperand(OpIdx); 1113 assert(MO.isTied() && "Operand isn't tied"); 1114 1115 // Normally TiedTo is in range. 1116 if (MO.TiedTo < TiedMax) 1117 return MO.TiedTo - 1; 1118 1119 // Uses on normal instructions can be out of range. 1120 if (!isInlineAsm()) { 1121 // Normal tied defs must be in the 0..TiedMax-1 range. 1122 if (MO.isUse()) 1123 return TiedMax - 1; 1124 // MO is a def. Search for the tied use. 1125 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) { 1126 const MachineOperand &UseMO = getOperand(i); 1127 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) 1128 return i; 1129 } 1130 llvm_unreachable("Can't find tied use"); 1131 } 1132 1133 // Now deal with inline asm by parsing the operand group descriptor flags. 1134 // Find the beginning of each operand group. 1135 SmallVector<unsigned, 8> GroupIdx; 1136 unsigned OpIdxGroup = ~0u; 1137 unsigned NumOps; 1138 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 1139 i += NumOps) { 1140 const MachineOperand &FlagMO = getOperand(i); 1141 assert(FlagMO.isImm() && "Invalid tied operand on inline asm"); 1142 unsigned CurGroup = GroupIdx.size(); 1143 GroupIdx.push_back(i); 1144 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 1145 // OpIdx belongs to this operand group. 1146 if (OpIdx > i && OpIdx < i + NumOps) 1147 OpIdxGroup = CurGroup; 1148 unsigned TiedGroup; 1149 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup)) 1150 continue; 1151 // Operands in this group are tied to operands in TiedGroup which must be 1152 // earlier. Find the number of operands between the two groups. 1153 unsigned Delta = i - GroupIdx[TiedGroup]; 1154 1155 // OpIdx is a use tied to TiedGroup. 1156 if (OpIdxGroup == CurGroup) 1157 return OpIdx - Delta; 1158 1159 // OpIdx is a def tied to this use group. 1160 if (OpIdxGroup == TiedGroup) 1161 return OpIdx + Delta; 1162 } 1163 llvm_unreachable("Invalid tied operand on inline asm"); 1164} 1165 1166/// clearKillInfo - Clears kill flags on all operands. 1167/// 1168void MachineInstr::clearKillInfo() { 1169 for (MachineOperand &MO : operands()) { 1170 if (MO.isReg() && MO.isUse()) 1171 MO.setIsKill(false); 1172 } 1173} 1174 1175void MachineInstr::substituteRegister(Register FromReg, Register ToReg, 1176 unsigned SubIdx, 1177 const TargetRegisterInfo &RegInfo) { 1178 if (Register::isPhysicalRegister(ToReg)) { 1179 if (SubIdx) 1180 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1181 for (MachineOperand &MO : operands()) { 1182 if (!MO.isReg() || MO.getReg() != FromReg) 1183 continue; 1184 MO.substPhysReg(ToReg, RegInfo); 1185 } 1186 } else { 1187 for (MachineOperand &MO : operands()) { 1188 if (!MO.isReg() || MO.getReg() != FromReg) 1189 continue; 1190 MO.substVirtReg(ToReg, SubIdx, RegInfo); 1191 } 1192 } 1193} 1194 1195/// isSafeToMove - Return true if it is safe to move this instruction. If 1196/// SawStore is set to true, it means that there is a store (or call) between 1197/// the instruction's location and its intended destination. 1198bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const { 1199 // Ignore stuff that we obviously can't move. 1200 // 1201 // Treat volatile loads as stores. This is not strictly necessary for 1202 // volatiles, but it is required for atomic loads. It is not allowed to move 1203 // a load across an atomic load with Ordering > Monotonic. 1204 if (mayStore() || isCall() || isPHI() || 1205 (mayLoad() && hasOrderedMemoryRef())) { 1206 SawStore = true; 1207 return false; 1208 } 1209 1210 if (isPosition() || isDebugInstr() || isTerminator() || 1211 mayRaiseFPException() || hasUnmodeledSideEffects()) 1212 return false; 1213 1214 // See if this instruction does a load. If so, we have to guarantee that the 1215 // loaded value doesn't change between the load and the its intended 1216 // destination. The check for isInvariantLoad gives the targe the chance to 1217 // classify the load as always returning a constant, e.g. a constant pool 1218 // load. 1219 if (mayLoad() && !isDereferenceableInvariantLoad(AA)) 1220 // Otherwise, this is a real load. If there is a store between the load and 1221 // end of block, we can't move it. 1222 return !SawStore; 1223 1224 return true; 1225} 1226 1227bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other, 1228 bool UseTBAA) const { 1229 const MachineFunction *MF = getMF(); 1230 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); 1231 const MachineFrameInfo &MFI = MF->getFrameInfo(); 1232 1233 // If neither instruction stores to memory, they can't alias in any 1234 // meaningful way, even if they read from the same address. 1235 if (!mayStore() && !Other.mayStore()) 1236 return false; 1237 1238 // Both instructions must be memory operations to be able to alias. 1239 if (!mayLoadOrStore() || !Other.mayLoadOrStore()) 1240 return false; 1241 1242 // Let the target decide if memory accesses cannot possibly overlap. 1243 if (TII->areMemAccessesTriviallyDisjoint(*this, Other)) 1244 return false; 1245 1246 // FIXME: Need to handle multiple memory operands to support all targets. 1247 if (!hasOneMemOperand() || !Other.hasOneMemOperand()) 1248 return true; 1249 1250 MachineMemOperand *MMOa = *memoperands_begin(); 1251 MachineMemOperand *MMOb = *Other.memoperands_begin(); 1252 1253 // The following interface to AA is fashioned after DAGCombiner::isAlias 1254 // and operates with MachineMemOperand offset with some important 1255 // assumptions: 1256 // - LLVM fundamentally assumes flat address spaces. 1257 // - MachineOperand offset can *only* result from legalization and 1258 // cannot affect queries other than the trivial case of overlap 1259 // checking. 1260 // - These offsets never wrap and never step outside 1261 // of allocated objects. 1262 // - There should never be any negative offsets here. 1263 // 1264 // FIXME: Modify API to hide this math from "user" 1265 // Even before we go to AA we can reason locally about some 1266 // memory objects. It can save compile time, and possibly catch some 1267 // corner cases not currently covered. 1268 1269 int64_t OffsetA = MMOa->getOffset(); 1270 int64_t OffsetB = MMOb->getOffset(); 1271 int64_t MinOffset = std::min(OffsetA, OffsetB); 1272 1273 uint64_t WidthA = MMOa->getSize(); 1274 uint64_t WidthB = MMOb->getSize(); 1275 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize; 1276 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize; 1277 1278 const Value *ValA = MMOa->getValue(); 1279 const Value *ValB = MMOb->getValue(); 1280 bool SameVal = (ValA && ValB && (ValA == ValB)); 1281 if (!SameVal) { 1282 const PseudoSourceValue *PSVa = MMOa->getPseudoValue(); 1283 const PseudoSourceValue *PSVb = MMOb->getPseudoValue(); 1284 if (PSVa && ValB && !PSVa->mayAlias(&MFI)) 1285 return false; 1286 if (PSVb && ValA && !PSVb->mayAlias(&MFI)) 1287 return false; 1288 if (PSVa && PSVb && (PSVa == PSVb)) 1289 SameVal = true; 1290 } 1291 1292 if (SameVal) { 1293 if (!KnownWidthA || !KnownWidthB) 1294 return true; 1295 int64_t MaxOffset = std::max(OffsetA, OffsetB); 1296 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB; 1297 return (MinOffset + LowWidth > MaxOffset); 1298 } 1299 1300 if (!AA) 1301 return true; 1302 1303 if (!ValA || !ValB) 1304 return true; 1305 1306 assert((OffsetA >= 0) && "Negative MachineMemOperand offset"); 1307 assert((OffsetB >= 0) && "Negative MachineMemOperand offset"); 1308 1309 int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset 1310 : MemoryLocation::UnknownSize; 1311 int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset 1312 : MemoryLocation::UnknownSize; 1313 1314 AliasResult AAResult = AA->alias( 1315 MemoryLocation(ValA, OverlapA, 1316 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()), 1317 MemoryLocation(ValB, OverlapB, 1318 UseTBAA ? MMOb->getAAInfo() : AAMDNodes())); 1319 1320 return (AAResult != NoAlias); 1321} 1322 1323/// hasOrderedMemoryRef - Return true if this instruction may have an ordered 1324/// or volatile memory reference, or if the information describing the memory 1325/// reference is not available. Return false if it is known to have no ordered 1326/// memory references. 1327bool MachineInstr::hasOrderedMemoryRef() const { 1328 // An instruction known never to access memory won't have a volatile access. 1329 if (!mayStore() && 1330 !mayLoad() && 1331 !isCall() && 1332 !hasUnmodeledSideEffects()) 1333 return false; 1334 1335 // Otherwise, if the instruction has no memory reference information, 1336 // conservatively assume it wasn't preserved. 1337 if (memoperands_empty()) 1338 return true; 1339 1340 // Check if any of our memory operands are ordered. 1341 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) { 1342 return !MMO->isUnordered(); 1343 }); 1344} 1345 1346/// isDereferenceableInvariantLoad - Return true if this instruction will never 1347/// trap and is loading from a location whose value is invariant across a run of 1348/// this function. 1349bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const { 1350 // If the instruction doesn't load at all, it isn't an invariant load. 1351 if (!mayLoad()) 1352 return false; 1353 1354 // If the instruction has lost its memoperands, conservatively assume that 1355 // it may not be an invariant load. 1356 if (memoperands_empty()) 1357 return false; 1358 1359 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo(); 1360 1361 for (MachineMemOperand *MMO : memoperands()) { 1362 if (!MMO->isUnordered()) 1363 // If the memory operand has ordering side effects, we can't move the 1364 // instruction. Such an instruction is technically an invariant load, 1365 // but the caller code would need updated to expect that. 1366 return false; 1367 if (MMO->isStore()) return false; 1368 if (MMO->isInvariant() && MMO->isDereferenceable()) 1369 continue; 1370 1371 // A load from a constant PseudoSourceValue is invariant. 1372 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) 1373 if (PSV->isConstant(&MFI)) 1374 continue; 1375 1376 if (const Value *V = MMO->getValue()) { 1377 // If we have an AliasAnalysis, ask it whether the memory is constant. 1378 if (AA && 1379 AA->pointsToConstantMemory( 1380 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo()))) 1381 continue; 1382 } 1383 1384 // Otherwise assume conservatively. 1385 return false; 1386 } 1387 1388 // Everything checks out. 1389 return true; 1390} 1391 1392/// isConstantValuePHI - If the specified instruction is a PHI that always 1393/// merges together the same virtual register, return the register, otherwise 1394/// return 0. 1395unsigned MachineInstr::isConstantValuePHI() const { 1396 if (!isPHI()) 1397 return 0; 1398 assert(getNumOperands() >= 3 && 1399 "It's illegal to have a PHI without source operands"); 1400 1401 Register Reg = getOperand(1).getReg(); 1402 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1403 if (getOperand(i).getReg() != Reg) 1404 return 0; 1405 return Reg; 1406} 1407 1408bool MachineInstr::hasUnmodeledSideEffects() const { 1409 if (hasProperty(MCID::UnmodeledSideEffects)) 1410 return true; 1411 if (isInlineAsm()) { 1412 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1413 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1414 return true; 1415 } 1416 1417 return false; 1418} 1419 1420bool MachineInstr::isLoadFoldBarrier() const { 1421 return mayStore() || isCall() || hasUnmodeledSideEffects(); 1422} 1423 1424/// allDefsAreDead - Return true if all the defs of this instruction are dead. 1425/// 1426bool MachineInstr::allDefsAreDead() const { 1427 for (const MachineOperand &MO : operands()) { 1428 if (!MO.isReg() || MO.isUse()) 1429 continue; 1430 if (!MO.isDead()) 1431 return false; 1432 } 1433 return true; 1434} 1435 1436/// copyImplicitOps - Copy implicit register operands from specified 1437/// instruction to this instruction. 1438void MachineInstr::copyImplicitOps(MachineFunction &MF, 1439 const MachineInstr &MI) { 1440 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands(); 1441 i != e; ++i) { 1442 const MachineOperand &MO = MI.getOperand(i); 1443 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) 1444 addOperand(MF, MO); 1445 } 1446} 1447 1448bool MachineInstr::hasComplexRegisterTies() const { 1449 const MCInstrDesc &MCID = getDesc(); 1450 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) { 1451 const auto &Operand = getOperand(I); 1452 if (!Operand.isReg() || Operand.isDef()) 1453 // Ignore the defined registers as MCID marks only the uses as tied. 1454 continue; 1455 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); 1456 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1; 1457 if (ExpectedTiedIdx != TiedIdx) 1458 return true; 1459 } 1460 return false; 1461} 1462 1463LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, 1464 const MachineRegisterInfo &MRI) const { 1465 const MachineOperand &Op = getOperand(OpIdx); 1466 if (!Op.isReg()) 1467 return LLT{}; 1468 1469 if (isVariadic() || OpIdx >= getNumExplicitOperands()) 1470 return MRI.getType(Op.getReg()); 1471 1472 auto &OpInfo = getDesc().OpInfo[OpIdx]; 1473 if (!OpInfo.isGenericType()) 1474 return MRI.getType(Op.getReg()); 1475 1476 if (PrintedTypes[OpInfo.getGenericTypeIndex()]) 1477 return LLT{}; 1478 1479 LLT TypeToPrint = MRI.getType(Op.getReg()); 1480 // Don't mark the type index printed if it wasn't actually printed: maybe 1481 // another operand with the same type index has an actual type attached: 1482 if (TypeToPrint.isValid()) 1483 PrintedTypes.set(OpInfo.getGenericTypeIndex()); 1484 return TypeToPrint; 1485} 1486 1487#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 1488LLVM_DUMP_METHOD void MachineInstr::dump() const { 1489 dbgs() << " "; 1490 print(dbgs()); 1491} 1492 1493LLVM_DUMP_METHOD void MachineInstr::dumprImpl( 1494 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth, 1495 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const { 1496 if (Depth >= MaxDepth) 1497 return; 1498 if (!AlreadySeenInstrs.insert(this).second) 1499 return; 1500 // PadToColumn always inserts at least one space. 1501 // Don't mess up the alignment if we don't want any space. 1502 if (Depth) 1503 fdbgs().PadToColumn(Depth * 2); 1504 print(fdbgs()); 1505 for (const MachineOperand &MO : operands()) { 1506 if (!MO.isReg() || MO.isDef()) 1507 continue; 1508 Register Reg = MO.getReg(); 1509 if (Reg.isPhysical()) 1510 continue; 1511 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg); 1512 if (NewMI == nullptr) 1513 continue; 1514 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs); 1515 } 1516} 1517 1518LLVM_DUMP_METHOD void MachineInstr::dumpr(const MachineRegisterInfo &MRI, 1519 unsigned MaxDepth) const { 1520 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs; 1521 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs); 1522} 1523#endif 1524 1525void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers, 1526 bool SkipDebugLoc, bool AddNewLine, 1527 const TargetInstrInfo *TII) const { 1528 const Module *M = nullptr; 1529 const Function *F = nullptr; 1530 if (const MachineFunction *MF = getMFIfAvailable(*this)) { 1531 F = &MF->getFunction(); 1532 M = F->getParent(); 1533 if (!TII) 1534 TII = MF->getSubtarget().getInstrInfo(); 1535 } 1536 1537 ModuleSlotTracker MST(M); 1538 if (F) 1539 MST.incorporateFunction(*F); 1540 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII); 1541} 1542 1543void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, 1544 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc, 1545 bool AddNewLine, const TargetInstrInfo *TII) const { 1546 // We can be a bit tidier if we know the MachineFunction. 1547 const TargetRegisterInfo *TRI = nullptr; 1548 const MachineRegisterInfo *MRI = nullptr; 1549 const TargetIntrinsicInfo *IntrinsicInfo = nullptr; 1550 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII); 1551 1552 if (isCFIInstruction()) 1553 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction"); 1554 1555 SmallBitVector PrintedTypes(8); 1556 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies(); 1557 auto getTiedOperandIdx = [&](unsigned OpIdx) { 1558 if (!ShouldPrintRegisterTies) 1559 return 0U; 1560 const MachineOperand &MO = getOperand(OpIdx); 1561 if (MO.isReg() && MO.isTied() && !MO.isDef()) 1562 return findTiedOperandIdx(OpIdx); 1563 return 0U; 1564 }; 1565 unsigned StartOp = 0; 1566 unsigned e = getNumOperands(); 1567 1568 // Print explicitly defined operands on the left of an assignment syntax. 1569 while (StartOp < e) { 1570 const MachineOperand &MO = getOperand(StartOp); 1571 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) 1572 break; 1573 1574 if (StartOp != 0) 1575 OS << ", "; 1576 1577 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{}; 1578 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp); 1579 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone, 1580 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); 1581 ++StartOp; 1582 } 1583 1584 if (StartOp != 0) 1585 OS << " = "; 1586 1587 if (getFlag(MachineInstr::FrameSetup)) 1588 OS << "frame-setup "; 1589 if (getFlag(MachineInstr::FrameDestroy)) 1590 OS << "frame-destroy "; 1591 if (getFlag(MachineInstr::FmNoNans)) 1592 OS << "nnan "; 1593 if (getFlag(MachineInstr::FmNoInfs)) 1594 OS << "ninf "; 1595 if (getFlag(MachineInstr::FmNsz)) 1596 OS << "nsz "; 1597 if (getFlag(MachineInstr::FmArcp)) 1598 OS << "arcp "; 1599 if (getFlag(MachineInstr::FmContract)) 1600 OS << "contract "; 1601 if (getFlag(MachineInstr::FmAfn)) 1602 OS << "afn "; 1603 if (getFlag(MachineInstr::FmReassoc)) 1604 OS << "reassoc "; 1605 if (getFlag(MachineInstr::NoUWrap)) 1606 OS << "nuw "; 1607 if (getFlag(MachineInstr::NoSWrap)) 1608 OS << "nsw "; 1609 if (getFlag(MachineInstr::IsExact)) 1610 OS << "exact "; 1611 if (getFlag(MachineInstr::NoFPExcept)) 1612 OS << "nofpexcept "; 1613 if (getFlag(MachineInstr::NoMerge)) 1614 OS << "nomerge "; 1615 1616 // Print the opcode name. 1617 if (TII) 1618 OS << TII->getName(getOpcode()); 1619 else 1620 OS << "UNKNOWN"; 1621 1622 if (SkipOpers) 1623 return; 1624 1625 // Print the rest of the operands. 1626 bool FirstOp = true; 1627 unsigned AsmDescOp = ~0u; 1628 unsigned AsmOpCount = 0; 1629 1630 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { 1631 // Print asm string. 1632 OS << " "; 1633 const unsigned OpIdx = InlineAsm::MIOp_AsmString; 1634 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{}; 1635 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx); 1636 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone, 1637 ShouldPrintRegisterTies, TiedOperandIdx, TRI, 1638 IntrinsicInfo); 1639 1640 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack 1641 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1642 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1643 OS << " [sideeffect]"; 1644 if (ExtraInfo & InlineAsm::Extra_MayLoad) 1645 OS << " [mayload]"; 1646 if (ExtraInfo & InlineAsm::Extra_MayStore) 1647 OS << " [maystore]"; 1648 if (ExtraInfo & InlineAsm::Extra_IsConvergent) 1649 OS << " [isconvergent]"; 1650 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 1651 OS << " [alignstack]"; 1652 if (getInlineAsmDialect() == InlineAsm::AD_ATT) 1653 OS << " [attdialect]"; 1654 if (getInlineAsmDialect() == InlineAsm::AD_Intel) 1655 OS << " [inteldialect]"; 1656 1657 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand; 1658 FirstOp = false; 1659 } 1660 1661 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1662 const MachineOperand &MO = getOperand(i); 1663 1664 if (FirstOp) FirstOp = false; else OS << ","; 1665 OS << " "; 1666 1667 if (isDebugValue() && MO.isMetadata()) { 1668 // Pretty print DBG_VALUE instructions. 1669 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata()); 1670 if (DIV && !DIV->getName().empty()) 1671 OS << "!\"" << DIV->getName() << '\"'; 1672 else { 1673 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{}; 1674 unsigned TiedOperandIdx = getTiedOperandIdx(i); 1675 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone, 1676 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); 1677 } 1678 } else if (isDebugLabel() && MO.isMetadata()) { 1679 // Pretty print DBG_LABEL instructions. 1680 auto *DIL = dyn_cast<DILabel>(MO.getMetadata()); 1681 if (DIL && !DIL->getName().empty()) 1682 OS << "\"" << DIL->getName() << '\"'; 1683 else { 1684 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{}; 1685 unsigned TiedOperandIdx = getTiedOperandIdx(i); 1686 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone, 1687 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); 1688 } 1689 } else if (i == AsmDescOp && MO.isImm()) { 1690 // Pretty print the inline asm operand descriptor. 1691 OS << '$' << AsmOpCount++; 1692 unsigned Flag = MO.getImm(); 1693 OS << ":["; 1694 OS << InlineAsm::getKindName(InlineAsm::getKind(Flag)); 1695 1696 unsigned RCID = 0; 1697 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) && 1698 InlineAsm::hasRegClassConstraint(Flag, RCID)) { 1699 if (TRI) { 1700 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); 1701 } else 1702 OS << ":RC" << RCID; 1703 } 1704 1705 if (InlineAsm::isMemKind(Flag)) { 1706 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag); 1707 OS << ":" << InlineAsm::getMemConstraintName(MCID); 1708 } 1709 1710 unsigned TiedTo = 0; 1711 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) 1712 OS << " tiedto:$" << TiedTo; 1713 1714 OS << ']'; 1715 1716 // Compute the index of the next operand descriptor. 1717 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); 1718 } else { 1719 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{}; 1720 unsigned TiedOperandIdx = getTiedOperandIdx(i); 1721 if (MO.isImm() && isOperandSubregIdx(i)) 1722 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI); 1723 else 1724 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone, 1725 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); 1726 } 1727 } 1728 1729 // Print any optional symbols attached to this instruction as-if they were 1730 // operands. 1731 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) { 1732 if (!FirstOp) { 1733 FirstOp = false; 1734 OS << ','; 1735 } 1736 OS << " pre-instr-symbol "; 1737 MachineOperand::printSymbol(OS, *PreInstrSymbol); 1738 } 1739 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) { 1740 if (!FirstOp) { 1741 FirstOp = false; 1742 OS << ','; 1743 } 1744 OS << " post-instr-symbol "; 1745 MachineOperand::printSymbol(OS, *PostInstrSymbol); 1746 } 1747 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) { 1748 if (!FirstOp) { 1749 FirstOp = false; 1750 OS << ','; 1751 } 1752 OS << " heap-alloc-marker "; 1753 HeapAllocMarker->printAsOperand(OS, MST); 1754 } 1755 1756 if (!SkipDebugLoc) { 1757 if (const DebugLoc &DL = getDebugLoc()) { 1758 if (!FirstOp) 1759 OS << ','; 1760 OS << " debug-location "; 1761 DL->printAsOperand(OS, MST); 1762 } 1763 } 1764 1765 if (!memoperands_empty()) { 1766 SmallVector<StringRef, 0> SSNs; 1767 const LLVMContext *Context = nullptr; 1768 std::unique_ptr<LLVMContext> CtxPtr; 1769 const MachineFrameInfo *MFI = nullptr; 1770 if (const MachineFunction *MF = getMFIfAvailable(*this)) { 1771 MFI = &MF->getFrameInfo(); 1772 Context = &MF->getFunction().getContext(); 1773 } else { 1774 CtxPtr = std::make_unique<LLVMContext>(); 1775 Context = CtxPtr.get(); 1776 } 1777 1778 OS << " :: "; 1779 bool NeedComma = false; 1780 for (const MachineMemOperand *Op : memoperands()) { 1781 if (NeedComma) 1782 OS << ", "; 1783 Op->print(OS, MST, SSNs, *Context, MFI, TII); 1784 NeedComma = true; 1785 } 1786 } 1787 1788 if (SkipDebugLoc) 1789 return; 1790 1791 bool HaveSemi = false; 1792 1793 // Print debug location information. 1794 if (const DebugLoc &DL = getDebugLoc()) { 1795 if (!HaveSemi) { 1796 OS << ';'; 1797 HaveSemi = true; 1798 } 1799 OS << ' '; 1800 DL.print(OS); 1801 } 1802 1803 // Print extra comments for DEBUG_VALUE. 1804 if (isDebugValue() && getDebugVariableOp().isMetadata()) { 1805 if (!HaveSemi) { 1806 OS << ";"; 1807 HaveSemi = true; 1808 } 1809 auto *DV = getDebugVariable(); 1810 OS << " line no:" << DV->getLine(); 1811 if (isIndirectDebugValue()) 1812 OS << " indirect"; 1813 } 1814 // TODO: DBG_LABEL 1815 1816 if (AddNewLine) 1817 OS << '\n'; 1818} 1819 1820bool MachineInstr::addRegisterKilled(Register IncomingReg, 1821 const TargetRegisterInfo *RegInfo, 1822 bool AddIfNotFound) { 1823 bool isPhysReg = Register::isPhysicalRegister(IncomingReg); 1824 bool hasAliases = isPhysReg && 1825 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1826 bool Found = false; 1827 SmallVector<unsigned,4> DeadOps; 1828 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1829 MachineOperand &MO = getOperand(i); 1830 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1831 continue; 1832 1833 // DEBUG_VALUE nodes do not contribute to code generation and should 1834 // always be ignored. Failure to do so may result in trying to modify 1835 // KILL flags on DEBUG_VALUE nodes. 1836 if (MO.isDebug()) 1837 continue; 1838 1839 Register Reg = MO.getReg(); 1840 if (!Reg) 1841 continue; 1842 1843 if (Reg == IncomingReg) { 1844 if (!Found) { 1845 if (MO.isKill()) 1846 // The register is already marked kill. 1847 return true; 1848 if (isPhysReg && isRegTiedToDefOperand(i)) 1849 // Two-address uses of physregs must not be marked kill. 1850 return true; 1851 MO.setIsKill(); 1852 Found = true; 1853 } 1854 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) { 1855 // A super-register kill already exists. 1856 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1857 return true; 1858 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1859 DeadOps.push_back(i); 1860 } 1861 } 1862 1863 // Trim unneeded kill operands. 1864 while (!DeadOps.empty()) { 1865 unsigned OpIdx = DeadOps.back(); 1866 if (getOperand(OpIdx).isImplicit() && 1867 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0)) 1868 RemoveOperand(OpIdx); 1869 else 1870 getOperand(OpIdx).setIsKill(false); 1871 DeadOps.pop_back(); 1872 } 1873 1874 // If not found, this means an alias of one of the operands is killed. Add a 1875 // new implicit operand if required. 1876 if (!Found && AddIfNotFound) { 1877 addOperand(MachineOperand::CreateReg(IncomingReg, 1878 false /*IsDef*/, 1879 true /*IsImp*/, 1880 true /*IsKill*/)); 1881 return true; 1882 } 1883 return Found; 1884} 1885 1886void MachineInstr::clearRegisterKills(Register Reg, 1887 const TargetRegisterInfo *RegInfo) { 1888 if (!Register::isPhysicalRegister(Reg)) 1889 RegInfo = nullptr; 1890 for (MachineOperand &MO : operands()) { 1891 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) 1892 continue; 1893 Register OpReg = MO.getReg(); 1894 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) 1895 MO.setIsKill(false); 1896 } 1897} 1898 1899bool MachineInstr::addRegisterDead(Register Reg, 1900 const TargetRegisterInfo *RegInfo, 1901 bool AddIfNotFound) { 1902 bool isPhysReg = Register::isPhysicalRegister(Reg); 1903 bool hasAliases = isPhysReg && 1904 MCRegAliasIterator(Reg, RegInfo, false).isValid(); 1905 bool Found = false; 1906 SmallVector<unsigned,4> DeadOps; 1907 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1908 MachineOperand &MO = getOperand(i); 1909 if (!MO.isReg() || !MO.isDef()) 1910 continue; 1911 Register MOReg = MO.getReg(); 1912 if (!MOReg) 1913 continue; 1914 1915 if (MOReg == Reg) { 1916 MO.setIsDead(); 1917 Found = true; 1918 } else if (hasAliases && MO.isDead() && 1919 Register::isPhysicalRegister(MOReg)) { 1920 // There exists a super-register that's marked dead. 1921 if (RegInfo->isSuperRegister(Reg, MOReg)) 1922 return true; 1923 if (RegInfo->isSubRegister(Reg, MOReg)) 1924 DeadOps.push_back(i); 1925 } 1926 } 1927 1928 // Trim unneeded dead operands. 1929 while (!DeadOps.empty()) { 1930 unsigned OpIdx = DeadOps.back(); 1931 if (getOperand(OpIdx).isImplicit() && 1932 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0)) 1933 RemoveOperand(OpIdx); 1934 else 1935 getOperand(OpIdx).setIsDead(false); 1936 DeadOps.pop_back(); 1937 } 1938 1939 // If not found, this means an alias of one of the operands is dead. Add a 1940 // new implicit operand if required. 1941 if (Found || !AddIfNotFound) 1942 return Found; 1943 1944 addOperand(MachineOperand::CreateReg(Reg, 1945 true /*IsDef*/, 1946 true /*IsImp*/, 1947 false /*IsKill*/, 1948 true /*IsDead*/)); 1949 return true; 1950} 1951 1952void MachineInstr::clearRegisterDeads(Register Reg) { 1953 for (MachineOperand &MO : operands()) { 1954 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg) 1955 continue; 1956 MO.setIsDead(false); 1957 } 1958} 1959 1960void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) { 1961 for (MachineOperand &MO : operands()) { 1962 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0) 1963 continue; 1964 MO.setIsUndef(IsUndef); 1965 } 1966} 1967 1968void MachineInstr::addRegisterDefined(Register Reg, 1969 const TargetRegisterInfo *RegInfo) { 1970 if (Register::isPhysicalRegister(Reg)) { 1971 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo); 1972 if (MO) 1973 return; 1974 } else { 1975 for (const MachineOperand &MO : operands()) { 1976 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() && 1977 MO.getSubReg() == 0) 1978 return; 1979 } 1980 } 1981 addOperand(MachineOperand::CreateReg(Reg, 1982 true /*IsDef*/, 1983 true /*IsImp*/)); 1984} 1985 1986void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs, 1987 const TargetRegisterInfo &TRI) { 1988 bool HasRegMask = false; 1989 for (MachineOperand &MO : operands()) { 1990 if (MO.isRegMask()) { 1991 HasRegMask = true; 1992 continue; 1993 } 1994 if (!MO.isReg() || !MO.isDef()) continue; 1995 Register Reg = MO.getReg(); 1996 if (!Reg.isPhysical()) 1997 continue; 1998 // If there are no uses, including partial uses, the def is dead. 1999 if (llvm::none_of(UsedRegs, 2000 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); })) 2001 MO.setIsDead(); 2002 } 2003 2004 // This is a call with a register mask operand. 2005 // Mask clobbers are always dead, so add defs for the non-dead defines. 2006 if (HasRegMask) 2007 for (ArrayRef<Register>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 2008 I != E; ++I) 2009 addRegisterDefined(*I, &TRI); 2010} 2011 2012unsigned 2013MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { 2014 // Build up a buffer of hash code components. 2015 SmallVector<size_t, 16> HashComponents; 2016 HashComponents.reserve(MI->getNumOperands() + 1); 2017 HashComponents.push_back(MI->getOpcode()); 2018 for (const MachineOperand &MO : MI->operands()) { 2019 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg())) 2020 continue; // Skip virtual register defs. 2021 2022 HashComponents.push_back(hash_value(MO)); 2023 } 2024 return hash_combine_range(HashComponents.begin(), HashComponents.end()); 2025} 2026 2027void MachineInstr::emitError(StringRef Msg) const { 2028 // Find the source location cookie. 2029 unsigned LocCookie = 0; 2030 const MDNode *LocMD = nullptr; 2031 for (unsigned i = getNumOperands(); i != 0; --i) { 2032 if (getOperand(i-1).isMetadata() && 2033 (LocMD = getOperand(i-1).getMetadata()) && 2034 LocMD->getNumOperands() != 0) { 2035 if (const ConstantInt *CI = 2036 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) { 2037 LocCookie = CI->getZExtValue(); 2038 break; 2039 } 2040 } 2041 } 2042 2043 if (const MachineBasicBlock *MBB = getParent()) 2044 if (const MachineFunction *MF = MBB->getParent()) 2045 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg); 2046 report_fatal_error(Msg); 2047} 2048 2049MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL, 2050 const MCInstrDesc &MCID, bool IsIndirect, 2051 Register Reg, const MDNode *Variable, 2052 const MDNode *Expr) { 2053 assert(isa<DILocalVariable>(Variable) && "not a variable"); 2054 assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); 2055 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && 2056 "Expected inlined-at fields to agree"); 2057 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug); 2058 if (IsIndirect) 2059 MIB.addImm(0U); 2060 else 2061 MIB.addReg(0U, RegState::Debug); 2062 return MIB.addMetadata(Variable).addMetadata(Expr); 2063} 2064 2065MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL, 2066 const MCInstrDesc &MCID, bool IsIndirect, 2067 MachineOperand &MO, const MDNode *Variable, 2068 const MDNode *Expr) { 2069 assert(isa<DILocalVariable>(Variable) && "not a variable"); 2070 assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); 2071 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && 2072 "Expected inlined-at fields to agree"); 2073 if (MO.isReg()) 2074 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr); 2075 2076 auto MIB = BuildMI(MF, DL, MCID).add(MO); 2077 if (IsIndirect) 2078 MIB.addImm(0U); 2079 else 2080 MIB.addReg(0U, RegState::Debug); 2081 return MIB.addMetadata(Variable).addMetadata(Expr); 2082 } 2083 2084MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB, 2085 MachineBasicBlock::iterator I, 2086 const DebugLoc &DL, const MCInstrDesc &MCID, 2087 bool IsIndirect, Register Reg, 2088 const MDNode *Variable, const MDNode *Expr) { 2089 MachineFunction &MF = *BB.getParent(); 2090 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr); 2091 BB.insert(I, MI); 2092 return MachineInstrBuilder(MF, MI); 2093} 2094 2095MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB, 2096 MachineBasicBlock::iterator I, 2097 const DebugLoc &DL, const MCInstrDesc &MCID, 2098 bool IsIndirect, MachineOperand &MO, 2099 const MDNode *Variable, const MDNode *Expr) { 2100 MachineFunction &MF = *BB.getParent(); 2101 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr); 2102 BB.insert(I, MI); 2103 return MachineInstrBuilder(MF, *MI); 2104} 2105 2106/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot. 2107/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE. 2108static const DIExpression *computeExprForSpill(const MachineInstr &MI) { 2109 assert(MI.getOperand(0).isReg() && "can't spill non-register"); 2110 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && 2111 "Expected inlined-at fields to agree"); 2112 2113 const DIExpression *Expr = MI.getDebugExpression(); 2114 if (MI.isIndirectDebugValue()) { 2115 assert(MI.getDebugOffset().getImm() == 0 && 2116 "DBG_VALUE with nonzero offset"); 2117 Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore); 2118 } 2119 return Expr; 2120} 2121 2122MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB, 2123 MachineBasicBlock::iterator I, 2124 const MachineInstr &Orig, 2125 int FrameIndex) { 2126 const DIExpression *Expr = computeExprForSpill(Orig); 2127 return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc()) 2128 .addFrameIndex(FrameIndex) 2129 .addImm(0U) 2130 .addMetadata(Orig.getDebugVariable()) 2131 .addMetadata(Expr); 2132} 2133 2134void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) { 2135 const DIExpression *Expr = computeExprForSpill(Orig); 2136 Orig.getDebugOperand(0).ChangeToFrameIndex(FrameIndex); 2137 Orig.getDebugOffset().ChangeToImmediate(0U); 2138 Orig.getDebugExpressionOp().setMetadata(Expr); 2139} 2140 2141void MachineInstr::collectDebugValues( 2142 SmallVectorImpl<MachineInstr *> &DbgValues) { 2143 MachineInstr &MI = *this; 2144 if (!MI.getOperand(0).isReg()) 2145 return; 2146 2147 MachineBasicBlock::iterator DI = MI; ++DI; 2148 for (MachineBasicBlock::iterator DE = MI.getParent()->end(); 2149 DI != DE; ++DI) { 2150 if (!DI->isDebugValue()) 2151 return; 2152 if (DI->getDebugOperandForReg(MI.getOperand(0).getReg())) 2153 DbgValues.push_back(&*DI); 2154 } 2155} 2156 2157void MachineInstr::changeDebugValuesDefReg(Register Reg) { 2158 // Collect matching debug values. 2159 SmallVector<MachineInstr *, 2> DbgValues; 2160 2161 if (!getOperand(0).isReg()) 2162 return; 2163 2164 Register DefReg = getOperand(0).getReg(); 2165 auto *MRI = getRegInfo(); 2166 for (auto &MO : MRI->use_operands(DefReg)) { 2167 auto *DI = MO.getParent(); 2168 if (!DI->isDebugValue()) 2169 continue; 2170 if (DI->getDebugOperandForReg(DefReg)) { 2171 DbgValues.push_back(DI); 2172 } 2173 } 2174 2175 // Propagate Reg to debug value instructions. 2176 for (auto *DBI : DbgValues) 2177 DBI->getDebugOperandForReg(DefReg)->setReg(Reg); 2178} 2179 2180using MMOList = SmallVector<const MachineMemOperand *, 2>; 2181 2182static unsigned getSpillSlotSize(const MMOList &Accesses, 2183 const MachineFrameInfo &MFI) { 2184 unsigned Size = 0; 2185 for (auto A : Accesses) 2186 if (MFI.isSpillSlotObjectIndex( 2187 cast<FixedStackPseudoSourceValue>(A->getPseudoValue()) 2188 ->getFrameIndex())) 2189 Size += A->getSize(); 2190 return Size; 2191} 2192 2193Optional<unsigned> 2194MachineInstr::getSpillSize(const TargetInstrInfo *TII) const { 2195 int FI; 2196 if (TII->isStoreToStackSlotPostFE(*this, FI)) { 2197 const MachineFrameInfo &MFI = getMF()->getFrameInfo(); 2198 if (MFI.isSpillSlotObjectIndex(FI)) 2199 return (*memoperands_begin())->getSize(); 2200 } 2201 return None; 2202} 2203 2204Optional<unsigned> 2205MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const { 2206 MMOList Accesses; 2207 if (TII->hasStoreToStackSlot(*this, Accesses)) 2208 return getSpillSlotSize(Accesses, getMF()->getFrameInfo()); 2209 return None; 2210} 2211 2212Optional<unsigned> 2213MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const { 2214 int FI; 2215 if (TII->isLoadFromStackSlotPostFE(*this, FI)) { 2216 const MachineFrameInfo &MFI = getMF()->getFrameInfo(); 2217 if (MFI.isSpillSlotObjectIndex(FI)) 2218 return (*memoperands_begin())->getSize(); 2219 } 2220 return None; 2221} 2222 2223Optional<unsigned> 2224MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const { 2225 MMOList Accesses; 2226 if (TII->hasLoadFromStackSlot(*this, Accesses)) 2227 return getSpillSlotSize(Accesses, getMF()->getFrameInfo()); 2228 return None; 2229} 2230