Searched refs:DestVT (Results 1 - 20 of 20) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCallingConvEmitter.cpp235 MVT::SimpleValueType DestVT = getValueType(DestTy); local
236 O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n";
237 if (MVT(DestVT).isFloatingPoint()) {
249 MVT::SimpleValueType DestVT = getValueType(DestTy); local
250 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n";
251 if (MVT(DestVT).isFloatingPoint()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
999 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
1001 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1078 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
1080 if (SrcVT != MVT::f64 || DestVT !
1210 MVT DestVT = VA.getLocVT(); local
1218 MVT DestVT = VA.getLocVT(); local
1751 MVT DestVT = VA.getValVT(); local
1783 EVT SrcVT, DestVT; local
1821 MVT DestVT = DestEVT.getSimpleVT(); local
1830 emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1849 emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1864 emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1873 emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg) argument
1895 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1909 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp173 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
963 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
965 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
981 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
983 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1273 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
1277 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1445 MVT DestVT = VA.getLocVT(); local
1447 (DestVT
1457 MVT DestVT = VA.getLocVT(); local
1512 MVT DestVT = VA.getValVT(); local
1751 MVT DestVT = VA.getLocVT(); local
1804 PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, bool IsZExt) argument
1876 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
1915 MVT DestVT = DestEVT.getSimpleVT(); local
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H A DPPCISelLowering.h887 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
H A DPPCISelLowering.cpp9003 const SDLoc &dl, EVT DestVT = MVT::Other) {
9004 if (DestVT == MVT::Other) DestVT = Op.getValueType();
9005 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
9013 EVT DestVT = MVT::Other) {
9014 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
9015 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
9023 EVT DestVT = MVT::Other) {
9024 if (DestVT
16332 isFPExtFree(EVT DestVT, EVT SrcVT) const argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp233 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
234 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2871 MVT DestVT; local
2872 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2886 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2888 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2891 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2893 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2896 DestVT
2904 MVT DestVT; local
3090 MVT DestVT = VA.getLocVT(); local
3100 MVT DestVT = VA.getLocVT(); local
3959 MVT DestVT = DestEVT.getSimpleVT(); local
4012 emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) argument
4421 emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool IsZExt) argument
[all...]
H A DAArch64ISelLowering.cpp7066 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); local
7073 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
7089 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7095 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7100 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7103 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7107 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
14136 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, local
14139 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, DestVT, Opnds);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp204 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1737 EVT DestVT = TLI.getValueType(DL, I->getType(), true); local
1741 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1952 MVT DestVT = VA.getLocVT(); local
1953 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
1955 ArgVT = DestVT;
1961 MVT DestVT = VA.getLocVT(); local
1962 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZEx
2040 MVT DestVT = RVLocs[0].getValVT(); local
2128 MVT DestVT = VA.getValVT(); local
2580 EVT SrcVT, DestVT; local
2598 ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt) argument
2755 MVT DestVT = DestEVT.getSimpleVT(); local
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H A DARMISelLowering.cpp7778 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); local
7786 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
7802 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7808 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7813 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7816 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
7819 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp161 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
163 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
872 EVT DestVT = Node->getValueType(0);
873 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
899 EVT IDestVT = DestVT.changeTypeToInteger();
904 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
1751 /// a load from the stack slot to DestVT, extending it if needed.
1754 EVT DestVT, const SDLoc &dl) {
1755 return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode());
1759 EVT DestVT, cons
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H A DLegalizeTypes.cpp888 EVT DestVT) {
895 Align DestAlign = DAG.getReducedAlign(DestVT, /*UseABI=*/false);
904 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), Align);
887 CreateStackStoreLoad(SDValue Op, EVT DestVT) argument
H A DSelectionDAGBuilder.cpp3128 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), local
3130 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
3147 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), local
3149 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
3291 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), local
3293 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3300 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), local
3302 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
3309 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), local
3311 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT,
3319 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); local
3328 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), local
3336 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), local
3344 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), local
3352 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), local
3360 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), local
3370 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), local
3384 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); local
3394 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), local
3417 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType()); local
[all...]
H A DLegalizeVectorTypes.cpp351 EVT DestVT = N->getValueType(0).getVectorElementType(); local
369 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op, N->getFlags());
1772 EVT DestVT = N->getValueType(0); local
1774 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1790 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
H A DLegalizeTypes.h220 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h2213 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2214 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
2219 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2221 AddPromotedToType(Opc, OrigVT, DestVT);
2621 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { argument
2622 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2631 EVT DestVT, EVT SrcVT) const {
2632 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2634 return isFPExtFree(DestVT, SrcVT);
2630 isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp918 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
925 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
2492 EVT DestVT = Op.getValueType(); local
2497 if (DestVT == MVT::f16)
2503 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext);
2508 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) {
2519 if (DestVT == MVT::f32)
2522 assert(DestVT == MVT::f64);
2528 EVT DestVT = Op.getValueType(); local
2534 if (DestVT
3908 EVT DestVT = N->getValueType(0); local
[all...]
H A DSIISelLowering.h236 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT,
H A DSIISelLowering.cpp867 EVT DestVT, EVT SrcVT) const {
870 DestVT.getScalarType() == MVT::f32 &&
866 isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const argument
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp993 MVT DestVT = TLI->getRegisterType(NewVT); local
994 RegisterVT = DestVT;
995 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
997 (LaneSizeInBits / DestVT.getScalarSizeInBits().getFixedSize());
1475 MVT DestVT = getRegisterType(Context, NewVT); local
1476 RegisterVT = DestVT;
1478 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1483 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp19241 MVT DestVT = Cast.getSimpleValueType();
19251 MVT ToVT = MVT::getVectorVT(DestVT, NumEltsInXMM);
19271 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, DestVT, VCast,
23391 MVT DestVT = VT == MVT::v2i64 ? MVT::v4i32 : VT;
23393 unsigned DestWidth = DestVT.getScalarSizeInBits();
23397 unsigned DestElts = DestVT.getVectorNumElements();
23406 Curr = DAG.getBitcast(DestVT, Curr);
23409 SignExt = DAG.getNode(X86ISD::VSRAI, dl, DestVT, Curr,
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