Lines Matching refs:DestVT
233 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
234 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2871 MVT DestVT;
2872 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2886 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2888 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2891 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2893 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2896 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
2904 MVT DestVT;
2905 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2908 if (DestVT == MVT::f16)
2911 assert((DestVT == MVT::f32 || DestVT == MVT::f64) &&
2933 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
2935 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
2938 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
2940 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
2943 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
3090 MVT DestVT = VA.getLocVT();
3092 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
3100 MVT DestVT = VA.getLocVT();
3102 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
3911 MVT DestVT = VA.getValVT();
3913 if (RVVT != DestVT) {
3921 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
3959 MVT DestVT = DestEVT.getSimpleVT();
3964 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
3965 DestVT != MVT::i1)
3981 switch (DestVT.SimpleTy) {
4012 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
4013 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
4014 DestVT == MVT::i64) &&
4017 if (DestVT == MVT::i8 || DestVT == MVT::i16)
4018 DestVT = MVT::i32;
4023 if (DestVT == MVT::i64) {
4036 if (DestVT == MVT::i64) {
4421 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
4423 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
4426 // DestVT are odd things, so test to make sure that they are both types we can
4427 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
4429 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
4430 (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
4442 return emiti1Ext(SrcReg, DestVT, IsZExt);
4444 if (DestVT == MVT::i64)
4451 if (DestVT == MVT::i64)
4458 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
4465 if (DestVT == MVT::i8 || DestVT == MVT::i16)
4466 DestVT = MVT::i32;
4467 else if (DestVT == MVT::i64) {
4478 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4643 MVT DestVT = DestEVT.getSimpleVT();
4644 if (DestVT != MVT::i64 && DestVT != MVT::i32)
4648 bool Is64bit = (DestVT == MVT::i64);
4671 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;